== Series Details ==
Series: Non-interface changing GuC CTBs updates (rev2)
URL : https://patchwork.freedesktop.org/series/90552/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10133 -> Patchwork_20196
Summary
---
**S
On 5/25/21 5:48 PM, Christian König wrote:
Am 25.05.21 um 12:07 schrieb Thomas Hellström:
On Tue, 2021-05-25 at 10:58 +0100, Matthew Auld wrote:
On Tue, 25 May 2021 at 10:32, Thomas Hellström
wrote:
On 5/25/21 11:18 AM, Matthew Auld wrote:
On Fri, 21 May 2021 at 16:33, Thomas Hellström
== Series Details ==
Series: drm/i915/gt: Introduce timeslicing for userspace
URL : https://patchwork.freedesktop.org/series/90568/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10133_full -> Patchwork_20195_full
Summary
--
On ADL-P, it's possible to enable the stream splitter on pipe B in
addition to pipe A.
Bspec: 50174
Cc: Uma Shankar
Cc: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_ddi.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/d
On 25/05/2021 18:52, Matthew Brost wrote:
On Tue, May 25, 2021 at 11:16:12AM +0100, Tvrtko Ursulin wrote:
On 06/05/2021 20:14, Matthew Brost wrote:
From: John Harrison
The serial number tracking of engines happens at the backend of
request submission and was expecting to only be given phys
If the panel is 12bpc then Dithering is not enabled in the Legacy
dithering block , instead its Enabled after the C1 CC1 pipe post
color space conversion.For a 6bpc pannel Dithering is enabled in
Legacy block.
Nischal Varide (1):
drm/i915/xelpd: Enabling dithering after the CC1
drivers/gpu/drm
If the panel is 12bpc then Dithering is not enabled in the Legacy
dithering block , instead its Enabled after the C1 CC1 pipe post
color space conversion.For a 6bpc pannel Dithering is enabled in
Legacy block.
Signed-off-by: Nischal Varide
---
drivers/gpu/drm/i915/display/intel_color.c | 15 ++
On 25/05/2021 18:21, Matthew Brost wrote:
On Tue, May 25, 2021 at 10:21:00AM +0100, Tvrtko Ursulin wrote:
On 06/05/2021 20:13, Matthew Brost wrote:
Add non blocking CTB send function, intel_guc_send_nb. In order to
support a non blocking CTB send function a spin lock is needed to
protect the
If the panel is 12bpc then Dithering is not enabled in the Legacy
dithering block , instead its Enabled after the C1 CC1 pipe post
color space conversion.For a 6bpc pannel Dithering is enabled in
Legacy block.
Signed-off-by: Nischal Varide
---
drivers/gpu/drm/i915/display/intel_color.c | 15 ++
If the panel is 12bpc then Dithering is not enabled in the Legacy
dithering block , instead its Enabled after the C1 CC1 pipe post
color space conversion.For a 6bpc pannel Dithering is enabled in
Legacy block.
Nischal Varide (1):
drm/i915/xelpd: Enabling dithering after the CC1
drivers/gpu/drm
On 25/05/2021 18:07, Matthew Brost wrote:
On Tue, May 25, 2021 at 11:06:00AM +0100, Tvrtko Ursulin wrote:
On 06/05/2021 20:14, Matthew Brost wrote:
When running the GuC the GPU can't be considered idle if the GuC still
has contexts pinned. As such, a call has been added in
intel_gt_wait_for_
On 25/05/2021 18:01, Matthew Brost wrote:
On Tue, May 25, 2021 at 10:52:01AM +0100, Tvrtko Ursulin wrote:
On 06/05/2021 20:14, Matthew Brost wrote:
Disable semaphores when using GuC scheduling as semaphores are broken in
the current GuC firmware.
What is "current"? Given that the patch its
On 25/05/2021 18:15, Matthew Brost wrote:
On Tue, May 25, 2021 at 10:24:09AM +0100, Tvrtko Ursulin wrote:
On 06/05/2021 20:13, Matthew Brost wrote:
With the introduction of non-blocking CTBs more than one CTB can be in
flight at a time. Increasing the size of the CTBs should reduce how
often
== Series Details ==
Series: Non-interface changing GuC CTBs updates (rev2)
URL : https://patchwork.freedesktop.org/series/90552/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10133_full -> Patchwork_20196_full
Summary
== Series Details ==
Series: drm/i915/adl_p: enable MSO on pipe B
URL : https://patchwork.freedesktop.org/series/90579/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10133 -> Patchwork_20197
Summary
---
**SUCCESS**
The WA requires the following procedure for VDBox SFC reset:
If (MFX-SFC usage is 1) {
1.Issue a MFX-SFC forced lock
2.Wait for MFX-SFC forced lock ack
3.Check the MFX-SFC usage bit
If (MFX-SFC usage bit is 1)
Reset VDBOX and SFC
else
Need an ack for push to intel gt branch. The patch has already been
reviewed by Daniele.
Aditya Swarup (1):
drm/i915: Add Wa_14010733141
drivers/gpu/drm/i915/gt/intel_reset.c | 194 +-
drivers/gpu/drm/i915/i915_reg.h | 6 +
2 files changed, 137 insertions(+), 63
From: Tvrtko Ursulin
We have a few modparams which get conditionaly exposed based on a Kconfig
options and in most cases this also means portions of the driver
implementing the respective feature are also left out.
Align the visibility of device level and global modparams to make them
consistent
On 25/05/2021 15:47, Daniel Vetter wrote:
On Tue, May 25, 2021 at 03:19:47PM +0100, Tvrtko Ursulin wrote:
+ dri-devel as per process
On 25/05/2021 14:55, Tejas Upadhyay wrote:
v2: Only declare timeslicing if we can safely preempt userspace.
Commit message got butchered up somehow so you'l
== Series Details ==
Series: drm/i915/xelpd: Enabling dithering after the CC1
URL : https://patchwork.freedesktop.org/series/90582/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6abe80f275a2 drm/i915/xelpd: Enabling dithering after the CC1
-:27: CHECK:UNNECESSARY_PARENTHESES: U
On 06/05/2021 20:14, Matthew Brost wrote:
Disable engine barriers for unpinning with GuC. This feature isn't
needed with the GuC as it disables context scheduling before unpinning
Just isn't needed or causes a problem somehow?
which guarantees the HW will not reference the context. Hence it
If the panel is 12bpc then Dithering is not enabled in the Legacy
dithering block , instead its Enabled after the C1 CC1 pipe post
color space conversion.For a 6bpc pannel Dithering is enabled in
Legacy block.
Bhanuprakash Modem (1):
drm/i915/display/debug: Expose Dither status via debugfs
Nisc
From: Nischal Varide
If the panel is 12bpc then Dithering is not enabled in the Legacy
dithering block , instead its Enabled after the C1 CC1 pipe post
color space conversion.For a 6bpc pannel Dithering is enabled in
Legacy block.
Signed-off-by: Nischal Varide
---
drivers/gpu/drm/i915/display/
It's useful to know the dithering state & pipe bpc for IGT testing.
This patch will expose the dithering state for the crtc via a debugfs
file "dither".
Example usage: cat /sys/kernel/debug/dri/0/crtc-0/dither
Cc: Uma Shankar
Cc: Nischal Varide
Cc: Matt Roper
Signed-off-by: Bhanuprakash Modem
Am 26.05.21 um 09:39 schrieb Thomas Hellström:
[SNIP]
I think the long term goal is to use memremap all over the place, to
just not have to bother with the __iomem annotation. But to do that io-
mapping.h needs to support memremap. But for now we need to be strict
about __iomem unless we're in a
== Series Details ==
Series: drm/i915/xelpd: Enabling dithering after the CC1
URL : https://patchwork.freedesktop.org/series/90582/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10133 -> Patchwork_20198
Summary
---
*
On Wed, 2021-05-26 at 12:45 +0200, Christian König wrote:
> Am 26.05.21 um 09:39 schrieb Thomas Hellström:
> > [SNIP]
> > > > I think the long term goal is to use memremap all over the
> > > > place, to
> > > > just not have to bother with the __iomem annotation. But to do
> > > > that io-
> > > >
Am 25.05.21 um 23:17 schrieb Jason Ekstrand:
None of these helpers actually leak any RCU details to the caller. They
all assume you have a genuine reference, take the RCU read lock, and
retry if needed. Naming them with an _rcu is likely to cause callers
more panic than needed.
I'm really won
Am 25.05.21 um 23:17 schrieb Jason Ekstrand:
Modern userspace APIs like Vulkan are built on an explicit
synchronization model. This doesn't always play nicely with the
implicit synchronization used in the kernel and assumed by X11 and
Wayland. The client -> compositor half of the synchronizatio
Hi Christian,
On Wed, 26 May 2021 at 12:02, Christian König wrote:
> Am 25.05.21 um 23:17 schrieb Jason Ekstrand:
> > This new IOCTL solves this problem by allowing us to get a snapshot of
> > the implicit synchronization state of a given dma-buf in the form of a
> > sync file. It's effectively
Hi,
On poniedziałek, 3 maja 2021 19:38:17 CEST Jani Nikula wrote:
> On Thu, 29 Apr 2021, Janusz Krzysztofik
wrote:
> > Commit 7a0f9ef9703d ("drm/i915: Use drm_fb_helper_fill_info")
> > effectively changed our FB driver name from "inteldrmfb" to
> > "i915drmfb". However, we are still using the o
This is an initial patch series to move discrete memory management over to
TTM. It will be followed up shortly with adding more functionality.
The buddy allocator is temporarily removed along with its selftests and
It is replaced with the TTM range manager and some selftests are adjusted
to accoun
If the bo is idle when calling ttm_bo_pipeline_gutting(), we unnecessarily
create a ghost object and push it out to delayed destroy.
Fix this by adding a path for idle, and document the function.
Also avoid having the bo end up in a bad state vulnerable to user-space
triggered kernel BUGs if the c
The internal ttm_bo_util memcpy uses ioremap functionality, and while it
probably might be possible to use it for copying in- and out of
sglist represented io memory, using io_mem_reserve() / io_mem_free()
callbacks, that would cause problems with fault().
Instead, implement a method mapping page-b
Any sleeping dma_resv lock taken while the vma pages_mutex is held
will cause a lockdep splat.
Move the i915_gem_object_pin_pages() call out of the pages_mutex
critical section.
Signed-off-by: Thomas Hellström
Reviewed-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_vma.c | 29 +
Use fast wc memcpy for reading out of wc memory for TTM bo moves.
Cc: Dave Airlie
Cc: Christian König
Cc: Daniel Vetter
Signed-off-by: Thomas Hellström
--
v4:
- Clarify when we try drm_memcpy_from_wc_dbm (Reported by Matthew Auld)
- Be paranoid about when drm_memcpy_from_wc_dbm may fail (Repor
From: Maarten Lankhorst
The paltform should exclusively use mmap_offset, one less path to worry
about for discrete.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gp
From: Maarten Lankhorst
This allows drivers to distinguish between different types of vma_node's.
The readonly flag was unused and is thus removed.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Thomas Hellström
---
drivers/gpu/drm/drm_gem.c | 9 -
include/drm/drm_vma_manager.h | 2
We are currently sharing the VM reservation locks across a number of
gem objects with page-table memory. Since TTM will individiualize the
reservation locks when freeing objects, including accessing the shared
locks, make sure that the shared locks are not freed until that is done.
For PPGTT we add
Temporarily remove the buddy allocator and related selftests
and hook up the TTM range manager for i915 regions.
Also modify the mock region selftests somewhat to account for a
fragmenting manager.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld #v2
---
v2:
- Fix an error unwind in lm
Memcpy from wc will be used as well by TTM memcpy.
Move it to core drm, and make the interface do the right thing
even on !X86.
Cc: Christian König
Cc: Daniel Vetter
Cc: Dave Airlie
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
---
v4:
- Fix !X86 path (Reported by Matthew Auld)
--
We are calling the eviction_valuable driver callback at eviction time to
determine whether we actually can evict a buffer object.
The upcoming i915 TTM backend needs the same functionality for swapout,
and that might actually be beneficial to other drivers as well.
Add an eviction_valuable call al
Since objects can be migrated or evicted when not pinned or locked,
update the checks for lmem residency or future residency so that
the value returned is not immediately stale.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
---
v2: Simplify i915_gem_object_migratable() (Reported by M
From: Maarten Lankhorst
Use the ttm handlers for servicing page faults, and vm_access.
We do our own validation of read-only access, otherwise use the
ttm handlers as much as possible.
Because the ttm handlers expect the vma_node at vma->base, we slightly
need to massage the mmap handlers to lo
Embed a struct ttm_buffer_object into the i915 gem object, making sure
we alias the gem object part. It's a bit unfortunate that the
struct ttm_buffer_ojbect embeds a gem object since we otherwise could
make the TTM part private to the TTM backend, and use the usual
i915 gem object for the other ba
All users of this function actually want the dma segment sizes, but that's
not what's calculated. Fix that and rename the function to
i915_sg_dma_sizes to reflect what's calculated.
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_dmabuf.c | 2 +-
Most logical place to introduce TTM buffer objects is as an i915
gem object backend. We need to add some ops to account for added
functionality like delayed delete and LRU list manipulation.
Initially we support only LMEM and SYSTEM memory, but SYSTEM
(which in this case means evicted LMEM objects
== Series Details ==
Series: drm/i915/xelpd: Enabling dithering after the CC1
URL : https://patchwork.freedesktop.org/series/90583/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a7d93728c6c9 drm/i915/xelpd: Enabling dithering after the CC1
-:27: CHECK:UNNECESSARY_PARENTHESES: U
== Series Details ==
Series: drm/i915/xelpd: Enabling dithering after the CC1
URL : https://patchwork.freedesktop.org/series/90583/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10133 -> Patchwork_20199
Summary
---
*
On 26.05.2021 08:42, Matthew Brost wrote:
> From: Michal Wajdeczko
>
> In upcoming patch we will allow more CTB requests to be sent in
> parallel to the GuC for processing, so we shouldn't assume any more
> that GuC will always reply without 10ms.
>
> Use bigger value from CONFIG_DRM_I915_GUC
== Series Details ==
Series: Adding Wa_14010733141 for SFC reset
URL : https://patchwork.freedesktop.org/series/90587/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
89510e29356a drm/i915: Add Wa_14010733141
-:42: WARNING:BAD_SIGN_OFF: Co-developed-by: must be immediately follow
On 26.05.2021 08:42, Matthew Brost wrote:
> Ensure H2G buffer updates are visible before descriptor tail updates by
> inserting a barrier between the H2G buffer update and the tail. The
> barrier is simple wmb() for SMEM and is register write for LMEM. This is
> needed if more than 1 H2G can be
Hi Claire,
On Tue, May 18, 2021 at 02:42:14PM +0800, Claire Chang wrote:
> Introduce the new compatible string, restricted-dma-pool, for restricted
> DMA. One can specify the address and length of the restricted DMA memory
> region by restricted-dma-pool in the reserved-memory node.
>
> Signed-of
Am 26.05.21 um 13:31 schrieb Daniel Stone:
Hi Christian,
On Wed, 26 May 2021 at 12:02, Christian König wrote:
Am 25.05.21 um 23:17 schrieb Jason Ekstrand:
This new IOCTL solves this problem by allowing us to get a snapshot of
the implicit synchronization state of a given dma-buf in the form
Am 21.05.21 um 17:32 schrieb Thomas Hellström:
Use fast wc memcpy for reading out of wc memory for TTM bo moves.
Cc: Dave Airlie
Cc: Christian König
Cc: Daniel Vetter
Signed-off-by: Thomas Hellström
Reviewed-by: Christian König
---
drivers/gpu/drm/ttm/ttm_bo_util.c | 9 -
1 f
From: Chris Wilson
The kernel prefers enabling fbc over the initial fb, since this leads to
actual runtime power savings, so if the initial fb is deemed too big
using some heuristic, then we simply skip allocating stolen for it.
However if the kernel is not configured with fbcon then it should be
== Series Details ==
Series: Adding Wa_14010733141 for SFC reset
URL : https://patchwork.freedesktop.org/series/90587/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10133 -> Patchwork_20200
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915/params: Align visibility of device level and global modparams
URL : https://patchwork.freedesktop.org/series/90588/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include
From: Andrzej Turko
Add a wrapper for gem_create_ext ioctl (a version of gem_create that
accepts extensions). In preparation for the driver change implementing it,
a local definition of its id and necessary structs have been added,
which are to be erased as soon as those definitions
appear in the
From: Andrzej Turko
With an introduction of Local Memory concept we should be able to
allocate object in specific memory region. This patch implements
helper functions that allow this, both for querying what the device
supports and hooking into gem_create_ext to select the placements.
Co-authore
From: Andrzej Turko
Converted the test gem_exec_basic to use the memory region uapi.
Signed-off-by: Andrzej Turko
Cc: Zbigniew Kempczynski
Cc: Dominik Grzegorzek
Cc: Petri Latvala
Signed-off-by: Matthew Auld
Acked-by: Petri Latvala
---
tests/i915/gem_exec_basic.c | 50
From: Andrzej Turko
Converted the test gem_media_fill to use memory region uapi.
Signed-off-by: Andrzej Turko
Cc: Zbigniew Kempczynski
Cc: Dominik Grzegorzek
Cc: Petri Latvala
Signed-off-by: Matthew Auld
Acked-by: Petri Latvala
Reviewed-by: Zbigniew Kempczyński
---
tests/i915/gem_media_f
From: "Kalamarz, Lukasz"
As a part of local memory effort we need to make sure, that
every available memory region is covered. This patch is an attempt
for this problem. If it will be accepted it will be replicated on
each test that can actually benefit from it.
Signed-off-by: Dominik Grzegorzek
Sync to get gem_create_ext and the regions query stuff.
Generated from kernel commit: 2459e56fd8af ("drm/i915/uapi: implement
object placement extension")
Signed-off-by: Matthew Auld
Acked-by: Petri Latvala
---
include/drm-uapi/i915_drm.h | 394
1 file chan
From: Dominik Grzegorzek
As we need to add new test variants, convert the code to standard
igt_main format so those variants can be easily accommodated.
Signed-off-by: Janusz Krzysztofik
Signed-off-by: Matthew Auld
Reviewed-by: Zbigniew Kempczyński
Acked-by: Petri Latvala
---
tests/i915/gem
From: Andrzej Turko
Converted the test gem_gpgpu_fill to use memory region uapi.
Signed-off-by: Andrzej Turko
Cc: Zbigniew Kempczynski
Cc: Dominik Grzegorzek
Cc: Petri Latvala
Signed-off-by: Matthew Auld
Acked-by: Petri Latvala
Reviewed-by: Zbigniew Kempczyński
---
tests/i915/gem_gpgpu_f
Add some explicit testcases for the create_ext placements extension.
Signed-off-by: Matthew Auld
Cc: Dominik Grzegorzek
Cc: Joonas Lahtinen
Acked-by: Petri Latvala
---
tests/i915/gem_create.c | 188
1 file changed, 188 insertions(+)
diff --git a/tests
== Series Details ==
Series: drm/i915/xelpd: Enabling dithering after the CC1
URL : https://patchwork.freedesktop.org/series/90594/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
41e126e0ef3b drm/i915/xelpd: Enabling dithering after the CC1
-:27: CHECK:UNNECESSARY_PARENTHESES: U
== Series Details ==
Series: drm/i915/xelpd: Enabling dithering after the CC1
URL : https://patchwork.freedesktop.org/series/90594/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/dr
Hi,
On Wed, 26 May 2021 at 13:46, Christian König wrote:
> Am 26.05.21 um 13:31 schrieb Daniel Stone:
> > How would we insert a syncobj+val into a resv though? Like, if we pass
> > an unmaterialised syncobj+val here to insert into the resv, then an
> > implicit-only media user (or KMS) goes to sy
== Series Details ==
Series: drm/i915/adl_p: enable MSO on pipe B
URL : https://patchwork.freedesktop.org/series/90579/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_10133_full -> Patchwork_20197_full
Summary
---
**F
On Wed, May 26, 2021 at 11:29:03AM +0300, Jani Nikula wrote:
> On ADL-P, it's possible to enable the stream splitter on pipe B in
> addition to pipe A.
>
> Bspec: 50174
> Cc: Uma Shankar
> Cc: Ville Syrjälä
> Signed-off-by: Jani Nikula
I have a feeling I reviewed this already. But maybe I'm ju
Am 26.05.21 um 15:12 schrieb Daniel Stone:
Hi,
On Wed, 26 May 2021 at 13:46, Christian König wrote:
Am 26.05.21 um 13:31 schrieb Daniel Stone:
How would we insert a syncobj+val into a resv though? Like, if we pass
an unmaterialised syncobj+val here to insert into the resv, then an
implicit-
Am 25.05.21 um 17:23 schrieb Daniel Vetter:
On Tue, May 25, 2021 at 5:05 PM Christian König
wrote:
Hi Daniel,
Am 25.05.21 um 15:05 schrieb Daniel Vetter:
Hi Christian,
On Sat, May 22, 2021 at 10:30:19AM +0200, Christian König wrote:
Am 21.05.21 um 20:31 schrieb Daniel Vetter:
This works by
On Tue, 25 May 2021, Shaokun Zhang wrote:
> Function 'intel_dbuf_init' is declared twice, remove the
> repeated declaration.
>
> Cc: Jani Nikula
> Cc: Joonas Lahtinen
> Cc: Rodrigo Vivi
> Signed-off-by: Shaokun Zhang
Thanks, pushed to drm-intel-next.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/
== Series Details ==
Series: drm/i915/xelpd: Enabling dithering after the CC1
URL : https://patchwork.freedesktop.org/series/90594/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_10133 -> Patchwork_20202
Summary
---
*
Am 26.05.21 um 13:32 schrieb Thomas Hellström:
We are calling the eviction_valuable driver callback at eviction time to
determine whether we actually can evict a buffer object.
The upcoming i915 TTM backend needs the same functionality for swapout,
and that might actually be beneficial to other d
On Wed, 26 May 2021, Ville Syrjälä wrote:
> On Wed, May 26, 2021 at 11:29:03AM +0300, Jani Nikula wrote:
>> On ADL-P, it's possible to enable the stream splitter on pipe B in
>> addition to pipe A.
>>
>> Bspec: 50174
>> Cc: Uma Shankar
>> Cc: Ville Syrjälä
>> Signed-off-by: Jani Nikula
>
> I h
On Wed, May 26, 2021 at 3:32 PM Christian König
wrote:
>
> Am 25.05.21 um 17:23 schrieb Daniel Vetter:
> > On Tue, May 25, 2021 at 5:05 PM Christian König
> > wrote:
> >> Hi Daniel,
> >>
> >> Am 25.05.21 um 15:05 schrieb Daniel Vetter:
> >>> Hi Christian,
> >>>
> >>> On Sat, May 22, 2021 at 10:30
On Wed, 26 May 2021, Bhanuprakash Modem wrote:
> From: Nischal Varide
>
> If the panel is 12bpc then Dithering is not enabled in the Legacy
> dithering block , instead its Enabled after the C1 CC1 pipe post
> color space conversion.For a 6bpc pannel Dithering is enabled in
> Legacy block.
>
> Sig
On Wed, May 26, 2021 at 11:00:06AM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> We have a few modparams which get conditionaly exposed based on a Kconfig
> options and in most cases this also means portions of the driver
> implementing the respective feature are also left out.
>
> Ali
From: Chris Wilson
The name very often may be freed independently of the fence, with the
only protection being RCU. To be safe as we read the names, hold RCU.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_sw_fence.c | 2 ++
From: Chris Wilson
After calling lock_set_subclass() the lock _must_ be used, or else
lockdep's internal nr_used_locks becomes unbalanced. Extract the little
utility function to i915_utils.c
Signed-off-by: Chris Wilson
Cc: Thomas Hellström
Reviewed-by: Thomas Hellström
Signed-off-by: Tvrtko U
From: Chris Wilson
Wrap cmpxchg64 with a try_cmpxchg()-esque helper. Hiding the old-value
dance in the helper allows for cleaner code.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_utils.h | 32
From: Chris Wilson
Instead of manipulating the object's cache domain, just use the device
coherent map to write the batch buffer.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
Signed-off-by: Tvrtko Ursulin
---
.../drm/i915/gem/selftests/i915_gem_context.c| 16 +---
1
From: Chris Wilson
After the memory-region test completes, it flushes the test by calling
set-to-cpu-domain. Use the igt_flush_test as it includes a timeout,
recovery and reports and error for miscreant tests.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
Signed-off-by: Tvrtko Ursulin
From: Chris Wilson
In construction the rpcs_query batch we know that it is device coherent
and ready for execution, the set-to-gtt-domain here is redudant.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_cont
From: Chris Wilson
Let's prefer to use explicit request tracking and bounded timeouts in
our selftests.
v2 (Tvrtko):
* Rebase.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld # v1
Signed-off-by: Tvrtko Ursulin
---
.../gpu/drm/i915/gt/selftest_workarounds.c| 107 +++---
From: Chris Wilson
After running client_blt, we flush the object by changing its domain.
This causes us to wait forever instead of an bounded wait suitable for
the selftest timeout. So do an explicit wait with a suitable timeout --
which in turn means we have to limit the size of the object/blit
From: Chris Wilson
Since we dropped the use of dev->struct_mutex from inside the shrinker,
we no longer include that as part of our fs_reclaim tainting. We can
drop the i915 argument and rebrand it as a generic fs_reclaim tainter.
v2 (Tvrtko):
* Rebase.
Signed-off-by: Chris Wilson
Cc: Thomas
From: Chris Wilson
Only perform the domain transition under the object lock, and push the
required waits to outside the lock.
v2 (Tvrtko):
* Rebase.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld # v1
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_clflush.c |
From: Tvrtko Ursulin
A small chunk of dropped and mostly already reviewed patches (a couple need
review updated due rebasing I had to do) with the goal of getting to actual
fixes in the next round.
Chris Wilson (12):
drm/i915: Take rcu_read_lock for querying fence's driver/timeline
names
From: Chris Wilson
Since the vma's backing store is flushed upon first creation, remove the
manual calls to set-to-gtt-domain.
v2 (Tvrtko):
* Rebase.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld # v1
Signed-off-by: Tvrtko Ursulin
---
.../gpu/drm/i915/gem/selftests/i915_gem_mman.c
From: Chris Wilson
Set the cache coherency and status using the set-coherency helper.
Otherwise, we forget to mark the new pages as cache dirty.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 14 +-
From: Tvrtko Ursulin
We have a few modparams which get conditionaly exposed based on a Kconfig
options and in most cases this also means portions of the driver
implementing the respective feature are also left out.
Align the visibility of device level and global modparams to make them
consistent
On Wed, 26 May 2021, Bhanuprakash Modem wrote:
> It's useful to know the dithering state & pipe bpc for IGT testing.
> This patch will expose the dithering state for the crtc via a debugfs
> file "dither".
>
> Example usage: cat /sys/kernel/debug/dri/0/crtc-0/dither
>
> Cc: Uma Shankar
> Cc: Nisc
Am 26.05.21 um 13:32 schrieb Thomas Hellström:
Memcpy from wc will be used as well by TTM memcpy.
Move it to core drm, and make the interface do the right thing
even on !X86.
Cc: Christian König
Cc: Daniel Vetter
Cc: Dave Airlie
Signed-off-by: Thomas Hellström
Reviewed-by: Matthew Auld
Ac
On 26/05/2021 15:14, Tvrtko Ursulin wrote:
From: Chris Wilson
Only perform the domain transition under the object lock, and push the
required waits to outside the lock.
v2 (Tvrtko):
* Rebase.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld # v1
Signed-off-by: Tvrtko Ursulin
---
d
Am 26.05.21 um 13:32 schrieb Thomas Hellström:
If the bo is idle when calling ttm_bo_pipeline_gutting(), we unnecessarily
create a ghost object and push it out to delayed destroy.
Fix this by adding a path for idle, and document the function.
Also avoid having the bo end up in a bad state vulner
From: Chris Wilson
Only perform the domain transition under the object lock, and push the
required waits to outside the lock.
v2 (Tvrtko):
* Rebase.
v3 (Tvrtko):
* Restore write to gtt domain in coherency selftest. (Matt)
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld # v1
Signed-of
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