[Intel-gfx] [RFC PATCH 67/97] drm/i915/guc: Suspend/resume implementation for new interface

The new GuC interface introduces an MMIO H2G command, INTEL_GUC_ACTION_RESET_CLIENT, which is used to implement suspend. This MMIO tears down any active contexts generating a context reset G2H CTB for each. Once that step completes the GuC tears down the CTB channels. It is safe to suspend once thi

[Intel-gfx] [RFC PATCH 55/97] drm/i915/guc: Update intel_gt_wait_for_idle to work with GuC

When running the GuC the GPU can't be considered idle if the GuC still has contexts pinned. As such, a call has been added in intel_gt_wait_for_idle to idle the UC and in turn the GuC by waiting for the number of unpinned contexts to go to zero. Cc: John Harrison Signed-off-by: Matthew Brost ---

[Intel-gfx] [RFC PATCH 42/97] drm/i915/guc: Remove GuC stage descriptor, add lrc descriptor

Remove old GuC stage descriptor, add lrc descriptor which will be used by the new GuC interface implemented in this patch series. Cc: John Harrison Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/intel_guc.h| 4 +- drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 65

[Intel-gfx] [RFC PATCH 53/97] drm/i915/guc: Disable semaphores when using GuC scheduling

Disable semaphores when using GuC scheduling as semaphores are broken in the current GuC firmware. Cc: John Harrison Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/i9

[Intel-gfx] [RFC PATCH 73/97] drm/i915/guc: Enable GuC engine reset

From: John Harrison Clear the 'disable resets' flag to allow GuC to reset hung contexts (detected via pre-emption timeout). Signed-off-by: John Harrison Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --

[Intel-gfx] [RFC PATCH 61/97] drm/i915: Hold reference to intel_context over life of i915_request

Hold a reference to the intel_context over life of an i915_request. Without this an i915_request can exist after the context has been destroyed (e.g. request retired, context closed, but user space holds a reference to the request from an out fence). In the case of GuC submission + virtual engine,

[Intel-gfx] [RFC PATCH 57/97] drm/i915/guc: Add several request trace points

Add trace points for request dependencies and GuC submit. Extended existing request trace points to include submit fence value,, guc_id, and ring tail value. Cc: John Harrison Signed-off-by: Matthew Brost --- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 3 ++ drivers/gpu/drm/i915/i915_reque

[Intel-gfx] [RFC PATCH 49/97] drm/i915/guc: Disable engine barriers with GuC during unpin

Disable engine barriers for unpinning with GuC. This feature isn't needed with the GuC as it disables context scheduling before unpinning which guarantees the HW will not reference the context. Hence it is not necessary to defer unpinning until a kernel context request completes on each engine in t

[Intel-gfx] [RFC PATCH 18/97] drm/i915/guc: Don't receive all G2H messages in irq handler

From: Michal Wajdeczko In irq handler try to receive just single G2H message, let other messages to be received from tasklet. Signed-off-by: Michal Wajdeczko Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 67 --- drivers/gpu/drm/i915/gt/uc/int

[Intel-gfx] [RFC PATCH 65/97] drm/i915: Reset GPU immediately if submission is disabled

If submission is disabled by the backend for any reason, reset the GPU immediately in the heartbeat code. Signed-off-by: Matthew Brost --- .../gpu/drm/i915/gt/intel_engine_heartbeat.c | 63 +++ .../gpu/drm/i915/gt/intel_engine_heartbeat.h | 4 ++ .../gpu/drm/i915/gt/uc/intel_g

[Intel-gfx] [RFC PATCH 37/97] drm/i915/guc: Add stall timer to non blocking CTB send function

Implement a stall timer which fails H2G CTBs once a period of time with no forward progress is reached to prevent deadlock. Also update to ct_write to return -EDEADLK rather than -EPIPE on a corrupted descriptor. Signed-off-by: John Harrison Signed-off-by: Daniele Ceraolo Spurio Signed-off-by:

[Intel-gfx] [RFC PATCH 22/97] drm/i915/guc: Update CTB response status

From: Michal Wajdeczko Format of the STATUS dword in CTB response message now follows definition of the HXG header. Update our code and remove any obsolete legacy definitions. GuC: 55.0.0 Signed-off-by: Michal Wajdeczko Signed-off-by: Matthew Brost Cc: Piotr Piórkowski --- drivers/gpu/drm/i9

[Intel-gfx] [RFC PATCH 20/97] drm/i915/guc: Introduce unified HXG messages

From: Michal Wajdeczko New GuC firmware will unify format of MMIO and CTB H2G messages. Introduce their definitions now to allow gradual transition of our code to match new changes. Signed-off-by: Michal Wajdeczko Signed-off-by: Matthew Brost Cc: Michał Winiarski --- .../gpu/drm/i915/gt/uc/a

[Intel-gfx] [RFC PATCH 48/97] drm/i915/guc: Defer context unpin until scheduling is disabled

With GuC scheduling, it isn't safe to unpin a context while scheduling is enabled for that context as the GuC may touch some of the pinned state (e.g. LRC). To ensure scheduling isn't enabled when an unpin is done, a call back is added to intel_context_unpin when pin count == 1 to disable schedulin

[Intel-gfx] [RFC PATCH 44/97] drm/i915/guc: Implement GuC submission tasklet

Implement GuC submission tasklet for new interface. The new GuC interface uses H2G to submit contexts to the GuC. Since H2G use a single channel, a single tasklet submits is used for the submission path. As such a global struct intel_engine_cs has been added to leverage the existing scheduling code

[Intel-gfx] [RFC PATCH 60/97] drm/i915: Track 'serial' counts for virtual engines

From: John Harrison The serial number tracking of engines happens at the backend of request submission and was expecting to only be given physical engines. However, in GuC submission mode, the decomposition of virtual to physical engines does not happen in i915. Instead, requests are submitted to

[Intel-gfx] [RFC PATCH 33/97] drm/i915: Engine relative MMIO

From: John Harrison With virtual engines, it is no longer possible to know which specific physical engine a given request will be executed on at the time that request is generated. This means that the request itself must be engine agnostic - any direct register writes must be relative to the engi

[Intel-gfx] [RFC PATCH 45/97] drm/i915/guc: Add bypass tasklet submission path to GuC

Add bypass tasklet submission path to GuC. The tasklet is only used if H2G channel has backpresure. Signed-off-by: Matthew Brost --- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +++ 1 file changed, 29 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/i

[Intel-gfx] [RFC PATCH 82/97] drm/i915/guc: Connect the number of guc_ids to debugfs

For testing purposes it may make sense to reduce the number of guc_ids available to be allocated. Add debugfs support for setting the number of guc_ids. Signed-off-by: Matthew Brost --- .../gpu/drm/i915/gt/uc/intel_guc_debugfs.c| 31 +++ .../gpu/drm/i915/gt/uc/intel_guc_submi

[Intel-gfx] [RFC PATCH 93/97] drm/i915/guc: Take engine PM when a context is pinned with GuC submission

Taking a PM reference to prevent intel_gt_wait_for_idle from short circuiting while a scheduling of user context could be enabled. Signed-off-by: Matthew Brost --- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 36 +-- 1 file changed, 33 insertions(+), 3 deletions(-) diff --git

[Intel-gfx] [RFC PATCH 75/97] drm/i915/guc: Fix for error capture after full GPU reset with GuC

From: John Harrison In the case of a full GPU reset (e.g. because GuC has died or because GuC's hang detection has been disabled), the driver can't rely on GuC reporting the guilty context. Instead, the driver needs to scan all active contexts and find one that is currently executing, as per the

[Intel-gfx] [RFC PATCH 46/97] drm/i915/guc: Implement GuC context operations for new inteface

Implement GuC context operations which includes GuC specific operations pin, unpin, and destroy. Signed-off-by: John Harrison Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/intel_context.c | 5 + drivers/gpu/drm/i915/gt/intel_context_types.h | 22 +- drivers/gpu/drm/i915/gt/i

[Intel-gfx] [RFC PATCH 70/97] drm/i915/guc: Enable the timer expired interrupt for GuC

The GuC can implement execution qunatums, detect hung contexts and other such things but it requires the timer expired interrupt to do so. Signed-off-by: Matthew Brost CC: John Harrison --- drivers/gpu/drm/i915/gt/intel_rps.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/d

[Intel-gfx] [RFC PATCH 74/97] drm/i915/guc: Capture error state on context reset

We receive notification of an engine reset from GuC at its completion. Meaning GuC has potentially cleared any HW state we may have been interested in capturing. GuC resumes scheduling on the engine post-reset, as the resets are meant to be transparent, further muddling our error state. There is o

[Intel-gfx] [RFC PATCH 84/97] drm/i915/guc: Don't allow requests not ready to consume all guc_ids

Add a heuristic which checks if over half of the available guc_ids are currently consumed by requests not ready to be submitted. If this heuristic is true at request creation time (normal guc_id allocation location) force all submissions + guc_ids allocations to tasklet. Signed-off-by: Matthew Bro

[Intel-gfx] [RFC PATCH 80/97] drm/i915/guc: Implement banned contexts for GuC submission

When using GuC submission, if a context gets banned disable scheduling and mark all inflight requests as complete. Cc: John Harrison Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 2 +- drivers/gpu/drm/i915/gt/intel_context.h | 13 ++ drivers/gpu/drm/i

[Intel-gfx] [RFC PATCH 87/97] drm/i915/guc: Implement GuC priority management

Implement a simple static mapping algorithm of the i915 priority levels (int, -1k to 1k exposed to user) to the 4 GuC levels. Mapping is as follows: i915 level < 0 -> GuC low level (3) i915 level == 0 -> GuC normal level (2) i915 level < INT_MAX-> GuC high level(1) i9

[Intel-gfx] [RFC PATCH 77/97] drm/i915/guc: Connect reset modparam updates to GuC policy flags

From: John Harrison Changing the reset module parameter has no effect on a running GuC. The corresponding entry in the ADS must be updated and then the GuC informed via a Host2GuC message. The new debugfs interface to module parameters allows this to happen. However, connecting the parameter dat

[Intel-gfx] [RFC PATCH 90/97] drm/i915/guc: Non-static lrc descriptor registration buffer

Dynamically allocate space for lrc descriptor registration with the GuC rather than using a large static buffer indexed by the guc_id. If no space is available to register a context, fall back to tasklet flow control mechanism. Only allow 1/2 of the space to be allocated outside the tasklet to prev

[Intel-gfx] [RFC PATCH 36/97] drm/i915/guc: Add non blocking CTB send function

Add non blocking CTB send function, intel_guc_send_nb. In order to support a non blocking CTB send function a spin lock is needed to protect the CTB descriptors fields. Also the non blocking call must not update the fence value as this value is owned by the blocking call (intel_guc_send). The bloc

[Intel-gfx] [RFC PATCH 79/97] drm/i915/guc: Don't call ring_is_idle in GuC submission

The engine registers really shouldn't be touched during GuC submission as the GuC owns the registers. Don't call ring_is_idle and tie intel_engine_is_idle strickly the engine pm. Because intel_engine_is_idle tied to the engine pm, retire requests before checking intel_engines_are_idle in gt_drop_c

[Intel-gfx] [RFC PATCH 35/97] drm/i915/guc: Improve error message for unsolicited CT response

Improve the error message when a unsolicited CT response is received by printing fence that couldn't be found, the last fence, and all requests with a response outstanding. Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 10 +++--- 1 file changed, 7 insertions(+)

[Intel-gfx] [RFC PATCH 71/97] drm/i915/guc: Provide mmio list to be saved/restored on engine reset

From: John Harrison The driver must provide GuC with a list of mmio registers that should be saved/restored during a GuC-based engine reset. Unfortunately, the list must be dynamically allocated as its size is variable. That means the driver must generate the list twice - once to work out the siz

[Intel-gfx] [RFC PATCH 89/97] drm/i915/guc: Check return of __xa_store when registering a context

Check return of __xa_store when registering a context as this can fail in a rare case if not memory can not be allocated. If this occurs fall back on the tasklet flow control and try again in the future. Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 14

[Intel-gfx] [RFC PATCH 94/97] drm/i915/guc: Don't call switch_to_kernel_context with GuC submission

Calling switch_to_kernel_context isn't needed if the engine PM reference is taken while all contexts are pinned. By not calling switch_to_kernel_context we save on issuing a request to the engine. Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/intel_engine_pm.c | 4 1 file changed

[Intel-gfx] [RFC PATCH 50/97] drm/i915/guc: Extend deregistration fence to schedule disable

Extend the deregistration context fence to fence whne a GuC context has scheduling disable pending. Cc: John Harrison Signed-off-by: Matthew Brost --- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 37 +++ 1 file changed, 30 insertions(+), 7 deletions(-) diff --git a/drivers/g

[Intel-gfx] [RFC PATCH 81/97] drm/i915/guc: Allow flexible number of context ids

Number of available GuC contexts ids might be limited. Stop refering in code to macro and use variable instead. Signed-off-by: Michal Wajdeczko Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 ++ .../gpu/drm/i915/gt/uc/intel_guc_submission.c| 16 ++

[Intel-gfx] [RFC PATCH 91/97] drm/i915/guc: Take GT PM ref when deregistering context

Taking a PM reference to prevent intel_gt_wait_for_idle from short circuiting while a deregister context H2G is in flight. Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/intel_engine_pm.h | 5 + drivers/gpu/drm/i915/gt/intel_gt_pm.h | 13 +++ drivers/gpu/drm/i915/gt/uc/int

[Intel-gfx] [RFC PATCH 97/97] drm/i915/guc: Unblock GuC submission on Gen11+

From: Daniele Ceraolo Spurio Unblock GuC submission on Gen11+ platforms. Signed-off-by: Michal Wajdeczko Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/intel_guc.h| 1 + drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 8 +++

[Intel-gfx] [RFC PATCH 69/97] drm/i915/guc: Handle engine reset failure notification

GuC will notify the driver, via G2H, if it fails to reset an engine. We recover by resorting to a full GPU reset. Signed-off-by: Matthew Brost Signed-off-by: Fernando Pacheco --- drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 + drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 +++ .../gp

[Intel-gfx] [RFC PATCH 95/97] drm/i915/guc: Selftest for GuC flow control

Add 5 selftests for hard (from user space) to recreate flow conditions. Test listed below: 1. A test to verify that the number of guc_ids can be exhausted and all submissions still complete. 2. A test to verify that the flow control state machine can recover from a full GPU reset. 3. A teset to

[Intel-gfx] [RFC PATCH 76/97] drm/i915/guc: Hook GuC scheduling policies up

From: John Harrison Use the official driver default scheduling policies for configuring the GuC scheduler rather than a bunch of hardcoded values. Signed-off-by: John Harrison Signed-off-by: Matthew Brost Cc: Jose Souza --- drivers/gpu/drm/i915/gt/intel_engine_types.h | 1 + drivers/gpu/dr

[Intel-gfx] [RFC PATCH 83/97] drm/i915/guc: Don't return -EAGAIN to user when guc_ids exhausted

Rather than returning -EAGAIN to the user when no guc_ids are available, implement a fair sharing algorithm in the kernel which blocks submissons until guc_ids become available. Submissions are released one at a time, based on priority, until the guc_id pressure is released to ensure fair sharing o

[Intel-gfx] [RFC PATCH 92/97] drm/i915: Add GT PM delayed worker

Sometimes it is desirable to queue work up for later if the GT PM isn't held and run that work on next GT PM unpark. Implemented with a list in the GT of all pending work, workqueues in the list, a callback to add a workqueue to the list, and finally a wakeref post_get callback that iterates / dra

[Intel-gfx] [RFC PATCH 86/97] drm/i915/guc: Add golden context to GuC ADS

From: John Harrison The media watchdog mechanism involves GuC doing a silent reset and continue of the hung context. This requires the i915 driver provide a golden context to GuC in the ADS. Signed-off-by: John Harrison Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/intel_gt.c

[Intel-gfx] [RFC PATCH 96/97] drm/i915/guc: Update GuC documentation

Signed-off-by: Matthew Brost --- .../gpu/drm/i915/gt/uc/intel_guc_submission.c | 99 ++- 1 file changed, 77 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c index 337ddc0dab6b..594a9

[Intel-gfx] [RFC PATCH 85/97] drm/i915/guc: Introduce guc_submit_engine object

Move fields related to controlling the GuC submission state machine to a unique object (guc_submit_engine) rather than the global GuC state (intel_guc). This encapsulation allows multiple instances of submission objects to operate in parallel and a single instance can block if needed while another

[Intel-gfx] [RFC PATCH 40/97] drm/i915/guc: Module load failure test for CT buffer creation

From: John Harrison Add several module failure load inject points in the CT buffer creation code path. Signed-off-by: John Harrison Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 8 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/uc

[Intel-gfx] [RFC PATCH 30/97] drm/i915/uc: turn on GuC/HuC auto mode by default

From: Daniele Ceraolo Spurio This will enable HuC loading for Gen11+ by default if the binaries are available on the system. GuC submission still requires explicit enabling by the user. Signed-off-by: Daniele Ceraolo Spurio Signed-off-by: Matthew Brost Cc: Michal Wajdeczko Cc: John Harrison

[Intel-gfx] [RFC PATCH 56/97] drm/i915/guc: Update GuC debugfs to support new GuC

Update GuC debugfs to support the new GuC structures. Signed-off-by: John Harrison Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 22 drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h | 3 ++ .../gpu/drm/i915/gt/uc/intel_guc_debugfs.c| 23 +++- ..

[Intel-gfx] [RFC PATCH 78/97] drm/i915/guc: Include scheduling policies in the debugfs state dump

From: John Harrison Added the scheduling policy parameters to the 'guc_info' debugfs state dump. Signed-off-by: John Harrison Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 13 + drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h | 2 ++ drivers/gpu

[Intel-gfx] [RFC PATCH 72/97] drm/i915/guc: Don't complain about reset races

From: John Harrison It is impossible to seal all race conditions of resets occurring concurrent to other operations. At least, not without introducing excesive mutex locking. Instead, don't complain if it occurs. In particular, don't complain if trying to send a H2G during a reset. Whatever the H

[Intel-gfx] [RFC PATCH 88/97] drm/i915/guc: Support request cancellation

This adds GuC backend support for i915_request_cancel(), which in turn makes CONFIG_DRM_I915_REQUEST_TIMEOUT work. Signed-off-by: Matthew Brost Cc: Tvrtko Ursulin --- drivers/gpu/drm/i915/gt/intel_context.c | 9 + drivers/gpu/drm/i915/gt/intel_context.h | 7 + drivers/gpu/drm/i9

Re: [Intel-gfx] [PATCH v2 01/10] drm/i915/xelpd: add XE_LPD display characteristics

On Thu, 2021-05-06 at 19:19 +0300, Imre Deak wrote: > From: Matt Roper > > Let's start preparing for upcoming platforms that will use an XE_LPD > design. > > v2: > - Use the now-preferred "XE_LPD" term to refer to this design > - Utilize DISPLAY_VER() rather than a feature flag > - Drop unuse

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Basic GuC submission support in the i915

== Series Details == Series: Basic GuC submission support in the i915 URL : https://patchwork.freedesktop.org/series/89844/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h LD [M]

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/adl_p: Add support for Display Page Tables (rev2)

Re-reported. -Original Message- From: Deak, Imre Sent: Thursday, May 6, 2021 10:58 AM To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana Subject: Re: ✗ Fi.CI.BAT: failure for drm/i915/adl_p: Add support for Display Page Tables (rev2) On Thu, May 06, 2021 at 05:03:29PM +,

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Try YCbCr420 color when RGB fails

== Series Details == Series: drm/i915/display: Try YCbCr420 color when RGB fails URL : https://patchwork.freedesktop.org/series/89842/ State : success == Summary == CI Bug Log - changes from CI_DRM_10053_full -> Patchwork_20079_full Summary

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/adl_p: Add support for Display Page Tables (rev2)

== Series Details == Series: drm/i915/adl_p: Add support for Display Page Tables (rev2) URL : https://patchwork.freedesktop.org/series/89078/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10053_full -> Patchwork_20077_full

Re: [Intel-gfx] [PATCH v2 07/10] drm/i915/adl_p: Add stride restriction when using DPT

On 5/6/21 9:19 AM, Imre Deak wrote: From: José Roberto de Souza Alderlake-P have a new stride restriction when using DPT and it is used by non linear framebuffers. Stride needs to be a power of two to take full DPT rows, but stride is a parameter set by userspace. What we could do is use a fa

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Use correct downstream caps for check Src-Ctl mode for PCON (rev2)

Hi Lakshmi, The following failure is due to existing issue : https://gitlab.freedesktop.org/drm/intel/-/issues/541 Possible regressions * igt@i915_selftest@live@gt_heartbeat: * fi-tgl-y: PASS

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Use correct downstream caps for check Src-Ctl mode for PCON (rev2)

== Series Details == Series: drm/i915: Use correct downstream caps for check Src-Ctl mode for PCON (rev2) URL : https://patchwork.freedesktop.org/series/89639/ State : success == Summary == CI Bug Log - changes from CI_DRM_10047 -> Patchwork_20065 =

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Use correct downstream caps for check Src-Ctl mode for PCON (rev2)

Re-reported. From: Nautiyal, Ankit K Sent: Thursday, May 6, 2021 9:28 PM To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana Subject: RE: ✗ Fi.CI.BAT: failure for drm/i915: Use correct downstream caps for check Src-Ctl mode for PCON (rev2) Hi Lakshmi, The following failure is due to

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Use correct downstream caps for check Src-Ctl mode for PCON (rev2)

== Series Details == Series: drm/i915: Use correct downstream caps for check Src-Ctl mode for PCON (rev2) URL : https://patchwork.freedesktop.org/series/89639/ State : success == Summary == CI Bug Log - changes from CI_DRM_10047_full -> Patchwork_20065_full ===

Re: [Intel-gfx] [RFC 0/1] drm/i915/display: Expose HDMI properties to userspace

On Thu, May 06, 2021 at 06:17:18AM +0530, Nischal Varide wrote: > Right now the HDMI properties like vendor and product ids are hardcoded > in the function "intel_hdmi_compute_spd_infoframe()". > > ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"). > > This patch enables the possibi

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