[Intel-gfx] [PATCH] drm/i915: Reorder skl+ scaler vs. plane updates

From: Ville Syrjälä When scanning out NV12 if we at any time have the plane enabled while the scaler is disabled we get a pretty catastrophics underrun. Let's reorder the operations so that we try to avoid that happening even if our vblank evade fails and the scaler enable/disable and the plane

[Intel-gfx] [RFC 0/1] drm/i915/display: Expose HDMI properties to userspace

Right now the HDMI properties like vendor and product ids are hardcoded in the function "intel_hdmi_compute_spd_infoframe()". ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"). This patch enables the possibility of setting vendor and product fields of the Infoframe structure in the

[Intel-gfx] [RFC 1/1] drm/i915/display: Expose HDMI properties to userspace

Right now the HDMI properties like vendor and product ids are hardcoded in the function "intel_hdmi_compute_spd_infoframe()". ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"). This patch enables the possibility of setting vendor and product fields of the Infoframe structure in the

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Reorder skl+ scaler vs. plane updates

== Series Details == Series: drm/i915: Reorder skl+ scaler vs. plane updates URL : https://patchwork.freedesktop.org/series/89832/ State : success == Summary == CI Bug Log - changes from CI_DRM_10050 -> Patchwork_20075 Summary --- **

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Expose HDMI properties to userspace

== Series Details == Series: drm/i915/display: Expose HDMI properties to userspace URL : https://patchwork.freedesktop.org/series/89833/ State : warning == Summary == $ dim checkpatch origin/drm-tip fed7f9fc21db drm/i915/display: Expose HDMI properties to userspace -:48: CHECK:COMPARISON_TO_NU

Re: [Intel-gfx] [PATCH] drm/i915: Reorder skl+ scaler vs. plane updates

On Thu, May 06, 2021 at 10:38:36AM +0300, Ville Syrjala wrote: > From: Ville Syrjälä > > When scanning out NV12 if we at any time have the plane enabled > while the scaler is disabled we get a pretty catastrophics > underrun. > > Let's reorder the operations so that we try to avoid that happenin

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm + usb-type-c: Add support for out-of-band hotplug notification (rev3)

Hi, On 5/5/21 9:14 PM, Patchwork wrote: > *Patch Details* > *Series:* drm + usb-type-c: Add support for out-of-band hotplug > notification (rev3) > *URL:*https://patchwork.freedesktop.org/series/89604/ > > *State:* failure > *Det

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Expose HDMI properties to userspace

== Series Details == Series: drm/i915/display: Expose HDMI properties to userspace URL : https://patchwork.freedesktop.org/series/89833/ State : success == Summary == CI Bug Log - changes from CI_DRM_10050 -> Patchwork_20076 Summary ---

Re: [Intel-gfx] Enabling sample_c optimization for Broadwell GPUs

Hi Rodrigo, Thank you very much for providing that information in a precise manner. Às 07:16 de 05/05/21, Rodrigo Vivi escreveu: Hi Andre, I'm not familiar with the sample c message optimization. Probably Ken can comment. However I could check the internal spec here and I saw this bit only ex

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Reorder skl+ scaler vs. plane updates

== Series Details == Series: drm/i915: Reorder skl+ scaler vs. plane updates URL : https://patchwork.freedesktop.org/series/89832/ State : success == Summary == CI Bug Log - changes from CI_DRM_10050_full -> Patchwork_20075_full Summary ---

Re: [Intel-gfx] [PATCH 8/8] drm/modifiers: Enforce consistency between the cap an IN_FORMATS

On Tue, Apr 27, 2021 at 11:20:18AM +0200, Daniel Vetter wrote: > It's very confusing for userspace to have to deal with inconsistencies > here, and some drivers screwed this up a bit. Most just ommitted the > format list when they meant to say that only linear modifier is > allowed, but some also m

Re: [Intel-gfx] [PATCH] drm/i915/display: Disable PSR2 sel fetch in TGL pre-production

Reviewed-by: Gwan-gyeong Mun On Wed, 2021-05-05 at 14:38 -0700, José Roberto de Souza wrote: > The implementation of two workarounds are missing causing failures > in CI with pre-production HW. > > Cc: Gwan-gyeong Mun > Signed-off-by: José Roberto de Souza > --- >  drivers/gpu/drm/i915/display/

Re: [Intel-gfx] [RFC 1/1] drm/i915/display: Expose HDMI properties to userspace

On Thu, 06 May 2021, Nischal Varide wrote: > Right now the HDMI properties like vendor and product ids are hardcoded > in the function "intel_hdmi_compute_spd_infoframe()". > > ret = hdmi_spd_infoframe_init(frame, "Intel", "Integrated gfx"). > > This patch enables the possibility of setting vendor

Re: [Intel-gfx] [PATCH] drm/i915: Nuke display error state

On Wed, 05 May 2021, Ville Syrjala wrote: > From: Ville Syrjälä > > I doubt anyone has used the display error state since CS flips > went the way of the dodo. Just nuke it. FWIW, I've never used it. Acked-by: Jani Nikula > > It might be semi interesting to have something like this for > FIFO

Re: [Intel-gfx] [PATCH 1/3] New function to avoid duplicate code in upcomming commits

On Wed, 05 May 2021, Werner Sembach wrote: > Moves some checks that later will be performed 2 times to an own fuction. This > avoids duplicate code later on. > > Signed-off-by: Werner Sembach > --- > > From 42a4a3a7d9ea9948b4071f406e7fcae23bfa0bdf Mon Sep 17 00:00:00 2001 > From: Werner Sembach

Re: [Intel-gfx] [PATCH 1/3] New function to avoid duplicate code in upcomming commits

On Wed, 05 May 2021, Werner Sembach wrote: > Subject: [PATCH 1/3] New function to avoid duplicate code in upcomming commits Also, the subject should have a prefix, such as "drm/i915/hdmi: " etc. depending on what you're changing. See git log on the files for examples. BR, Jani. -- Jani Nikula

Re: [Intel-gfx] [PATCH] i915: Increase *_latency array size

On Wed, 05 May 2021, Ville Syrjälä wrote: > On Wed, May 05, 2021 at 07:18:30AM -0700, Andi Kleen wrote: >> What do I miss when you say there is no bug? > > We always use dev_priv->wm.skl_latency[] for gen9+. See > {pri,spr,cur}_wm_latency_show(), skl_setup_wm_latency(), etc. Granted, we should pr

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/display: Expose HDMI properties to userspace

== Series Details == Series: drm/i915/display: Expose HDMI properties to userspace URL : https://patchwork.freedesktop.org/series/89833/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10050_full -> Patchwork_20076_full Summa

Re: [Intel-gfx] [PATCH] drm/i915: Reorder skl+ scaler vs. plane updates

On Thu, May 06, 2021 at 11:47:08AM +0300, Lisovskiy, Stanislav wrote: > On Thu, May 06, 2021 at 10:38:36AM +0300, Ville Syrjala wrote: > > From: Ville Syrjälä > > > > When scanning out NV12 if we at any time have the plane enabled > > while the scaler is disabled we get a pretty catastrophics > >

Re: [Intel-gfx] [PATCH 10/11] drm/i915/adl_p: Require a minimum of 8 tiles stride for DPT FBs

> -Original Message- > From: Intel-gfx On Behalf Of Imre > Deak > Sent: Friday, April 16, 2021 1:13 AM > To: intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH 10/11] drm/i915/adl_p: Require a minimum of > 8 tiles stride for DPT FBs > > On Wed, Apr 14, 2021 at 06:52:07PM +0

[Intel-gfx] [PULL] drm-misc-next-fixes

Hi Dave, Daniel, Here's the drm-misc-next-fixes PR for this week Thanks! Maxime drm-misc-next-fixes-2021-05-06: Two patches, one to fix a null pointer dereference in msm, and one to fix an unused warning for in fbdev when PROCFS is disabled. The following changes since commit 74deef03a44ae77db85

Re: [Intel-gfx] i915 flickering with 5.12.X kernels

See: https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs From: Intel-gfx On Behalf Of Risto Paavola Sent: torstai 6. toukokuuta 2021 8.20 To: jani.nik...@linux.intel.com; joonas.lahti...@linux.intel.com; Vivi, Rodrigo ; airl...@linux.ie; dan...@ffwll.ch; intel-gfx@lists.free

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm + usb-type-c: Add support for out-of-band hotplug notification (rev3)

== Series Details == Series: drm + usb-type-c: Add support for out-of-band hotplug notification (rev3) URL : https://patchwork.freedesktop.org/series/89604/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10049_full -> Patchwork_20068_full ==

[Intel-gfx] [PATCH v2 00/10] drm/i915/adl_p: Add support for Display Page Tables

This is v2 of [1], rebasing the patchset on the latest drm-tip tree and adding Reviewed-by tags. [1] https://patchwork.freedesktop.org/series/89078/ Clinton Taylor (2): drm/i915/adl_p: Add PCI Devices IDs drm/i915/adl_p: ADL_P device info enabling Imre Deak (3): drm/i915/adl_p: Disable sup

[Intel-gfx] [PATCH v2 01/10] drm/i915/xelpd: add XE_LPD display characteristics

From: Matt Roper Let's start preparing for upcoming platforms that will use an XE_LPD design. v2: - Use the now-preferred "XE_LPD" term to refer to this design - Utilize DISPLAY_VER() rather than a feature flag - Drop unused mbus_size field (Lucas) v3: - Adjust for dbuf.{size,slice_mask} (Vi

[Intel-gfx] [PATCH v2 03/10] drm/i915/adl_p: ADL_P device info enabling

From: Clinton Taylor Add ADL-P to the device_info table and support MACROS. Bspec: 49185, 55372, 55373 Cc: Matt Atwood Cc: Matt Roper Signed-off-by: Clinton Taylor Signed-off-by: Matt Roper Reviewed-by: José Roberto de Souza Signed-off-by: Imre Deak --- arch/x86/kernel/early-quirks.c

[Intel-gfx] [PATCH v2 02/10] drm/i915/adl_p: Add PCI Devices IDs

From: Clinton Taylor Add 18 known PCI device IDs Bspec: 55376 Cc: Caz Yokoyama Cc: Matt Atwood Cc: Matt Roper Signed-off-by: Clinton Taylor Signed-off-by: Matt Roper Reviewed-by: Anusha Srivatsa Signed-off-by: Imre Deak --- include/drm/i915_pciids.h | 21 + 1 file cha

[Intel-gfx] [PATCH v2 04/10] drm/i915/xelpd: First stab at DPT support

From: Ville Syrjälä Add support for DPT (display page table). DPT is a slightly peculiar two level page table scheme used for tiled scanout buffers (linear uses direct ggtt mapping still). The plane surface address will point at a page in the DPT which holds the PTEs for 512 actual pages. Thus we

[Intel-gfx] [PATCH v2 05/10] drm/i915/xelpd: Fallback to plane stride limitations when using DPT

From: José Roberto de Souza GTT remapping allow us to have planes with strides larger than HW supports but DPT + GTT remapping is still not properly handled so falling back to plane HW limitations for now. This patch can be dropped when DPT + GTT remapping is correctly handled but until then we

[Intel-gfx] [PATCH v2 06/10] drm/i915/xelpd: Support 128k plane stride

From: Juha-Pekka Heikkilä XE_LPD supports plane strides up to 128KB. Cc: Vandita Kulkarni Signed-off-by: Juha-Pekka Heikkilä Signed-off-by: Matt Roper Reviewed-by: Lucas De Marchi Signed-off-by: Imre Deak --- .../drm/i915/display/skl_universal_plane.c| 46 +++ drivers/g

[Intel-gfx] [PATCH v2 07/10] drm/i915/adl_p: Add stride restriction when using DPT

From: José Roberto de Souza Alderlake-P have a new stride restriction when using DPT and it is used by non linear framebuffers. Stride needs to be a power of two to take full DPT rows, but stride is a parameter set by userspace. What we could do is use a fake stride when doing DPT allocation so

[Intel-gfx] [PATCH v2 08/10] drm/i915/adl_p: Disable support for 90/270 FB rotation

The latest specification removed the support for 90/270 FB rotation on ADL_P, even though legacy Y-tiled surfaces are supported. Align the code accordingly. Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä --- .../drm/i915/display/intel_display_types.h| 6 +++-- drivers/gpu/drm/i915/dis

[Intel-gfx] [PATCH v2 09/10] drm/i915/adl_p: Require a minimum of 8 tiles stride for DPT FBs

The specification only requires DPT FB strides to be POT aligned, but there seems to be also a minimum of 8 stride tile requirement. Scanning out FBs with < 8 stride tiles will result in pipe faults (even though the stride is POT aligned). Signed-off-by: Imre Deak Acked-by: Ville Syrjälä Reviewe

[Intel-gfx] [PATCH v2 10/10] drm/i915/adl_p: Enable remapping to pad DPT FB strides to POT

Enable padding of DPT FB strides to POT, using the FB remapping logic. Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 16 drivers/gpu/drm/i915/display/intel_fb.c | 7 +-- drivers/gpu/drm/i915/display/intel_fb.h

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/adl_p: Add support for Display Page Tables (rev2)

== Series Details == Series: drm/i915/adl_p: Add support for Display Page Tables (rev2) URL : https://patchwork.freedesktop.org/series/89078/ State : warning == Summary == $ dim checkpatch origin/drm-tip ff3b7dc8f685 drm/i915/xelpd: add XE_LPD display characteristics a319d966c549 drm/i915/adl_

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/adl_p: Add support for Display Page Tables (rev2)

== Series Details == Series: drm/i915/adl_p: Add support for Display Page Tables (rev2) URL : https://patchwork.freedesktop.org/series/89078/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +driv

Re: [Intel-gfx] [PATCH 1/3] New function to avoid duplicate code in upcomming commits

Am 06.05.21 um 12:19 schrieb Jani Nikula: > On Wed, 05 May 2021, Werner Sembach wrote: >> Moves some checks that later will be performed 2 times to an own fuction. >> This >> avoids duplicate code later on. >> >> Signed-off-by: Werner Sembach >> --- >> >> From 42a4a3a7d9ea9948b4071f406e7fcae23

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/adl_p: Add support for Display Page Tables (rev2)

== Series Details == Series: drm/i915/adl_p: Add support for Display Page Tables (rev2) URL : https://patchwork.freedesktop.org/series/89078/ State : failure == Summary == CI Bug Log - changes from CI_DRM_10053 -> Patchwork_20077 Summary --

[Intel-gfx] [RFC PATCH 1/5] drm/doc/rfc: i915 GuC submission / DRM scheduler integration plan

Add entry for i915 GuC submission / DRM scheduler integration plan. Follow up patch with details of new parallel submission uAPI to come. Cc: Jon Bloomfield Cc: Jason Ekstrand Cc: Dave Airlie Cc: Daniel Vetter Cc: Jason Ekstrand Cc: dri-de...@lists.freedesktop.org Signed-off-by: Matthew Brost

[Intel-gfx] [RFC PATCH 2/5] drm/doc/rfc: i915 new parallel submission uAPI plan

Add entry fpr i915 new parallel submission uAPI plan. Cc: Tvrtko Ursulin Cc: Tony Ye CC: Carl Zhang Cc: Daniel Vetter Cc: Jason Ekstrand Signed-off-by: Matthew Brost --- Documentation/gpu/rfc/i915_scheduler.rst | 56 +++- 1 file changed, 54 insertions(+), 2 deletions(-)

[Intel-gfx] [RFC PATCH 3/5] drm/i915: Expose logical engine instance to user

Expose logical engine instance to user via query engine info IOCTL. This is required for split-frame workloads as these need to be placed on engines in a logically contiguous order. The logical mapping can change based on fusing. Rather than having user have knowledge of the fusing we simply just e

[Intel-gfx] [RFC PATCH 0/5] GuC submission / DRM scheduler integration plan + new uAPI

Subject and patches say it all. Initial post of GuC submission patches, detailed in patch 1, coming shortly. Signed-off-by: Matthew Brost Matthew Brost (5): drm/doc/rfc: i915 GuC submission / DRM scheduler integration plan drm/doc/rfc: i915 new parallel submission uAPI plan drm/i915: Expo

[Intel-gfx] [RFC PATCH 4/5] drm/i915: Introduce 'set parallel submit' extension

i915_drm.h updates for 'set parallel submit' extension. Cc: Tvrtko Ursulin Cc: Tony Ye CC: Carl Zhang Cc: Daniel Vetter Cc: Jason Ekstrand Signed-off-by: Matthew Brost --- include/uapi/drm/i915_drm.h | 126 1 file changed, 126 insertions(+) diff --git a

[Intel-gfx] [RFC PATCH 5/5] drm/i915: Update execbuf IOCTL to accept N BBs

Add I915_EXEC_NUMBER_BB_* to drm_i915_gem_execbuffer2.flags which allows submitting N BBs per IOCTL. Cc: Tvrtko Ursulin Cc: Tony Ye CC: Carl Zhang Cc: Daniel Vetter Cc: Jason Ekstrand Signed-off-by: Matthew Brost --- include/uapi/drm/i915_drm.h | 21 - 1 file changed, 20

[Intel-gfx] [PATCH 0/3] drm/i915/display: Try YCbCr420 color when RGB fails

When encoder validation of a display mode fails, retry with less bandwidth heavy YCbCr420 color mode, if available. This enables some HDMI 1.4 setups to support 4k60Hz output, which previously failed silently. AMDGPU had nearly the exact same issue. This problem description is therefore copied fro

[Intel-gfx] [PATCH 1/3] drm/i915/display: New function to avoid duplicate code in upcomming commits

Moves some checks that later will be performed 2 times to an own fuction. This avoids duplicate code later on. Signed-off-by: Werner Sembach --- drivers/gpu/drm/i915/display/intel_hdmi.c | 41 ++- 1 file changed, 26 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm

[Intel-gfx] [PATCH 2/3] drm/i915/display: Restructure output format computation for better expandability

Couples the decission between RGB and YCbCr420 mode and the check if the port clock can archive the required frequency. Other checks and configuration steps that where previously done in between can also be done before or after. This allows for are cleaner implementation of retrying different colo

[Intel-gfx] [PATCH 3/3] drm/i915/display: Use YCbCr420 as fallback when RGB fails

When encoder validation of a display mode fails, retry with less bandwidth heavy YCbCr420 color mode, if available. This enables some HDMI 1.4 setups to support 4k60Hz output, which previously failed silently. AMDGPU had nearly the exact same issue. This problem description is therefore copied fro

[Intel-gfx] ✗ Fi.CI.BUILD: failure for GuC submission / DRM scheduler integration plan + new uAPI

== Series Details == Series: GuC submission / DRM scheduler integration plan + new uAPI URL : https://patchwork.freedesktop.org/series/89840/ State : failure == Summary == Applying: drm/doc/rfc: i915 GuC submission / DRM scheduler integration plan Using index info to reconstruct a base tree...

Re: [Intel-gfx] [PATCH 1/3] New function to avoid duplicate code in upcomming commits

On Thu, 06 May 2021, Werner Sembach wrote: > Am 06.05.21 um 12:19 schrieb Jani Nikula: >> On Wed, 05 May 2021, Werner Sembach wrote: >>> Moves some checks that later will be performed 2 times to an own fuction. >>> This >>> avoids duplicate code later on. >>> >>> Signed-off-by: Werner Sembach >

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Try YCbCr420 color when RGB fails

== Series Details == Series: drm/i915/display: Try YCbCr420 color when RGB fails URL : https://patchwork.freedesktop.org/series/89842/ State : warning == Summary == $ dim checkpatch origin/drm-tip 00bf5b4bbe7e drm/i915/display: New function to avoid duplicate code in upcomming commits -:7: WA

Re: [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display: Disable PSR2 sel fetch in TGL pre-production

On Thu, 2021-05-06 at 01:02 +, Patchwork wrote: Patch Details Series: drm/i915/display: Disable PSR2 sel fetch in TGL pre-production URL:https://patchwork.freedesktop.org/series/89825/ State: success Details: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20074/index.html CI Bu

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/adl_p: Add support for Display Page Tables (rev2)

On Thu, May 06, 2021 at 05:03:29PM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/adl_p: Add support for Display Page Tables (rev2) > URL : https://patchwork.freedesktop.org/series/89078/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_10053 -> Pat

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display: Try YCbCr420 color when RGB fails

== Series Details == Series: drm/i915/display: Try YCbCr420 color when RGB fails URL : https://patchwork.freedesktop.org/series/89842/ State : success == Summary == CI Bug Log - changes from CI_DRM_10053 -> Patchwork_20079 Summary ---

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/adl_p: Add support for Display Page Tables (rev2)

== Series Details == Series: drm/i915/adl_p: Add support for Display Page Tables (rev2) URL : https://patchwork.freedesktop.org/series/89078/ State : success == Summary == CI Bug Log - changes from CI_DRM_10053 -> Patchwork_20077 Summary --

[Intel-gfx] [RFC PATCH 00/97] Basic GuC submission support in the i915

Basic GuC submission support. This is the first bullet point in the upstreaming plan covered in the following RFC [1]. At a very high level the GuC is a piece of firmware which sits between the i915 and the GPU. It offloads some of the scheduling of contexts from the i915 and programs the GPU to s

[Intel-gfx] [RFC PATCH 04/97] drm/i915/guc: skip disabling CTBs before sanitizing the GuC

From: Daniele Ceraolo Spurio If we're about to sanitize the GuC, something might have going wrong beforehand, so we should avoid trying to talk to it. Even if GuC is still running fine, the sanitize will reset its internal state and clear the CTB registration, so there is still no need to explici

[Intel-gfx] [RFC PATCH 03/97] drm/i915/gt: Move CS interrupt handler to the backend

From: Chris Wilson The different submission backends each have their own preferred behaviour and interrupt setup. Let each handle their own interrupts. This becomes more useful later as we to extract the use of auxiliary state in the interrupt handler that is backend specific. Signed-off-by: Ma

[Intel-gfx] [RFC PATCH 01/97] drm/i915/gt: Move engine setup out of set_default_submission

From: Chris Wilson Now that we no longer switch back and forth between guc and execlists, we no longer need to restore the backend's vfunc and can leave them set after initialisation. The only catch is that we lose the submission on wedging and still need to reset the submit_request vfunc on unwe

[Intel-gfx] [RFC PATCH 02/97] drm/i915/gt: Move submission_method into intel_gt

From: Chris Wilson Since we setup the submission method for the engines once, it is easy to assign an enum and use that instead of probing into the backends. Signed-off-by: Matthew Brost Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin --- drivers/gpu/drm/i915/gt/intel_engine.h |

[Intel-gfx] [RFC PATCH 16/97] drm/i915/guc: Start protecting access to CTB descriptors

From: Michal Wajdeczko We want to stop using guc.send_mutex while sending CTB messages so we have to start protecting access to CTB send descriptor. For completeness protect also CTB send descriptor. Add spinlock to struct intel_guc_ct_buffer and start using it. Signed-off-by: Michal Wajdeczko

[Intel-gfx] [RFC PATCH 09/97] drm/i915/guc: Stop using fence/status from CTB descriptor

From: Michal Wajdeczko Stop using fence/status from CTB descriptor as future GuC ABI will no longer support replies over CTB descriptor. Signed-off-by: Michal Wajdeczko Signed-off-by: Matthew Brost --- .../gt/uc/abi/guc_communication_ctb_abi.h | 4 +- drivers/gpu/drm/i915/gt/uc/intel_guc

[Intel-gfx] [RFC PATCH 06/97] drm/i915/guc: enable only the user interrupt when using GuC submission

From: Daniele Ceraolo Spurio In GuC submission mode the CS is owned by the GuC FW, so all CS status interrupts are handled by it. We only need the user interrupt as that signals request completion. Since we're now starting the engines directly in GuC submission mode when selected, we can stop sw

[Intel-gfx] [RFC PATCH 11/97] drm/i915/guc: Only rely on own CTB size

From: Michal Wajdeczko In upcoming GuC firmware, CTB size will be removed from the CTB descriptor so we must keep it locally for any calculations. While around, improve some debug messages and helpers. Signed-off-by: Michal Wajdeczko Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/u

[Intel-gfx] [RFC PATCH 17/97] drm/i915/guc: Stop using mutex while sending CTB messages

From: Michal Wajdeczko We are no longer using descriptor to hold G2H replies and we are protecting access to the descriptor and command buffer by the separate spinlock, so we can stop using mutex. Signed-off-by: Michal Wajdeczko Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/inte

[Intel-gfx] [RFC PATCH 19/97] drm/i915/guc: Always copy CT message to new allocation

From: Michal Wajdeczko Since most of future CT traffic will be based on G2H requests, instead of copying incoming CT message to static buffer and then create new allocation for such request, always copy incoming CT message to new allocation. Also by doing it while reading CT header, we can safely

[Intel-gfx] [RFC PATCH 05/97] drm/i915/guc: use probe_error log for CT enablement failure

From: Daniele Ceraolo Spurio We have a couple of failure injection points in the CT enablement path, so we need to use i915_probe_error() to select the appropriate log level. A new macro (CT_PROBE_ERROR) has been added to the set of CT logging macros to be used in this scenario and upcoming ones.

[Intel-gfx] [RFC PATCH 21/97] drm/i915/guc: Update MMIO based communication

From: Michal Wajdeczko The MMIO based Host-to-GuC communication protocol has been updated to use unified HXG messages. Update our intel_guc_send_mmio() function by correctly handle BUSY, RETRY and FAILURE replies. Also update our documentation. GuC: 55.0.0 Signed-off-by: Michal Wajdeczko Signe

[Intel-gfx] [RFC PATCH 12/97] drm/i915/guc: Don't repeat CTB layout calculations

From: Michal Wajdeczko We can retrieve offsets to cmds buffers and descriptor from actual pointers that we already keep locally. Signed-off-by: Michal Wajdeczko Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 16 ++-- 1 file changed, 10 insertions(+),

[Intel-gfx] [RFC PATCH 10/97] drm/i915: Promote ptrdiff() to i915_utils.h

From: Michal Wajdeczko Generic helpers should be placed in i915_utils.h. Signed-off-by: Michal Wajdeczko Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/i915_utils.h | 5 + drivers/gpu/drm/i915/i915_vma.h | 5 - 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/dr

[Intel-gfx] [RFC PATCH 13/97] drm/i915/guc: Replace CTB array with explicit members

From: Michal Wajdeczko Upcoming GuC firmware will always require just two CTBs and we also plan to configure them with different sizes, so definining them as array is no longer suitable. Signed-off-by: Michal Wajdeczko Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c

[Intel-gfx] [RFC PATCH 26/97] drm/i915/guc: New definition of the CTB registration action

From: Michal Wajdeczko Definition of the CTB registration action has changed. Add some ABI documentation and implement required changes. GuC: 57.0.0 Signed-off-by: Michal Wajdeczko Signed-off-by: Matthew Brost --- .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 107 ++ .../gt/

[Intel-gfx] [RFC PATCH 07/97] drm/i915/guc: Remove sample_forcewake h2g action

From: Rodrigo Vivi This action is no-op in the GuC side for a few versions already and it is getting entirely removed soon, in an upcoming version. Time to remove before we face communication issues. Cc: Vinay Belgaumkar Signed-off-by: Rodrigo Vivi Signed-off-by: Matthew Brost --- drivers/

[Intel-gfx] [RFC PATCH 14/97] drm/i915/guc: Update sizes of CTB buffers

From: Michal Wajdeczko Future GuC will require CTB buffers sizes to be multiple of 4K. Make these changes now as this shouldn't impact us too much. Signed-off-by: Michal Wajdeczko Signed-off-by: Matthew Brost Cc: John Harrison --- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 60 --

[Intel-gfx] [RFC PATCH 08/97] drm/i915/guc: Keep strict GuC ABI definitions

From: Michal Wajdeczko Our fwif.h file is now mix of strict firmware ABI definitions and set of our helpers. In anticipation of upcoming changes to the GuC interface try to keep them separate in smaller maintainable files. Signed-off-by: Michal Wajdeczko Signed-off-by: Matthew Brost Cc: Michał

[Intel-gfx] [RFC PATCH 52/97] drm/i915/guc: Ensure request ordering via completion fences

If two requests are on the same ring, they are explicitly ordered by the HW. So, a submission fence is sufficient to ensure ordering when using the new GuC submission interface. Conversely, if two requests share a timeline and are on the same physical engine but different context this doesn't ensur

[Intel-gfx] [RFC PATCH 47/97] drm/i915/guc: Insert fence on context when deregistering

Sometime during context pinning a context with the same guc_id is registered with the GuC. In this a case deregister must be before before the context can be registered. A fence is inserted on all requests while the deregister is in flight. Once the G2H is received indicating the deregistration is

[Intel-gfx] [RFC PATCH 24/97] drm/i915/guc: Add flag for mark broken CTB

From: Michal Wajdeczko Once CTB descriptor is found in error state, either set by GuC or us, there is no need continue checking descriptor any more, we can rely on our internal flag. Signed-off-by: Michal Wajdeczko Signed-off-by: Matthew Brost Cc: Piotr Piórkowski --- drivers/gpu/drm/i915/gt

[Intel-gfx] [RFC PATCH 64/97] drm/i915/guc: Reset implementation for new GuC interface

Reset implementation for new GuC interface. This is the legacy reset implementation which is called when the i915 owns the engine hang check. Future patches will offload the engine hang check to GuC but we will continue to maintain this legacy path as a fallback and this code path is also required

[Intel-gfx] [RFC PATCH 27/97] drm/i915/guc: New CTB based communication

From: Michal Wajdeczko Format of the CTB messages has changed: - support for multiple formats - message fence is now part of the header - reuse of unified HXG message formats Signed-off-by: Michal Wajdeczko Signed-off-by: Matthew Brost Cc: Piotr Piórkowski --- .../gt/uc/abi/guc_communicat

[Intel-gfx] [RFC PATCH 15/97] drm/i915/guc: Relax CTB response timeout

From: Michal Wajdeczko In upcoming patch we will allow more CTB requests to be sent in parallel to the GuC for procesing, so we shouldn't assume any more that GuC will always reply without 10ms. Use bigger value from CONFIG_DRM_I915_HEARTBEAT_INTERVAL instead. Signed-off-by: Michal Wajdeczko S

[Intel-gfx] [RFC PATCH 34/97] drm/i915/guc: Use guc_class instead of engine_class in fw interface

From: Daniele Ceraolo Spurio GuC has its own defines for the engine classes. They're currently mapping 1:1 to the defines used by the driver, but there is no guarantee this will continue in the future. Given that we've been caught off-guard in the past by similar divergences, we can prepare for t

[Intel-gfx] [RFC PATCH 25/97] drm/i915/guc: New definition of the CTB descriptor

From: Michal Wajdeczko Definition of the CTB descriptor has changed, leaving only minimal shared fields like HEAD/TAIL/STATUS. Both HEAD and TAIL are now in dwords. Add some ABI documentation and implement required changes. GuC: 57.0.0 GuC: 60.0.0 Signed-off-by: Michal Wajdeczko Signed-off-by

[Intel-gfx] [RFC PATCH 39/97] drm/i915/guc: Increase size of CTB buffers

With the introduction of non-blocking CTBs more than one CTB can be in flight at a time. Increasing the size of the CTBs should reduce how often software hits the case where no space is available in the CTB buffer. Cc: John Harrison Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/in

[Intel-gfx] [RFC PATCH 63/97] drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbs

With GuC virtual engines the physical engine which a request executes and completes on isn't known to the i915. Therefore we can't attach a request to a physical engines breadcrumbs. To work around this we create a single breadcrumbs per engine class when using GuC submission and direct all physica

[Intel-gfx] [RFC PATCH 28/97] drm/i915/guc: Kill guc_clients.ct_pool

From: Michal Wajdeczko CTB pool is now maintained internally by the GuC as part of its "private data". No need to allocate separate buffer and pass it to GuC as yet another ADS. GuC: 57.0.0 Signed-off-by: Michal Wajdeczko Signed-off-by: Matthew Brost Cc: Janusz Krzysztofik Cc: Matthew Brost

[Intel-gfx] [RFC PATCH 43/97] drm/i915/guc: Add lrc descriptor context lookup array

Add lrc descriptor context lookup array which can resolve the intel_context from the lrc descriptor index. In addition to lookup, it can determine in the lrc descriptor context is currently registered with the GuC by checking if an entry for a descriptor index is present. Future patches in the seri

[Intel-gfx] [RFC PATCH 59/97] drm/i915/guc: GuC virtual engines

Implement GuC virtual engines. Rather simple implementation, basically just allocate an engine, setup context enter / exit function to virtual engine specific functions, set all other variables / functions to guc versions, and set the engine mask to that of all the siblings. Cc: Daniele Ceraolo Sp

[Intel-gfx] [RFC PATCH 51/97] drm/i915: Disable preempt busywait when using GuC scheduling

Disable preempt busywait when using GuC scheduling. This isn't need as the GuC control preemption when scheduling. Cc: John Harrison Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/dr

[Intel-gfx] [RFC PATCH 31/97] drm/i915/guc: Early initialization of GuC send registers

From: Michal Wajdeczko Base offset and count of the GuC scratch registers, used for sending MMIO messages to GuC, can be initialized earlier with other GuC members that also depends on platform. Signed-off-by: Michal Wajdeczko Signed-off-by: Matthew Brost Cc: Daniele Ceraolo Spurio --- drive

[Intel-gfx] [RFC PATCH 41/97] drm/i915/guc: Add new GuC interface defines and structures

Add new GuC interface defines and structures while maintaining old ones in parallel. Cc: John Harrison Signed-off-by: Matthew Brost --- .../gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 18 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 41 +++ 2 files changed, 59 insert

[Intel-gfx] [RFC PATCH 54/97] drm/i915/guc: Ensure G2H response has space in buffer

Ensure G2H response has space in the buffer before sending H2G CTB as the GuC can't handle any backpressure on the G2H interface. Signed-off-by: John Harrison Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/intel_guc.h| 13 +++- drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c

[Intel-gfx] [RFC PATCH 38/97] drm/i915/guc: Optimize CTB writes and reads

CTB writes are now in the path of command submission and should be optimized for performance. Rather than reading CTB descriptor values (e.g. head, tail, size) which could result in accesses across the PCIe bus, store shadow local copies and only read/write the descriptor values when absolutely nec

[Intel-gfx] [RFC PATCH 58/97] drm/i915: Add intel_context tracing

Add intel_context tracing. These trace points are particular helpful when debugging the GuC firmware and can be enabled via CONFIG_DRM_I915_LOW_LEVEL_TRACEPOINTS kernel config option. Cc: John Harrison Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/intel_context.c | 6 + .../g

[Intel-gfx] [RFC PATCH 68/97] drm/i915/guc: Handle context reset notification

GuC will issue a reset on detecting an engine hang and will notify the driver via a G2H message. The driver will service the notification by resetting the guilty context to a simple state or banning it completely. Cc: Matthew Brost Cc: John Harrison Signed-off-by: Matthew Brost --- drivers/gpu

[Intel-gfx] [RFC PATCH 29/97] drm/i915/guc: Update firmware to v60.1.2

From: John Harrison Signed-off-by: John Harrison Signed-off-by: Michal Wajdeczko Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 25 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c b

[Intel-gfx] [RFC PATCH 62/97] drm/i915/guc: Disable bonding extension with GuC submission

Update the bonding extension to return -ENODEV when using GuC submission as this extension fundamentally will not work with the GuC submission interface. Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915/gem/i915_gem_context.c | 5 + 1 file changed, 5 insertions(+) diff --git a/drivers/

[Intel-gfx] [RFC PATCH 23/97] drm/i915/guc: Support per context scheduling policies

From: John Harrison GuC firmware v53.0.0 introduced per context scheduling policies. This includes changes to some of the ADS structures which are required to load the firmware even if not using GuC submission. Signed-off-by: John Harrison Signed-off-by: Matthew Brost --- drivers/gpu/drm/i915

[Intel-gfx] [RFC PATCH 32/97] drm/i915: Introduce i915_sched_engine object

Introduce i915_sched_engine object which is lower level data structure that i915_scheduler / generic code can operate on without touching execlist specific structures. This allows additional submission backends to be added without breaking the layer. Cc: Daniele Ceraolo Spurio Signed-off-by: Matt

[Intel-gfx] [RFC PATCH 66/97] drm/i915/guc: Add disable interrupts to guc sanitize

Add disable GuC interrupts to intel_guc_sanitize(). Part of this requires moving the guc_*_interrupt wrapper function into header file intel_guc.h. Signed-off-by: Matthew Brost Cc: Daniele Ceraolo Spurio ct); } +static inline void intel_guc_reset_interrupts(struct intel_guc *guc) +{ + gu

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