Re: [Intel-gfx] [PATCH 0/4] drm/i915: Silence pipe tracepoint WARNs

2021-03-05 Thread Jani Nikula
On Thu, 04 Mar 2021, Ville Syrjala wrote: > From: Ville Syrjälä > > I believe this should silence the WARN spew from the > pipe disable tracepoint Steve reported. And I tossed in > a few other minor improvements as well. On some of the patches I'll just have to take your word for what it says in

Re: [Intel-gfx] [PATCH v3] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9

2021-03-05 Thread Tvrtko Ursulin
On 05/03/2021 00:53, Chris Wilson wrote: Quoting Chris Wilson (2021-03-04 11:56:16) Quoting Chris Wilson (2021-03-04 09:19:24) Quoting Tvrtko Ursulin (2021-03-04 09:12:26) On 02/03/2021 06:27, Cooper Chiou wrote: WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Gen9 to resolve VP8

Re: [Intel-gfx] [PATCH v2 6/7] drm/i915: rename DISP_STEPPING->DISPLAY_STEP and GT_STEPPING->GT_STEP

2021-03-05 Thread Chris Wilson
Quoting Jani Nikula (2021-02-24 08:46:55) > On Tue, 23 Feb 2021, Lucas De Marchi wrote: > > On Tue, Feb 23, 2021 at 05:35:11PM +0200, Jani Nikula wrote: > >>Matter of taste. STEP matches the enums. > >> > >>Signed-off-by: Jani Nikula > >>--- > >> drivers/gpu/drm/i915/display/intel_display_power.c

Re: [Intel-gfx] [PATCH v3] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9

2021-03-05 Thread Chris Wilson
Quoting Tvrtko Ursulin (2021-03-05 09:23:02) > I am not sure if PC8 and DMC could also be involved from what Cooper was > saying in a different thread. Maybe another CI run without the DMC, both > ffs and fls. Another for limiting cstates. Disabling the dmc leaves the display code in an inconsis

[Intel-gfx] [PATCH RESEND][next] drm/i915/gem: Fix fall-through warnings for Clang

2021-03-05 Thread Gustavo A. R. Silva
In preparation to enable -Wimplicit-fallthrough for Clang, fix a warning by explicitly adding a return statement instead of letting the code fall through to the next case. Link: https://github.com/KSPP/linux/issues/115 Signed-off-by: Gustavo A. R. Silva --- drivers/gpu/drm/i915/gem/i915_gem_shri

[Intel-gfx] [PATCH v5] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9

2021-03-05 Thread Cooper Chiou
WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Gen9 to resolve VP8 hardware encoding system hang up on GT1 sku for ChromiumOS projects Slice specific MMIO read inaccurate so MGSR needs to be programmed appropriately to get correct reads from these slicet-related MMIOs. It dictates that

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gem: Fix fall-through warnings for Clang

2021-03-05 Thread Patchwork
== Series Details == Series: drm/i915/gem: Fix fall-through warnings for Clang URL : https://patchwork.freedesktop.org/series/87690/ State : success == Summary == CI Bug Log - changes from CI_DRM_9835 -> Patchwork_19758 Summary --- *

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev7)

2021-03-05 Thread Patchwork
== Series Details == Series: drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev7) URL : https://patchwork.freedesktop.org/series/81764/ State : success == Summary == CI Bug Log - changes from CI_DRM_9835 -> Patchwork_19759

Re: [Intel-gfx] [PATCH v3] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9

2021-03-05 Thread Chris Wilson
Quoting Chris Wilson (2021-03-05 12:20:45) > Quoting Tvrtko Ursulin (2021-03-05 09:23:02) > > I am not sure if PC8 and DMC could also be involved from what Cooper was > > saying in a different thread. Maybe another CI run without the DMC, both > > ffs and fls. Another for limiting cstates. > > D

Re: [Intel-gfx] [PATCH v3] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9

2021-03-05 Thread Chiou, Cooper
After switched to ffs from fls in "patch v5"(https://patchwork.freedesktop.org/series/81764/#rev7), now CI result is PASS no regression in wa_verify warning. @Chen, Rong Could you please run “phoronix-test-suite.supertuxkart.1024x768.Fullscreen.Ultimate.1.GranParadisoIsland.frames_per_second”

[Intel-gfx] [PATCH 0/6] drm/i915: More SAGV related fixes/cleanups

2021-03-05 Thread Ville Syrjala
From: Ville Syrjälä The SAGV watermark handling is still a bit of mess. Let's try to clean it up a bit more, and in the process fix up a couple of minor mishaps. Ville Syrjälä (6): drm/i915: Fix enabled_planes bitmask drm/i915: Tighten SAGV constraint for pre-tgl drm/i915: Check SAGV wm mi

[Intel-gfx] [PATCH 1/6] drm/i915: Fix enabled_planes bitmask

2021-03-05 Thread Ville Syrjala
From: Ville Syrjälä The enabled_planes bitmask was supposed to track logically enabled planes (ie. fb!=NULL and crtc!=NULL), but instead we end up putting even disabled planes into the bitmask since intel_plane_atomic_check_with_state() only takes the early exit if the plane was disabled and stay

[Intel-gfx] [PATCH 2/6] drm/i915: Tighten SAGV constraint for pre-tgl

2021-03-05 Thread Ville Syrjala
From: Ville Syrjälä Say we have two planes enabled with watermarks configured as follows: plane A: wm0=enabled/can_sagv=false, wm1=enabled/can_sagv=true plane B: wm0=enabled/can_sagv=true, wm1=disabled This is possible since the latency we use to calculate can_sagv may not be the same for both

[Intel-gfx] [PATCH 3/6] drm/i915: Check SAGV wm min_ddb_alloc rather than plane_res_b

2021-03-05 Thread Ville Syrjala
From: Ville Syrjälä For non-transition watermarks we are supposed to check min_ddb_alloc rather than plane_res_b when determining if we have enough DDB space for it. A bit too much copy pasta made me check the wrong thing. Cc: Stanislav Lisovskiy Fixes: df4a50a35e2c ("drm/i915: Zero out SAGV wm

[Intel-gfx] [PATCH 5/6] drm/i915: Extract skl_check_wm_level() and skl_check_nv12_wm_level()

2021-03-05 Thread Ville Syrjala
From: Ville Syrjälä Make the code more typo proof by extracting small helpers that do the "do we have enough DDB for the WM level?" checks in a consistent manner. Cc: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_pm.c | 58 - 1

[Intel-gfx] [PATCH 6/6] drm/i915: s/plane_res_b/blocks/ etc.

2021-03-05 Thread Ville Syrjala
From: Ville Syrjälä Rename a bunch of the skl+ watermark struct members to have sensible names. Avoids me having to think what plane_res_b/etc. means. Cc: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 24 +-- .../drm/i915/display/intel_d

[Intel-gfx] [PATCH 4/6] drm/i915: Calculate min_ddb_alloc for trans_wm

2021-03-05 Thread Ville Syrjala
From: Ville Syrjälä Let's make all the "do we have enough DDB for this WM level?" checks use min_ddb_alloc. To achieve that we need to populate this for the transition watermarks as well. Cc: Stanislav Lisovskiy Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_pm.c | 8 +--- 1

Re: [Intel-gfx] [PATCH 0/4] drm/i915: Silence pipe tracepoint WARNs

2021-03-05 Thread Ville Syrjälä
On Thu, Mar 04, 2021 at 02:20:22PM -0500, Steven Rostedt wrote: > On Thu, 4 Mar 2021 19:04:17 +0200 > Ville Syrjala wrote: > > > From: Ville Syrjälä > > > > I believe this should silence the WARN spew from the > > pipe disable tracepoint Steve reported. And I tossed in > > a few other minor im

Re: [Intel-gfx] [PATCH v3] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9

2021-03-05 Thread Tvrtko Ursulin
On 05/03/2021 15:24, Chiou, Cooper wrote: After switched to ffs from fls in "patch v5"(https://patchwork.freedesktop.org/series/81764/#rev7), now CI result is PASS no regression in wa_verify warning. @Chen, Rong Could you please run “phoronix-test-suite.supertuxkart.1024x768.Fullscreen.Ultima

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: More SAGV related fixes/cleanups

2021-03-05 Thread Patchwork
== Series Details == Series: drm/i915: More SAGV related fixes/cleanups URL : https://patchwork.freedesktop.org/series/87699/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5c14f9d5eac8 drm/i915: Fix enabled_planes bitmask ebc6a3e5fe6d drm/i915: Tighten SAGV constraint for pre-t

Re: [Intel-gfx] [patch 2/7] drm/vmgfx: Replace kmap_atomic()

2021-03-05 Thread Roland Scheidegger
On 03.03.21 14:20, Thomas Gleixner wrote: > From: Thomas Gleixner > > There is no reason to disable pagefaults and preemption as a side effect of > kmap_atomic_prot(). > > Use kmap_local_page_prot() instead and document the reasoning for the > mapping usage with the given pgprot. > > Remove the

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: More SAGV related fixes/cleanups

2021-03-05 Thread Patchwork
== Series Details == Series: drm/i915: More SAGV related fixes/cleanups URL : https://patchwork.freedesktop.org/series/87699/ State : success == Summary == CI Bug Log - changes from CI_DRM_9836 -> Patchwork_19760 Summary --- **SUCCES

[Intel-gfx] [PATCH] Revert "drm/i915: Propagate errors on awaiting already signaled fences"

2021-03-05 Thread Jason Ekstrand
This reverts commit 9e31c1fe45d555a948ff66f1f0e3fe1f83ca63f7. Ever since that commit, we've been having issues where a hang in one client can propagate to another. In particular, a hang in an app can propagate to the X server which causes the whole desktop to lock up. Signed-off-by: Jason Ekstra

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Revert "drm/i915: Propagate errors on awaiting already signaled fences"

2021-03-05 Thread Patchwork
== Series Details == Series: Revert "drm/i915: Propagate errors on awaiting already signaled fences" URL : https://patchwork.freedesktop.org/series/87704/ State : warning == Summary == $ dim checkpatch origin/drm-tip d9e330a82c56 Revert "drm/i915: Propagate errors on awaiting already signaled

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gem: Fix fall-through warnings for Clang

2021-03-05 Thread Patchwork
== Series Details == Series: drm/i915/gem: Fix fall-through warnings for Clang URL : https://patchwork.freedesktop.org/series/87690/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9835_full -> Patchwork_19758_full Summary --

Re: [Intel-gfx] [PATCH] Revert "drm/i915: Propagate errors on awaiting already signaled fences"

2021-03-05 Thread Chris Wilson
Quoting Jason Ekstrand (2021-03-05 17:05:46) > This reverts commit 9e31c1fe45d555a948ff66f1f0e3fe1f83ca63f7. Ever > since that commit, we've been having issues where a hang in one client > can propagate to another. In particular, a hang in an app can propagate > to the X server which causes the w

[Intel-gfx] ✓ Fi.CI.BAT: success for Revert "drm/i915: Propagate errors on awaiting already signaled fences"

2021-03-05 Thread Patchwork
== Series Details == Series: Revert "drm/i915: Propagate errors on awaiting already signaled fences" URL : https://patchwork.freedesktop.org/series/87704/ State : success == Summary == CI Bug Log - changes from CI_DRM_9836 -> Patchwork_19761

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev7)

2021-03-05 Thread Patchwork
== Series Details == Series: drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev7) URL : https://patchwork.freedesktop.org/series/81764/ State : success == Summary == CI Bug Log - changes from CI_DRM_9835_full -> Patchwork_19759_full ==

[Intel-gfx] [PATCH] i915/query: Correlate engine and cpu timestamps with better accuracy

2021-03-05 Thread Umesh Nerlige Ramappa
Perf measurements rely on CPU and engine timestamps to correlate events of interest across these time domains. Current mechanisms get these timestamps separately and the calculated delta between these timestamps lack enough accuracy. To improve the accuracy of these time measurements to within a f

Re: [Intel-gfx] [PATCH 1/3] drm/i915/display: Move dc3co_exitline variable to struct intel_psr

2021-03-05 Thread Mun, Gwan-gyeong
On Wed, 2021-03-03 at 18:54 +0200, Ville Syrjälä wrote: > On Wed, Mar 03, 2021 at 06:41:59PM +0200, Gwan-gyeong Mun wrote: > > dc3co_exitline is indirectly called by intel_psr_compute_config(). > > And it will not be changed until the next calling of > > intel_psr_compute_config(). So in order to u

Re: [Intel-gfx] [PATCH 3/3] drm/i915/display: Introduce new intel_psr_pause/resume function

2021-03-05 Thread Mun, Gwan-gyeong
On Wed, 2021-03-03 at 10:05 -0800, Souza, Jose wrote: > patch 1 is a nack for the reasons that Ville explained. > > This one could be simplified even more. > > intel_psr_enable_locked() should have all the dev_priv->psr.* > initialization from crtc_state + intel_dp_compute_psr_vsc_sdp(). > Then a

[Intel-gfx] [PATCH v2 1/3] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct

2021-03-05 Thread Gwan-gyeong Mun
It replaces dc3co_enabled with dc3co_exitline on intel_psr struct. And it saves dc3co_exitline, not dc3co_enabled, so we can use dc3co_exitline without intel_crtc_state on other psr internal function like as intel_psr_enable_source(). v2: Do not mutate externally visible state in .compute_config()

[Intel-gfx] [PATCH v2 2/3] drm/i915/display: Remove a redundant function argument from intel_psr_enable_source()

2021-03-05 Thread Gwan-gyeong Mun
It removes intel_crtc_state from function argument of intel_psr_enable_source() in order to use intel_psr_enable_source() without intel_crtc_state on other psr internal functions. And we can get cpu_trancoder from intel_psr, therefore we don't need to pass intel_crtc_state to this function. Cc: Jo

[Intel-gfx] [PATCH v2 3/3] drm/i915/display: Introduce new intel_psr_pause/resume function

2021-03-05 Thread Gwan-gyeong Mun
This introduces the following function that can enable and disable psr without intel_crtc_state/drm_connector_state when intel_psr is already enabled with current intel_crtc_state and drm_connector_state information. - intel_psr_pause(): Pause current PSR. it deactivates current psr state. - intel

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: More SAGV related fixes/cleanups

2021-03-05 Thread Patchwork
== Series Details == Series: drm/i915: More SAGV related fixes/cleanups URL : https://patchwork.freedesktop.org/series/87699/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9836_full -> Patchwork_19760_full Summary ---

[Intel-gfx] ✓ Fi.CI.BAT: success for i915/query: Correlate engine and cpu timestamps with better accuracy (rev3)

2021-03-05 Thread Patchwork
== Series Details == Series: i915/query: Correlate engine and cpu timestamps with better accuracy (rev3) URL : https://patchwork.freedesktop.org/series/87552/ State : success == Summary == CI Bug Log - changes from CI_DRM_9836 -> Patchwork_19762 ===

[Intel-gfx] [PATCH] i915/perf: Start hrtimer only if sampling the OA buffer

2021-03-05 Thread Umesh Nerlige Ramappa
SAMPLE_OA parameter enables sampling of OA buffer and results in a call to init the OA buffer which initializes the OA unit head/tail pointers. The OA_EXPONENT parameter controls the periodicity of the OA reports in the OA buffer and results in starting a hrtimer. Before gen12, all use cases requi

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/3] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct

2021-03-05 Thread Patchwork
== Series Details == Series: series starting with [v2,1/3] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct URL : https://patchwork.freedesktop.org/series/87717/ State : success == Summary == CI Bug Log - changes from CI_DRM_9836 -> Patchwork_19763 =

[Intel-gfx] ✓ Fi.CI.BAT: success for i915/perf: Start hrtimer only if sampling the OA buffer (rev2)

2021-03-05 Thread Patchwork
== Series Details == Series: i915/perf: Start hrtimer only if sampling the OA buffer (rev2) URL : https://patchwork.freedesktop.org/series/87524/ State : success == Summary == CI Bug Log - changes from CI_DRM_9836 -> Patchwork_19764 Summary

[Intel-gfx] ✗ Fi.CI.IGT: failure for Revert "drm/i915: Propagate errors on awaiting already signaled fences"

2021-03-05 Thread Patchwork
== Series Details == Series: Revert "drm/i915: Propagate errors on awaiting already signaled fences" URL : https://patchwork.freedesktop.org/series/87704/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9836_full -> Patchwork_19761_full ==

[Intel-gfx] ✗ Fi.CI.IGT: failure for i915/query: Correlate engine and cpu timestamps with better accuracy (rev3)

2021-03-05 Thread Patchwork
== Series Details == Series: i915/query: Correlate engine and cpu timestamps with better accuracy (rev3) URL : https://patchwork.freedesktop.org/series/87552/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9836_full -> Patchwork_19762_full =

Re: [Intel-gfx] [RFC PATCH 8/9] drm/gem: Associate GEM objects with drm cgroup

2021-03-05 Thread Brian Welty
On 2/11/2021 7:34 AM, Daniel Vetter wrote: > On Wed, Feb 10, 2021 at 02:00:57PM -0800, Brian Welty wrote: >> >> On 2/9/2021 2:54 AM, Daniel Vetter wrote: >>> On Tue, Jan 26, 2021 at 01:46:25PM -0800, Brian Welty wrote: This patch adds tracking of which cgroup to make charges against for a >>

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/3] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct

2021-03-05 Thread Patchwork
== Series Details == Series: series starting with [v2,1/3] drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr struct URL : https://patchwork.freedesktop.org/series/87717/ State : success == Summary == CI Bug Log - changes from CI_DRM_9836_full -> Patchwork_19763_full ===

[Intel-gfx] ✗ Fi.CI.IGT: failure for i915/perf: Start hrtimer only if sampling the OA buffer (rev2)

2021-03-05 Thread Patchwork
== Series Details == Series: i915/perf: Start hrtimer only if sampling the OA buffer (rev2) URL : https://patchwork.freedesktop.org/series/87524/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9836_full -> Patchwork_19764_full ===

Re: [Intel-gfx] [PATCH v3] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9

2021-03-05 Thread Chiou, Cooper
Hi Rong, Please help to trigger 3D performance test on several Gen9 CI test boxes which different fusing sku with/without “patch v5”. Thanks, Best Regards, Cooper > On Mar 6, 2021, at 12:01 AM, Tvrtko Ursulin > wrote: > >  >> On 05/03/2021 15:24, Chiou, Cooper wrote: >> After switched to ffs

Re: [Intel-gfx] [PATCH v5] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9

2021-03-05 Thread Chiou, Cooper
Hi Rong, Please help to trigger 3D performance test on several Gen9 CI test boxes which different fusing sku with/without “patch v5”, and share the results. Thanks, Best Regards, Cooper ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://