Re: [Intel-gfx] [Linaro-mm-sig] [PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap

2021-03-01 Thread Daniel Vetter
On Sat, Feb 27, 2021 at 9:06 AM Thomas Hellström (Intel) wrote: > On 2/26/21 2:28 PM, Daniel Vetter wrote: > > So I think it stops gup. But I haven't verified at all. Would be good > > if Christian can check this with some direct io to a buffer in system > > memory. > > Hmm, > > Docs (again vm_nor

[Intel-gfx] add remap_pfn_range_notrack instead of reinventing it in i915

2021-03-01 Thread Christoph Hellwig
Hi all, i915 has some reason to want to avoid the track_pfn_remap overhead in remap_pfn_range. Add a function to the core VM to do just that rather than reinventing the functionality poorly in the driver. Note that the remap_io_sg path does get exercises when using Xorg on my Thinkpad X1, so thi

[Intel-gfx] [PATCH 1/2] mm: add remap_pfn_range_notrack

2021-03-01 Thread Christoph Hellwig
Add a version of remap_pfn_range that does not call track_pfn_range. This will be used to fix horrible abuses of VM internals in the i915 driver. Signed-off-by: Christoph Hellwig --- include/linux/mm.h | 2 ++ mm/memory.c| 52 -- 2 files chang

[Intel-gfx] [PATCH 2/2] i915: use remap_pfn_range_notrack

2021-03-01 Thread Christoph Hellwig
Use the remap_pfn_range_notrack helper instead of directly messing with PTEs. Signed-off-by: Christoph Hellwig --- drivers/gpu/drm/i915/i915_mm.c | 101 + 1 file changed, 26 insertions(+), 75 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_mm.c b/drivers/gpu/

Re: [Intel-gfx] [PATCH 1/7] drm/i915: Fix TGL+ plane SAGV watermark programming

2021-03-01 Thread Lisovskiy, Stanislav
On Fri, Feb 26, 2021 at 05:31:58PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > When we switch between SAGV on vs. off we need to reprogram all > plane wateramrks accordingly. Currently skl_wm_add_affected_planes() > totally ignores the SAGV watermark and just assumes we will use > the n

Re: [Intel-gfx] [Linaro-mm-sig] [PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap

2021-03-01 Thread Intel
Hi, On 3/1/21 9:28 AM, Daniel Vetter wrote: On Sat, Feb 27, 2021 at 9:06 AM Thomas Hellström (Intel) wrote: On 2/26/21 2:28 PM, Daniel Vetter wrote: So I think it stops gup. But I haven't verified at all. Would be good if Christian can check this with some direct io to a buffer in system memo

Re: [Intel-gfx] [PATCH 2/7] drm/i915: Zero out SAGV wm when we don't have enough DDB for it

2021-03-01 Thread Lisovskiy, Stanislav
On Fri, Feb 26, 2021 at 05:31:59PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Let's handle the SAGV WM0 more like the other wm levels and just > totally zero it out when we don't have the DDB space to back it > up. Reviewed-by: Stanislav Lisovskiy > > Cc: Stanislav Lisovskiy > Sig

Re: [Intel-gfx] add remap_pfn_range_notrack instead of reinventing it in i915

2021-03-01 Thread Daniel Vetter
On Mon, Mar 01, 2021 at 09:33:18AM +0100, Christoph Hellwig wrote: > Hi all, > > i915 has some reason to want to avoid the track_pfn_remap overhead in > remap_pfn_range. Add a function to the core VM to do just that rather > than reinventing the functionality poorly in the driver. It's not _notr

Re: [Intel-gfx] add remap_pfn_range_notrack instead of reinventing it in i915

2021-03-01 Thread Christoph Hellwig
On Mon, Mar 01, 2021 at 09:44:13AM +0100, Daniel Vetter wrote: > On Mon, Mar 01, 2021 at 09:33:18AM +0100, Christoph Hellwig wrote: > > Hi all, > > > > i915 has some reason to want to avoid the track_pfn_remap overhead in > > remap_pfn_range. Add a function to the core VM to do just that rather >

[Intel-gfx] ✗ Fi.CI.BAT: failure for HDCP 2.2 MST fixes

2021-03-01 Thread Patchwork
== Series Details == Series: HDCP 2.2 MST fixes URL : https://patchwork.freedesktop.org/series/87475/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9816 -> Patchwork_19734 Summary --- **FAILURE** Serious unknown c

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] mm: add remap_pfn_range_notrack

2021-03-01 Thread Patchwork
== Series Details == Series: series starting with [1/2] mm: add remap_pfn_range_notrack URL : https://patchwork.freedesktop.org/series/87479/ State : warning == Summary == $ dim checkpatch origin/drm-tip 4595e8c87551 mm: add remap_pfn_range_notrack -:21: CHECK:PARENTHESIS_ALIGNMENT: Alignment

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] mm: add remap_pfn_range_notrack

2021-03-01 Thread Patchwork
== Series Details == Series: series starting with [1/2] mm: add remap_pfn_range_notrack URL : https://patchwork.freedesktop.org/series/87479/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./dr

Re: [Intel-gfx] [Linaro-mm-sig] [PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap

2021-03-01 Thread Daniel Vetter
On Mon, Mar 01, 2021 at 09:39:53AM +0100, Thomas Hellström (Intel) wrote: > Hi, > > On 3/1/21 9:28 AM, Daniel Vetter wrote: > > On Sat, Feb 27, 2021 at 9:06 AM Thomas Hellström (Intel) > > wrote: > > > On 2/26/21 2:28 PM, Daniel Vetter wrote: > > > > So I think it stops gup. But I haven't verifie

Re: [Intel-gfx] -stable regression in Intel graphics, introduced in Linux 5.10.9

2021-03-01 Thread Greg KH
On Sun, Feb 28, 2021 at 09:05:45PM +0100, Diego Calleja wrote: > El domingo, 28 de febrero de 2021 16:14:54 (CET) Greg KH escribió: > > Is this the same issue reported here: > > > > https://lore.kernel.org/r/f1070486-891a-8ec0-0390-b9aeb0317...@redhat.com > > ? > > I just tested current mainl

Re: [Intel-gfx] [PATCH 3/7] drm/i915: Print wm changes if sagv_wm0 changes

2021-03-01 Thread Lisovskiy, Stanislav
On Fri, Feb 26, 2021 at 05:32:00PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Let's consider sagv_wm0 as well when deciding whether to dump > out the watermark changes. > > Cc: Stanislav Lisovskiy > Signed-off-by: Ville Syrjälä > --- > drivers/gpu/drm/i915/intel_pm.c | 3 ++- > 1 f

Re: [Intel-gfx] add remap_pfn_range_notrack instead of reinventing it in i915

2021-03-01 Thread Daniel Vetter
On Mon, Mar 01, 2021 at 09:45:59AM +0100, Christoph Hellwig wrote: > On Mon, Mar 01, 2021 at 09:44:13AM +0100, Daniel Vetter wrote: > > On Mon, Mar 01, 2021 at 09:33:18AM +0100, Christoph Hellwig wrote: > > > Hi all, > > > > > > i915 has some reason to want to avoid the track_pfn_remap overhead in

Re: [Intel-gfx] [PATCH 4/7] drm/i915: Stuff SAGV watermark into a sub-structure

2021-03-01 Thread Lisovskiy, Stanislav
On Fri, Feb 26, 2021 at 05:32:01PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > We'll want a SAGV transition watermark as well. Prepare > for that by collecting SAGV wm0 into a sub-strcture. > > Cc: Stanislav Lisovskiy > Signed-off-by: Ville Syrjälä Reviewed-by: Stanislav Lisovskiy

Re: [Intel-gfx] [PATCH 5/7] drm/i915: Introduce SAGV transtion watermark

2021-03-01 Thread Lisovskiy, Stanislav
On Fri, Feb 26, 2021 at 05:32:02PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Seems to me that if we calculate WM0 using the bumped up SAGV latency > we need to calculate the transition watermark accordingly. Track it > alongside the other watermarks. > > Cc: Stanislav Lisovskiy > Si

Re: [Intel-gfx] [Linaro-mm-sig] [PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap

2021-03-01 Thread Intel
On 3/1/21 10:05 AM, Daniel Vetter wrote: On Mon, Mar 01, 2021 at 09:39:53AM +0100, Thomas Hellström (Intel) wrote: Hi, On 3/1/21 9:28 AM, Daniel Vetter wrote: On Sat, Feb 27, 2021 at 9:06 AM Thomas Hellström (Intel) wrote: On 2/26/21 2:28 PM, Daniel Vetter wrote: So I think it stops gup. B

Re: [Intel-gfx] [PATCH 6/7] drm/i915: Check tgl+ SAGV watermarks properly

2021-03-01 Thread Lisovskiy, Stanislav
On Fri, Feb 26, 2021 at 05:32:03PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > We know which WM0 (normal vs. SAGV) we supposedly programmed > into the hardware, so just check against that instead of accepting > either watermark as valid. > > Cc: Stanislav Lisovskiy > Signed-off-by: Vi

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] mm: add remap_pfn_range_notrack

2021-03-01 Thread Patchwork
== Series Details == Series: series starting with [1/2] mm: add remap_pfn_range_notrack URL : https://patchwork.freedesktop.org/series/87479/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9816 -> Patchwork_19735 Summary ---

Re: [Intel-gfx] [PATCH 7/7] drm/i915: Clean up verify_wm_state()

2021-03-01 Thread Lisovskiy, Stanislav
On Fri, Feb 26, 2021 at 05:32:04PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä > > Get rid of the nonsense cursor special case in verify_wm_state() > by just iterating through all the planes. And let's use the > canonical [PLANE:..] style in the debug prints while at it. Great move! Revie

Re: [Intel-gfx] [Linaro-mm-sig] [PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap

2021-03-01 Thread Christian König
Am 01.03.21 um 10:21 schrieb Thomas Hellström (Intel): On 3/1/21 10:05 AM, Daniel Vetter wrote: On Mon, Mar 01, 2021 at 09:39:53AM +0100, Thomas Hellström (Intel) wrote: Hi, On 3/1/21 9:28 AM, Daniel Vetter wrote: On Sat, Feb 27, 2021 at 9:06 AM Thomas Hellström (Intel) wrote: On 2/26/21

Re: [Intel-gfx] -stable regression in Intel graphics, introduced in Linux 5.10.9

2021-03-01 Thread Greg KH
On Mon, Mar 01, 2021 at 11:11:13AM +0100, Diego Calleja wrote: > El lunes, 1 de marzo de 2021 10:09:10 (CET) Greg KH escribió: > > I do not see all 3 commits in Linus's tree already, am I missing > > something? > > > > What are the git ids that you are looking at? > > I used grep on the git log,

Re: [Intel-gfx] [RFC PATCH 0/9] drm/i915/spi: discrete graphics internal spi

2021-03-01 Thread Jani Nikula
On Wed, 17 Feb 2021, "Winkler, Tomas" wrote: >> >> On Tue, 16 Feb 2021, Tomas Winkler wrote: >> > Intel discrete graphic devices have internal spi storage, that holds >> > firmware and oprom images. The spi device is exposed to the user space >> > via mtd framework to be accessed during manufact

Re: [Intel-gfx] [Linaro-mm-sig] [PATCH 1/2] dma-buf: Require VM_PFNMAP vma for mmap

2021-03-01 Thread Daniel Vetter
On Mon, Mar 1, 2021 at 11:17 AM Christian König wrote: > > > > Am 01.03.21 um 10:21 schrieb Thomas Hellström (Intel): > > > > On 3/1/21 10:05 AM, Daniel Vetter wrote: > >> On Mon, Mar 01, 2021 at 09:39:53AM +0100, Thomas Hellström (Intel) > >> wrote: > >>> Hi, > >>> > >>> On 3/1/21 9:28 AM, Daniel

Re: [Intel-gfx] [5.10.y regression] i915 clear-residuals mitigation is causing gfx issues

2021-03-01 Thread Greg Kroah-Hartman
On Mon, Feb 15, 2021 at 03:26:59PM +0100, Greg Kroah-Hartman wrote: > On Sun, Feb 14, 2021 at 05:00:44PM +0100, Hans de Goede wrote: > > Hi, > > > > On 2/11/21 1:26 PM, Hans de Goede wrote: > > > Hi, > > > > > > On 2/11/21 11:49 AM, Chris Wilson wrote: > > >> Quoting Hans de Goede (2021-02-11 10:

Re: [Intel-gfx] -stable regression in Intel graphics, introduced in Linux 5.10.9

2021-03-01 Thread Diego Calleja
El domingo, 28 de febrero de 2021 16:14:54 (CET) Greg KH escribió: > Is this the same issue reported here: > > https://lore.kernel.org/r/f1070486-891a-8ec0-0390-b9aeb0317...@redhat.com > ? I just tested current mainline (which already contains the three commits mentioned in the bugzilla),

Re: [Intel-gfx] -stable regression in Intel graphics, introduced in Linux 5.10.9

2021-03-01 Thread Diego Calleja
El lunes, 1 de marzo de 2021 10:09:10 (CET) Greg KH escribió: > I do not see all 3 commits in Linus's tree already, am I missing > something? > > What are the git ids that you are looking at? I used grep on the git log, the commits are there but seem to have different commit ids (except for the

[Intel-gfx] -stable regression in Intel graphics, introduced in Linux 5.10.9

2021-03-01 Thread Diego Calleja
Hi, There is a regression in Linux 5.10.9 that does not happen in 5.10.8. It is still there as of 5.11.1 This regression consists in graphics artifacts that will *only* start appearing after resuming from suspend. They don't happen immediately after resuming from suspend either, but after some

[Intel-gfx] [PATCH] drm/i915/display/vlv_dsi: Do no shut down displays on reboot if a DSI panel is used

2021-03-01 Thread Hans de Goede
After the recently added commit fe0f1e3bfdfe ("drm/i915: Shut down displays gracefully on reboot"), the DSI panel on a Cherry Trail based Predia Basic tablet would no longer properly light up after reboot. The backlight still turns back on after reboot, but the LCD shows an all black display. The

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display/vlv_dsi: Do no shut down displays on reboot if a DSI panel is used

2021-03-01 Thread Patchwork
== Series Details == Series: drm/i915/display/vlv_dsi: Do no shut down displays on reboot if a DSI panel is used URL : https://patchwork.freedesktop.org/series/87498/ State : warning == Summary == $ dim checkpatch origin/drm-tip 3994974850ed drm/i915/display/vlv_dsi: Do no shut down displays

[Intel-gfx] 2021 X.Org Board of Directions Nomination period ends next Sunday

2021-03-01 Thread Harry Wentland
Unfortunately my previous email seems to not have been received by many people. I will send this email separately to each mailing list to hopefully get better coverage. The nomination period is currently ongoing. So far we have received 3 nominations and will need at least 4 to fill the vacant

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/display/vlv_dsi: Do no shut down displays on reboot if a DSI panel is used

2021-03-01 Thread Patchwork
== Series Details == Series: drm/i915/display/vlv_dsi: Do no shut down displays on reboot if a DSI panel is used URL : https://patchwork.freedesktop.org/series/87498/ State : success == Summary == CI Bug Log - changes from CI_DRM_9818 -> Patchwork_19736 ===

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/display/vlv_dsi: Do no shut down displays on reboot if a DSI panel is used

2021-03-01 Thread Patchwork
== Series Details == Series: drm/i915/display/vlv_dsi: Do no shut down displays on reboot if a DSI panel is used URL : https://patchwork.freedesktop.org/series/87498/ State : success == Summary == CI Bug Log - changes from CI_DRM_9818_full -> Patchwork_19736_full =

[Intel-gfx] [WARNING] v5.12-rc1 in intel_pipe_disable tracepoint

2021-03-01 Thread Steven Rostedt
On my test box with latest v5.12-rc1, running with all trace events enabled, I consistently trigger this warning. It appears to get triggered by the trace_intel_pipe_disable() code. -- Steve [ cut here ] i915 :00:02.0: drm_WARN_ON_ONCE(drm_drv_uses_atomic_modeset(

Re: [Intel-gfx] [WARNING] v5.12-rc1 in intel_pipe_disable tracepoint

2021-03-01 Thread Ville Syrjälä
On Mon, Mar 01, 2021 at 11:59:46AM -0500, Steven Rostedt wrote: > > On my test box with latest v5.12-rc1, running with all trace events > enabled, I consistently trigger this warning. > > It appears to get triggered by the trace_intel_pipe_disable() code. > > -- Steve > > [ cut her

Re: [Intel-gfx] [WARNING] v5.12-rc1 in intel_pipe_disable tracepoint

2021-03-01 Thread Steven Rostedt
On Mon, 1 Mar 2021 19:20:59 +0200 Ville Syrjälä wrote: > > ilk_crtc_disable+0x85/0x390 [i915] > > But this part is confusing me. intel_crtc_get_vblank_counter() is > only supposed to do drm_crtc_accurate_vblank_count() fallback when > the hardware lacks a working frame counter, and that sho

[Intel-gfx] [PATCH v2 00/16] Introduce Intel PXP

2021-03-01 Thread Daniele Ceraolo Spurio
PXP (Protected Xe Path) is an i915 component, available on GEN12+, that helps to establish the hardware protected session and manage the status of the alive software session, as well as its life cycle. Several major functional changes compared to v1: - Termination is issued on runtime resume as we

[Intel-gfx] [PATCH v2 01/16] drm/i915/pxp: Define PXP component interface

2021-03-01 Thread Daniele Ceraolo Spurio
This will be used for communication between the i915 driver and the mei one. Defining it in a stand-alone patch to avoid circualr dependedencies between the patches modifying the 2 drivers. Split out from an original patch from Huang, Sean Z v2: rename the component struct (Rodrigo) Signed-off-

[Intel-gfx] [PATCH v2 02/16] mei: pxp: export pavp client to me client bus

2021-03-01 Thread Daniele Ceraolo Spurio
From: Vitaly Lubart Export PAVP client to work with i915 driver, for binding it uses kernel component framework. Signed-off-by: Vitaly Lubart Signed-off-by: Tomas Winkler Signed-off-by: Daniele Ceraolo Spurio --- drivers/misc/mei/Kconfig | 2 + drivers/misc/mei/Makefile | 1 +

[Intel-gfx] [PATCH v2 03/16] drm/i915/pxp: define PXP device flag and kconfig

2021-03-01 Thread Daniele Ceraolo Spurio
Ahead of the PXP implementation, define the relevant define flag and kconfig option. Signed-off-by: Daniele Ceraolo Spurio Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/Kconfig | 11 +++ drivers/gpu/drm/i915/i915_drv.h | 4 drivers/gpu/drm/i915/intel_devi

[Intel-gfx] [PATCH v2 04/16] drm/i915/pxp: allocate a vcs context for pxp usage

2021-03-01 Thread Daniele Ceraolo Spurio
The context is required to send the session termination commands to the VCS, which will be implemented in a follow-up patch. We can also use the presence of the context as a check of pxp initialization completion. v2: use perma-pinned context (Chris) Signed-off-by: Daniele Ceraolo Spurio Cc: Chr

[Intel-gfx] [PATCH v2 05/16] drm/i915/pxp: set KCR reg init during the boot time

2021-03-01 Thread Daniele Ceraolo Spurio
Set the KCR init during the boot time, which is required by hardware, to allow us doing further protection operation such as sending commands to GPU or TEE. Signed-off-by: Huang, Sean Z Signed-off-by: Daniele Ceraolo Spurio Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/pxp/intel_pxp.c | 2

[Intel-gfx] [PATCH v2 06/16] drm/i915/pxp: Implement funcs to create the TEE channel

2021-03-01 Thread Daniele Ceraolo Spurio
From: "Huang, Sean Z" Implement the funcs to create the TEE channel, so kernel can send the TEE commands directly to TEE for creating the arbitrary (default) session. v2: fix locking, don't pollute dev_priv (Chris) Signed-off-by: Huang, Sean Z Signed-off-by: Daniele Ceraolo Spurio Cc: Chris W

[Intel-gfx] [PATCH v2 07/16] drm/i915/pxp: Create the arbitrary session after boot

2021-03-01 Thread Daniele Ceraolo Spurio
From: "Huang, Sean Z" Create the arbitrary session, with the fixed session id 0xf, after system boot, for the case that application allocates the protected buffer without establishing any protection session. Because the hardware requires at least one alive session for protected buffer creation. T

[Intel-gfx] [PATCH v2 08/16] drm/i915/pxp: Implement arb session teardown

2021-03-01 Thread Daniele Ceraolo Spurio
From: "Huang, Sean Z" Teardown is triggered when the display topology changes and no long meets the secure playback requirement, and hardware trashes all the encryption keys for display. Additionally, we want to emit a teardown operation to make sure we're clean on boot and resume v2: emit in th

[Intel-gfx] [PATCH v2 09/16] drm/i915/pxp: Implement PXP irq handler

2021-03-01 Thread Daniele Ceraolo Spurio
From: "Huang, Sean Z" The HW will generate a teardown interrupt when session termination is required, which requires i915 to submit a terminating batch. Once the HW is done with the termination it will generate another interrupt, at which point it is safe to re-create the session. v2: use struct

[Intel-gfx] [PATCH v2 10/16] drm/i915/pxp: Enable PXP power management

2021-03-01 Thread Daniele Ceraolo Spurio
From: "Huang, Sean Z" During the power event S3+ sleep/resume, hardware will lose all the encryption keys for every hardware session, even though the software session state was marked as alive after resume. So to handle such case, PXP should unconditionally terminate the hardware sessions and cle

[Intel-gfx] [PATCH v2 11/16] drm/i915/pxp: interface for creation of protected contexts

2021-03-01 Thread Daniele Ceraolo Spurio
Usage of protected objects, coming in a follow-up patch, will be restricted to protected contexts. Contexts can only be marked as protected at creation time and they must be both bannable and not recoverable. When a PXP teardown occurs, all gem contexts marked as protected that have been used at l

[Intel-gfx] [PATCH v2 12/16] drm/i915/uapi: introduce drm_i915_gem_create_ext

2021-03-01 Thread Daniele Ceraolo Spurio
From: Bommu Krishnaiah Same old gem_create but with now with extensions support. This is needed to support various upcoming usecases. For now we use the extensions mechanism to support PAVP. Signed-off-by: Bommu Krishnaiah Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Matthew Auld Cc:

[Intel-gfx] [PATCH v2 13/16] drm/i915/pxp: User interface for Protected buffer

2021-03-01 Thread Daniele Ceraolo Spurio
From: Bommu Krishnaiah This api allow user mode to create Protected buffers. Only contexts marked as protected are allowed to operate on protected buffers. We only allow setting the flags at creation time. All protected objects that have backing storage will be considered invalid when the sessi

[Intel-gfx] [PATCH v2 14/16] drm/i915/pxp: Add plane decryption support

2021-03-01 Thread Daniele Ceraolo Spurio
From: Anshuman Gupta Add support to enable/disable PLANE_SURF Decryption Request bit. It requires only to enable plane decryption support when following condition met. 1. PXP session is enabled. 2. Buffer object is protected. v2: - Used gen fb obj user_flags instead gem_object_metadata. [Krishna

[Intel-gfx] [PATCH v2 15/16] drm/i915/pxp: black pixels on pxp disabled

2021-03-01 Thread Daniele Ceraolo Spurio
From: Anshuman Gupta When protected sufaces has flipped and pxp session is disabled display black pixels by using plane color CTM correction. Cc: Ville Syrjälä Cc: Gaurav Kumar Cc: Shankar Uma Signed-off-by: Anshuman Gupta Signed-off-by: Daniele Ceraolo Spurio --- .../drm/i915/display/skl_

[Intel-gfx] [PATCH v2 16/16] drm/i915/pxp: enable PXP for integrated Gen12

2021-03-01 Thread Daniele Ceraolo Spurio
Note that discrete cards can support PXP as well, but we haven't tested on those yet so keeping it disabled for now. Signed-off-by: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/i915_pci.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Intel PXP (rev2)

2021-03-01 Thread Patchwork
== Series Details == Series: Introduce Intel PXP (rev2) URL : https://patchwork.freedesktop.org/series/86798/ State : warning == Summary == $ dim checkpatch origin/drm-tip d3a311348975 drm/i915/pxp: Define PXP component interface -:30: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s)

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Introduce Intel PXP (rev2)

2021-03-01 Thread Patchwork
== Series Details == Series: Introduce Intel PXP (rev2) URL : https://patchwork.freedesktop.org/series/86798/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +drivers/gpu/drm/i915/gt/intel_reset.

[Intel-gfx] ✓ Fi.CI.BAT: success for Introduce Intel PXP (rev2)

2021-03-01 Thread Patchwork
== Series Details == Series: Introduce Intel PXP (rev2) URL : https://patchwork.freedesktop.org/series/86798/ State : success == Summary == CI Bug Log - changes from CI_DRM_9818 -> Patchwork_19737 Summary --- **SUCCESS** No regres

[Intel-gfx] ✓ Fi.CI.IGT: success for Introduce Intel PXP (rev2)

2021-03-01 Thread Patchwork
== Series Details == Series: Introduce Intel PXP (rev2) URL : https://patchwork.freedesktop.org/series/86798/ State : success == Summary == CI Bug Log - changes from CI_DRM_9818_full -> Patchwork_19737_full Summary --- **SUCCESS**

[Intel-gfx] [PATCH] i915/perf: Start hrtimer only if sampling the OA buffer

2021-03-01 Thread Umesh Nerlige Ramappa
SAMPLE_OA parameter enables sampling of OA buffer and results in a call to init the OA buffer which initializes the OA unit head/tail pointers. The OA_EXPONENT parameter controls the periodicity of the OA reports in the OA buffer and results in starting a hrtimer. Before gen12, all use cases requi

Re: [Intel-gfx] [PATCH] i915/perf: Start hrtimer only if sampling the OA buffer

2021-03-01 Thread Dixit, Ashutosh
On Mon, 01 Mar 2021 16:01:41 -0800, Nerlige Ramappa, Umesh wrote: > > SAMPLE_OA parameter enables sampling of OA buffer and results in a call > to init the OA buffer which initializes the OA unit head/tail pointers. > The OA_EXPONENT parameter controls the periodicity of the OA reports in > the OA

[Intel-gfx] ✓ Fi.CI.BAT: success for i915/perf: Start hrtimer only if sampling the OA buffer

2021-03-01 Thread Patchwork
== Series Details == Series: i915/perf: Start hrtimer only if sampling the OA buffer URL : https://patchwork.freedesktop.org/series/87524/ State : success == Summary == CI Bug Log - changes from CI_DRM_9818 -> Patchwork_19738 Summary --

[Intel-gfx] ✓ Fi.CI.IGT: success for i915/perf: Start hrtimer only if sampling the OA buffer

2021-03-01 Thread Patchwork
== Series Details == Series: i915/perf: Start hrtimer only if sampling the OA buffer URL : https://patchwork.freedesktop.org/series/87524/ State : success == Summary == CI Bug Log - changes from CI_DRM_9818_full -> Patchwork_19738_full Summ

[Intel-gfx] [PATCH] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9

2021-03-01 Thread Cooper Chiou
WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Gen9 to resolve VP8 hardware encoding system hang up on GT1 sku for ChromiumOS projects Reference: HSD#1508045018,1405586840, BSID#0575 Cc: Ville Syrjälä Cc: Rodrigo Vivi Cc: Jani Nikula Cc: Chris Wilson Cc: Tvrtko Ursulin Cc: William

[Intel-gfx] [PATCH v4] vfio/pci: Add support for opregion v2.1+

2021-03-01 Thread Fred Gao
Before opregion version 2.0 VBT data is stored in opregion mailbox #4, However, When VBT data exceeds 6KB size and cannot be within mailbox #4 starting from opregion v2.0+, Extended VBT region, next to opregion, is used to hold the VBT data, so the total size will be opregion size plus extended VBT

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev4)

2021-03-01 Thread Patchwork
== Series Details == Series: drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev4) URL : https://patchwork.freedesktop.org/series/81764/ State : warning == Summary == $ dim checkpatch origin/drm-tip 0c4bb5d01f88 drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmi

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev4)

2021-03-01 Thread Patchwork
== Series Details == Series: drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev4) URL : https://patchwork.freedesktop.org/series/81764/ State : success == Summary == CI Bug Log - changes from CI_DRM_9819 -> Patchwork_19739

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev4)

2021-03-01 Thread Patchwork
== Series Details == Series: drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev4) URL : https://patchwork.freedesktop.org/series/81764/ State : success == Summary == CI Bug Log - changes from CI_DRM_9819_full -> Patchwork_19739_full ==

[Intel-gfx] [PATCH v3] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9

2021-03-01 Thread Cooper Chiou
WaProgramMgsrForCorrectSliceSpecificMmioReads applies for Gen9 to resolve VP8 hardware encoding system hang up on GT1 sku for ChromiumOS projects Slice specific MMIO read inaccurate so MGSR needs to be programmed appropriately to get correct reads from these slicet-related MMIOs. It dictates that

[Intel-gfx] ✗ Fi.CI.BAT: failure for vfio/pci: Add support for opregion v2.0+ (rev4)

2021-03-01 Thread Patchwork
== Series Details == Series: vfio/pci: Add support for opregion v2.0+ (rev4) URL : https://patchwork.freedesktop.org/series/84494/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9819 -> Patchwork_19740 Summary --- **F

[Intel-gfx] ✓ Fi.CI.IGT: success for vfio/pci: Add support for opregion v2.0+ (rev4)

2021-03-01 Thread Patchwork
== Series Details == Series: vfio/pci: Add support for opregion v2.0+ (rev4) URL : https://patchwork.freedesktop.org/series/84494/ State : success == Summary == CI Bug Log - changes from CI_DRM_9819_full -> Patchwork_19740_full Summary

Re: [Intel-gfx] [PATCH v3] drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9

2021-03-01 Thread Chiou, Cooper
Hi Tvrtko, This WaProgramMgsrForCorrectSliceSpecificMmioReads info can be found on bspec WA#0575 and it's necessary for GT subslice fuse sku on PC7 exit case while running VP8 hw encode, it impacted CrOS projects since google disabled VP8 HW encode feature on Gen9 sku, so that's why we need this

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev5)

2021-03-01 Thread Patchwork
== Series Details == Series: drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev5) URL : https://patchwork.freedesktop.org/series/81764/ State : success == Summary == CI Bug Log - changes from CI_DRM_9819 -> Patchwork_19741

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev5)

2021-03-01 Thread Patchwork
== Series Details == Series: drm/i915: Enable WaProgramMgsrForCorrectSliceSpecificMmioReads for Gen9 (rev5) URL : https://patchwork.freedesktop.org/series/81764/ State : success == Summary == CI Bug Log - changes from CI_DRM_9819_full -> Patchwork_19741_full ==