== Series Details ==
Series: series starting with [CI,1/3] drm/i915/gt: Move engine setup out of
set_default_submission
URL : https://patchwork.freedesktop.org/series/86603/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9720 -> Patchwork_19567
The different submission backends each have their own preferred
behaviour and interrupt setup. Let each handle their own interrupts.
This becomes more useful later as we to extract the use of auxiliary
state in the interrupt handler that is backend specific.
v2: An overabundance of caution is alw
Currently, we allocate exactly the VMA requested for the framebuffer and
rely on filling the whole of the GGTT with scratch pages to catch when
VT-d prefetches beyond the bounds of the surface. However, this means
that we have to scrub the GGTT on startup and resume, and on recent HW
this is made e
On Wed, Feb 03, 2021 at 08:38:41AM +, Chris Wilson wrote:
> Currently, we allocate exactly the VMA requested for the framebuffer and
> rely on filling the whole of the GGTT with scratch pages to catch when
> VT-d prefetches beyond the bounds of the surface. However, this means
> that we have to
Set the cache coherency and status using the set-coherency helper.
Otherwise, we forget to mark the new pages as cache dirty.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/selftests/huge_pages.c | 14 +-
1 file changed, 5 insertions(+), 9 deletio
After running client_blt, we flush the object by changing its domain.
This causes us to wait forever instead of an bounded wait suitable for
the selftest timeout. So do an explicit wait with a suitable timeout --
which in turn means we have to limit the size of the object/blit to run
within reason.
After the memory-region test completes, it flushes the test by calling
set-to-cpu-domain. Use the igt_flush_test as it includes a timeout,
recovery and reports and error for miscreant tests.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/selftests/intel_memory_re
Instead of manipulating the object's cache domain, just use the device
coherent map to write the batch buffer.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
.../drm/i915/gem/selftests/i915_gem_context.c| 16 +---
1 file changed, 9 insertions(+), 7 deletions(-)
diff
Only perform the domain transition under the object lock, and push the
required waits to outside the lock.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_clflush.c | 9 +-
drivers/gpu/drm/i915/gem/i915_gem_clflush.h | 2 -
drivers/gpu/drm/i91
Let's prefer to use explicit request tracking and bounded timeouts in
our selftests.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
.../gpu/drm/i915/gt/selftest_workarounds.c| 106 +++---
1 file changed, 40 insertions(+), 66 deletions(-)
diff --git a/drivers/gpu/drm/
In construction the rpcs_query batch we know that it is device coherent
and ready for execution, the set-to-gtt-domain here is redudant.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 2 --
1 file changed, 2 deletions(-)
diff -
Since the vma's backing store is flushed upon first creation, remove the
manual calls to set-to-gtt-domain.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
.../gpu/drm/i915/gem/selftests/i915_gem_mman.c | 16
drivers/gpu/drm/i915/selftests/i915_vma.c| 6 ---
As per Bspec: 53655 Update PCI ids for Mobile BGA.
Cc: Jani Nikula
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: David Airlie
Cc: Daniel Vetter
Signed-off-by: Anand Moon
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index ebd0dd1c35b3..3be25768321d 100644
--- a/include/drm/i
Quoting Ville Syrjälä (2021-02-03 09:00:54)
> On Wed, Feb 03, 2021 at 08:38:41AM +, Chris Wilson wrote:
> > Currently, we allocate exactly the VMA requested for the framebuffer and
> > rely on filling the whole of the GGTT with scratch pages to catch when
> > VT-d prefetches beyond the bounds o
From: Ville Syrjälä
The BXT/GLK DPLL can't generate certain frequencies. We already
reject the 233-240MHz range on both. But on GLK the DPLL max
frequency was bumped from 300MHz to 594MHz, so now we get to
also worry about the 446-480MHz range (double the original
problem range). Reject any frequ
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/gt: Move engine setup out of
set_default_submission (rev2)
URL : https://patchwork.freedesktop.org/series/86603/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9721 -> Patchwork_19568
=
On 02/02/2021 09:54, Umesh Nerlige Ramappa wrote:
Validity of an OA format is checked by using a sparse array of formats
per gen. Instead maintain a mask of supported formats for a platform in
the perf object.
Signed-off-by: Umesh Nerlige Ramappa
Nice cleanup : Reviewed-by: Lionel Landwerlin
On Wed, 03 Feb 2021, Stephen Rothwell wrote:
> Hi all,
>
> Commit
>
> 44c5bd08518c ("*** HAX FOR CI *** Revert "rtc: mc146818: Detect and handle
> broken RTCs"")
>
> is missing a Signed-off-by from its author and committer.
>
> Reverts are commits as well.
It's a hack on top of the tree to unb
On Tue, 2021-02-02 at 15:43 +, Chris Wilson wrote:
> After calling lock_set_subclass() the lock _must_ be used, or else
> lockdep's internal nr_used_locks becomes unbalanced. Extract the
> little
> utility function to i915_utils.c
>
> Signed-off-by: Chris Wilson
> Cc: Thomas Hellström
> ---
== Series Details ==
Series: drm/i915: Apply VT-d scanout adjustment to the VMA
URL : https://patchwork.freedesktop.org/series/86625/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9721 -> Patchwork_19569
Summary
---
On Mon, Feb 01, 2021 at 03:21:35PM -0800, Brian Welty wrote:
>
> On 1/28/2021 7:00 PM, Xingyou Chen wrote:
> > On 2021/1/27 上午5:46, Brian Welty wrote:
> >
> >> We'd like to revisit the proposal of a GPU cgroup controller for managing
> >> GPU devices but with just a basic set of controls. This s
From: Tvrtko Ursulin
Walking the client "list" makes assumptions about the order of active and
free slots which means we need to sort the array after every update.
Patch is mostly just code movement with the only functional difference of
eliminating two subsequent scans with no sort in between T
On 01/02/2021 12:07, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2021-02-01 11:57:56)
From: Tvrtko Ursulin
Slight improvement with regards to wrapping header components to fit
console width. If a single element is wider than max it can still
overflow but it should now work better for practic
== Series Details ==
Series: series starting with [CI,1/8] drm/i915/selftests: Set cache status for
huge_gem_object
URL : https://patchwork.freedesktop.org/series/86626/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9721 -> Patchwork_19570
Quoting Tvrtko Ursulin (2021-02-03 10:31:04)
>
> On 01/02/2021 12:07, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2021-02-01 11:57:56)
> >> From: Tvrtko Ursulin
> >>
> >> Slight improvement with regards to wrapping header components to fit
> >> console width. If a single element is wider than
Quoting Tvrtko Ursulin (2021-02-03 10:26:01)
> From: Tvrtko Ursulin
>
> Walking the client "list" makes assumptions about the order of active and
> free slots which means we need to sort the array after every update.
>
> Patch is mostly just code movement with the only functional difference of
>
From: Colin Ian King
There is a spelling mistake in a drm_dbg message. Fix it.
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/i
Exercise rescheduling priority inheritance around a sequence of requests
that wrap around all the engines.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../gpu/drm/i915/selftests/i915_scheduler.c | 215 ++
1 file changed, 215 insertions(+)
diff --git a/drivers/
Lift the ability to defer a request until later from execlists into the
common layer.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../drm/i915/gt/intel_execlists_submission.c | 57 +++--
drivers/gpu/drm/i915/i915_scheduler.c | 63 +--
drivers
Now that we no longer switch back and forth between guc and execlists,
we no longer need to restore the backend's vfunc and can leave them set
after initialisation. The only catch is that we lose the submission on
wedging and still need to reset the submit_request vfunc on unwedging.
Signed-off-by
The core of the scheduling algorithm is that we compute the topological
order of the fence DAG. Knowing that we have a DAG, we should be able to
use a DFS to compute the topological sort in linear time. However,
during the conversion of the recursive algorithm into an iterative one,
the memoization
In the process of preparing to reuse the request submission logic for
other backends, lift it out of the execlists backend. It already
operates on the common structs, so just a matter of moving and renaming.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../drm/i915/gt/intel_execl
In anticipation of wanting to be able to call pi from underneath an
engine's active.lock, rework the priority inheritance to primarily work
along an engine's priority queue, delegating any other engine that the
chain may traverse to a worker. This reduces the global spinlock from
governing the enti
In the process of preparing to reuse the request submission logic for
other backends, lift it out of the execlists backend.
While this operates on the common structs, we do have a bit of backend
knowledge, which is harmless for !lrc but still unsightly.
Signed-off-by: Chris Wilson
Reviewed-by: T
As a topological sort, we expect it to run in linear graph time,
O(V+E). In removing the recursion, it is no longer a DFS but rather a
BFS, and performs as O(VE). Let's demonstrate how bad this is with a few
examples, and build a few test cases to verify a potential fix.
Signed-off-by: Chris Wilso
The different submission backends each have their own preferred
behaviour and interrupt setup. Let each handle their own interrupts.
This becomes more useful later as we to extract the use of auxiliary
state in the interrupt handler that is backend specific.
v2: An overabundance of caution is alw
Make the ability to suspend and resume a request and its dependents
generic.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../drm/i915/gt/intel_execlists_submission.c | 167 +-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 8 +-
drivers/gpu/drm/i915/i915_sche
Looking to the future, we want to set the scheduling attributes
explicitly and so replace the generic engine->schedule() with the more
direct i915_request_set_priority()
What it loses in removing the 'schedule' name from the function, it
gains in having an explicit entry point with a stated goal.
Since we setup the submission method for the engines once, it is easy to
assign an enum and use that instead of probing into the backends.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine.h | 8 +++-
drivers/gpu/drm/i915/gt/inte
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/gt: Move engine setup out of
set_default_submission (rev2)
URL : https://patchwork.freedesktop.org/series/86603/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9721_full -> Patchwork_19568_full
===
On Thu, Jan 28, 2021 at 09:13:49PM +0200, Imre Deak wrote:
> On Wed, Jan 27, 2021 at 08:19:09PM +0200, Imre Deak wrote:
> > At least on some TGL platforms PUNIT wants to access some display HW
> > registers, but it doesn't handle display power managment (disabling DC
> > states as required) and so
Quoting Tejas Upadhyay (2020-11-30 12:48:55)
> Removing force probe protection from RKL platform. Did
> not observe warnings, errors, flickering or any visual
> defects while doing ordinary tasks like browsing and
> editing documents in a two monitor setup.
>
> Signed-off-by: Tejas Upadhyay
We n
From: Tvrtko Ursulin
Useful to mimick top view.
Signed-off-by: Tvrtko Ursulin
---
man/intel_gpu_top.rst | 2 +-
tools/intel_gpu_top.c | 46 +++
2 files changed, 34 insertions(+), 14 deletions(-)
diff --git a/man/intel_gpu_top.rst b/man/intel_gpu_top.rs
From: Tvrtko Ursulin
It is useful to let the user know what is the currently active sort mode.
Signed-off-by: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 15 +--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index 584aa2
Quoting Tvrtko Ursulin (2021-02-03 11:44:55)
> From: Tvrtko Ursulin
>
> It is useful to let the user know what is the currently active sort mode.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> tools/intel_gpu_top.c | 15 +--
> 1 file changed, 13 insertions(+), 2 deletions(-)
>
> diff -
On 03/02/2021 11:47, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2021-02-03 11:44:55)
From: Tvrtko Ursulin
It is useful to let the user know what is the currently active sort mode.
Signed-off-by: Tvrtko Ursulin
---
tools/intel_gpu_top.c | 15 +--
1 file changed, 13 insertion
Quoting Tvrtko Ursulin (2021-02-03 11:44:56)
> From: Tvrtko Ursulin
>
> Useful to mimick top view.
>
> Signed-off-by: Tvrtko Ursulin
> ---
> man/intel_gpu_top.rst | 2 +-
> tools/intel_gpu_top.c | 46 +++
> 2 files changed, 34 insertions(+), 14 deletion
== Series Details ==
Series: drm/i915: Apply VT-d scanout adjustment to the VMA
URL : https://patchwork.freedesktop.org/series/86625/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9721_full -> Patchwork_19569_full
Summary
-
For the PTEs we get an LM bit, to signal whether the page resides in
SMEM or LMEM.
v2: just use gen8_pte_encode for dg1
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Venkata Sandeep Dhanalakota
--
The vm insert_page is useful to insert a vma-less page into the GGTT,
which so far is always to map something through the mappable aperture,
usually when the entire VMA doesn't fit, or if we specifically don't
want to hog it, since it's generally quite limited in size.
On platforms including DG1 t
From: Zbigniew Kempczyński
In preparation for Xe HP multi-tile architecture with multiple memory
regions, we need to be able differentiate multiple instances of device
local-memory.
Signed-off-by: Zbigniew Kempczyński
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/gt/intel_gt.c
For the PTEs we get an LM bit, to signal whether the page resides in
SMEM or LMEM.
Based on a patch from Michel Thierry.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 19 ---
drivers/gpu/drm/i91
Quoting Matthew Auld (2021-02-03 12:11:18)
> The vm insert_page is useful to insert a vma-less page into the GGTT,
> which so far is always to map something through the mappable aperture,
> usually when the entire VMA doesn't fit, or if we specifically don't
> want to hog it, since it's generally q
>From some contexts, we may not be allowed to wait during request
construction. For example, in the powermanagement handler that should
never block (as the engine was idle) and the driver would be crippled if
we did. Similarly, the user may request that the execbuf does not block,
and so would pref
== Series Details ==
Series: series starting with [CI,1/8] drm/i915/selftests: Set cache status for
huge_gem_object
URL : https://patchwork.freedesktop.org/series/86626/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9721_full -> Patchwork_19570_full
==
On 03/02/2021 11:00, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2021-02-03 10:31:04)
On 01/02/2021 12:07, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2021-02-01 11:57:56)
From: Tvrtko Ursulin
Slight improvement with regards to wrapping header components to fit
console width. If a single
Quoting Matthew Auld (2021-02-03 14:11:16)
> From: Zbigniew Kempczyński
>
> In preparation for Xe HP multi-tile architecture with multiple memory
> regions, we need to be able differentiate multiple instances of device
> local-memory.
Would be good to comment here on where this name is used, and
Quoting Brian Welty (2021-01-26 23:46:24)
> Single control below is added to DRM cgroup controller in order to track
> user execution time for GPU devices. It is up to device drivers to
> charge execution time to the cgroup via drm_cgroup_try_charge().
>
> sched.runtime
> Read-only value,
For the PTEs we get an LM bit, to signal whether the page resides in
SMEM or LMEM.
v2: just use gen8_pte_encode for dg1
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Venkata Sandeep Dhanalakota
--
From: Zbigniew Kempczyński
In preparation for Xe HP multi-tile architecture with multiple memory
regions, we need to be able differentiate multiple instances of device
local-memory.
Note that the region name is just to give it a human friendly
identifier, instead of using class/instance which al
For the PTEs we get an LM bit, to signal whether the page resides in
SMEM or LMEM.
Based on a patch from Michel Thierry.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 23 ++-
drivers/gpu/drm
Quoting Matthew Auld (2021-02-03 14:13:12)
> For the PTEs we get an LM bit, to signal whether the page resides in
> SMEM or LMEM.
>
> v2: just use gen8_pte_encode for dg1
>
> Signed-off-by: Matthew Auld
> Cc: Joonas Lahtinen
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Niranjana Vi
Quoting Matthew Auld (2021-02-03 14:13:13)
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h
> b/drivers/gpu/drm/i915/gt/intel_gtt.h
> index 4a1d9b5cc75b..55873663d37f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
> @@ -85,7 +85,8 @@ typedef u64 ge
Quoting Matthew Auld (2021-02-03 14:13:11)
> From: Zbigniew Kempczyński
>
> In preparation for Xe HP multi-tile architecture with multiple memory
> regions, we need to be able differentiate multiple instances of device
> local-memory.
>
> Note that the region name is just to give it a human frie
>From some contexts, we may not be allowed to wait during request
construction. For example, in the powermanagement handler that should
never block (as the engine was idle) and the driver would be crippled if
we did. Similarly, the user may request that the execbuf does not block,
and so would pref
>From some contexts, we may not be allowed to wait during request
construction. For example, in the powermanagement handler that should
never block (as the engine was idle) and the driver would be crippled if
we did. Similarly, the user may request that the execbuf does not block,
and so would pref
From: Zbigniew Kempczyński
In preparation for Xe HP multi-tile architecture with multiple memory
regions, we need to be able differentiate multiple instances of device
local-memory.
Note that the region name is just to give it a human friendly
identifier, instead of using class/instance which al
For the PTEs we get an LM bit, to signal whether the page resides in
SMEM or LMEM.
v2: just use gen8_pte_encode for dg1
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Venkata Sandeep Dhanalakota
Re
For the PTEs we get an LM bit, to signal whether the page resides in
SMEM or LMEM.
Based on a patch from Michel Thierry.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 24 +
== Series Details ==
Series: drm/i915/adl_s: ADL-S platform Update PCI ids for Mobile BGA
URL : https://patchwork.freedesktop.org/series/86627/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9725 -> Patchwork_19571
Summary
-
On Wed, Feb 03, 2021 at 01:40:05PM +0200, Ville Syrjälä wrote:
> On Thu, Jan 28, 2021 at 09:13:49PM +0200, Imre Deak wrote:
> > On Wed, Jan 27, 2021 at 08:19:09PM +0200, Imre Deak wrote:
> > > At least on some TGL platforms PUNIT wants to access some display HW
> > > registers, but it doesn't handl
== Series Details ==
Series: drm/i915: Reject 446-480MHz HDMI clock on GLK
URL : https://patchwork.freedesktop.org/series/86631/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9725 -> Patchwork_19572
Summary
---
**SUC
== Series Details ==
Series: drm/i915/display: fix spelling mistake "Couldnt" -> "Couldn't"
URL : https://patchwork.freedesktop.org/series/86637/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9725 -> Patchwork_19573
Summary
> -Original Message-
> From: Intel-gfx On Behalf Of
> Matthew Auld
> Sent: Wednesday, February 3, 2021 7:24 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Chris Wilson
> Subject: [Intel-gfx] [PATCH v3 3/3] drm/i915/gtt/dg1: add PTE_LM plumbing
> for GGTT
>
> For the PTEs we get an LM
Exercise rescheduling priority inheritance around a sequence of requests
that wrap around all the engines.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../gpu/drm/i915/selftests/i915_scheduler.c | 215 ++
1 file changed, 215 insertions(+)
diff --git a/drivers/
Looking to the future, we want to set the scheduling attributes
explicitly and so replace the generic engine->schedule() with the more
direct i915_request_set_priority()
What it loses in removing the 'schedule' name from the function, it
gains in having an explicit entry point with a stated goal.
Lift the ability to defer a request until later from execlists into the
common layer.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../drm/i915/gt/intel_execlists_submission.c | 57 +++--
drivers/gpu/drm/i915/i915_scheduler.c | 63 +--
drivers
Make the ability to suspend and resume a request and its dependents
generic.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../drm/i915/gt/intel_execlists_submission.c | 167 +-
drivers/gpu/drm/i915/gt/selftest_execlists.c | 8 +-
drivers/gpu/drm/i915/i915_sche
In the process of preparing to reuse the request submission logic for
other backends, lift it out of the execlists backend. It already
operates on the common structs, so just a matter of moving and renaming.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../drm/i915/gt/intel_execl
In anticipation of wanting to be able to call pi from underneath an
engine's active.lock, rework the priority inheritance to primarily work
along an engine's priority queue, delegating any other engine that the
chain may traverse to a worker. This reduces the global spinlock from
governing the enti
As a topological sort, we expect it to run in linear graph time,
O(V+E). In removing the recursion, it is no longer a DFS but rather a
BFS, and performs as O(VE). Let's demonstrate how bad this is with a few
examples, and build a few test cases to verify a potential fix.
Signed-off-by: Chris Wilso
The core of the scheduling algorithm is that we compute the topological
order of the fence DAG. Knowing that we have a DAG, we should be able to
use a DFS to compute the topological sort in linear time. However,
during the conversion of the recursive algorithm into an iterative one,
the memoization
In the process of preparing to reuse the request submission logic for
other backends, lift it out of the execlists backend.
While this operates on the common structs, we do have a bit of backend
knowledge, which is harmless for !lrc but still unsightly.
Signed-off-by: Chris Wilson
Reviewed-by: T
'--base' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Chris-Wilson/drm-i915-Prevent-waiting-inside-ring-construction-for-critical-sections/20210203-204914
base: git://anongit.freedesktop.org/drm-intel for-linux-next
conf
Quoting Tvrtko Ursulin (2021-02-03 13:12:05)
>
> On 03/02/2021 11:00, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2021-02-03 10:31:04)
> >>
> >> On 01/02/2021 12:07, Chris Wilson wrote:
> >>> Quoting Tvrtko Ursulin (2021-02-01 11:57:56)
> From: Tvrtko Ursulin
>
> Slight improve
On Wed, 3 Feb 2021 at 16:51, Tang, CQ wrote:
>
>
>
> > -Original Message-
> > From: Intel-gfx On Behalf Of
> > Matthew Auld
> > Sent: Wednesday, February 3, 2021 7:24 AM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Chris Wilson
> > Subject: [Intel-gfx] [PATCH v3 3/3] drm/i915/gtt/dg1:
From: Zbigniew Kempczyński
In preparation for Xe HP multi-tile architecture with multiple memory
regions, we need to be able differentiate multiple instances of device
local-memory.
Note that the region name is just to give it a human friendly
identifier, instead of using class/instance which al
For the PTEs we get an LM bit, to signal whether the page resides in
SMEM or LMEM.
Based on a patch from Michel Thierry.
BSpec: 45015
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 24
For the PTEs we get an LM bit, to signal whether the page resides in
SMEM or LMEM.
BSpec: 45040
v2: just use gen8_pte_encode for dg1
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Niranjana Vishwanathapura
Signed-off-by: Venkata Sandeep D
== Series Details ==
Series: series starting with [CI,01/12] drm/i915/gt: Move engine setup out of
set_default_submission
URL : https://patchwork.freedesktop.org/series/86639/
State : failure
== Summary ==
Applying: drm/i915/gt: Move engine setup out of set_default_submission
Using index info
== Series Details ==
Series: drm/i915: Prevent waiting inside ring construction for critical
sections (rev3)
URL : https://patchwork.freedesktop.org/series/86644/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c2a787bb37c7 drm/i915: Prevent waiting inside ring construction for
== Series Details ==
Series: drm/i915: Prevent waiting inside ring construction for critical
sections (rev3)
URL : https://patchwork.freedesktop.org/series/86644/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9725 -> Patchwork_19575
===
== Series Details ==
Series: series starting with [CI,1/9] drm/i915: Replace engine->schedule() with
a known request operation
URL : https://patchwork.freedesktop.org/series/86656/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
836be19c8de4 drm/i915: Replace engine->schedule()
== Series Details ==
Series: series starting with [CI,1/9] drm/i915: Replace engine->schedule() with
a known request operation
URL : https://patchwork.freedesktop.org/series/86656/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each com
> -Original Message-
> From: Matthew Auld
> Sent: Wednesday, February 3, 2021 9:03 AM
> To: Tang, CQ
> Cc: Auld, Matthew ; intel-
> g...@lists.freedesktop.org; Chris Wilson
> Subject: Re: [Intel-gfx] [PATCH v3 3/3] drm/i915/gtt/dg1: add PTE_LM
> plumbing for GGTT
>
> On Wed, 3 Feb 20
== Series Details ==
Series: series starting with [CI,1/9] drm/i915: Replace engine->schedule() with
a known request operation
URL : https://patchwork.freedesktop.org/series/86656/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9725 -> Patchwork_19576
=
On Wed, 3 Feb 2021 at 18:01, Tang, CQ wrote:
>
>
>
> > -Original Message-
> > From: Matthew Auld
> > Sent: Wednesday, February 3, 2021 9:03 AM
> > To: Tang, CQ
> > Cc: Auld, Matthew ; intel-
> > g...@lists.freedesktop.org; Chris Wilson
> > Subject: Re: [Intel-gfx] [PATCH v3 3/3] drm/i91
== Series Details ==
Series: series starting with [v4,1/3] drm/i915: Distinction of memory regions
URL : https://patchwork.freedesktop.org/series/86658/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9725 -> Patchwork_19577
== Series Details ==
Series: drm/i915/adl_s: ADL-S platform Update PCI ids for Mobile BGA
URL : https://patchwork.freedesktop.org/series/86627/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9725_full -> Patchwork_19571_full
== Series Details ==
Series: drm/i915: Reject 446-480MHz HDMI clock on GLK
URL : https://patchwork.freedesktop.org/series/86631/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9725_full -> Patchwork_19572_full
Summary
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