Verify that the virtual engine is destroyed when the context is lost if
persistence is disabled either on the context or system-wide.
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_balancer.c | 165 +
1 file changed, 165 insertions(+)
diff --git a/tests/i915
The reason why we did not enable preemption on Broadwater was due to
missing GPGPU workarounds. Since this only applies to rcs0, only
restrict rcs0 (and our global capabilities).
While this does not affect exposing a preemption capability to
userspace, it does affect our internal decisions on whet
The timeouts are frequent and expected. We will complain if we retry so
often as to lose patience and give up, so the cacophony from individual
complaints is redundant.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/dr
---
drivers/gpu/drm/i915/display/intel_display_types.h | 3 +++
drivers/gpu/drm/i915/i915_drv.h| 3 ---
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index
Since multiple connectors may run intel_dp_aux_xfer conncurrently, a
single global pm_qos does not suffice. (One connector may disable the
dma-latency boost prematurely while the second is still depending on
it.) Instead of a single global pm_qos, track the pm_qos request for
each intel_dp.
Fixes:
The timeouts are frequent and expected. We will complain if we retry so
often as to lose patience and give up, so the cacophony from individual
complaints is redundant.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_dp.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/dr
Since multiple connectors may run intel_dp_aux_xfer conncurrently, a
single global pm_qos does not suffice. (One connector may disable the
dma-latency boost prematurely while the second is still depending on
it.) Instead of a single global pm_qos, track the pm_qos request for
each intel_dp.
Fixes:
== Series Details ==
Series: drm/i915/gt: Only disable preemption on gen8 render engines
URL : https://patchwork.freedesktop.org/series/85311/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9533 -> Patchwork_19225
Summary
--
== Series Details ==
Series: drm/i915/dp: Remove aux xfer timeout debug message
URL : https://patchwork.freedesktop.org/series/85313/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9533 -> Patchwork_19226
Summary
---
== Series Details ==
Series: series starting with [1/2] pm-qos
URL : https://patchwork.freedesktop.org/series/85314/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a5980931c890 pm-qos
-:8: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
-:34: ERROR:M
== Series Details ==
Series: series starting with [1/2] pm-qos
URL : https://patchwork.freedesktop.org/series/85314/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/gt/intel
Re-enable secure dispatch for gen6/gen7, primarily to workaround the
command parser and overly zealous command validation on Haswell.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.
== Series Details ==
Series: series starting with [1/2] pm-qos
URL : https://patchwork.freedesktop.org/series/85314/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9533 -> Patchwork_19227
Summary
---
**FAILURE**
Se
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: Remove aux xfer timeout debug
message
URL : https://patchwork.freedesktop.org/series/85315/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d3af34a8e551 drm/i915/dp: Remove aux xfer timeout debug message
e8faa2
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: Remove aux xfer timeout debug
message
URL : https://patchwork.freedesktop.org/series/85315/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9533 -> Patchwork_19228
=
Chris Wilson writes:
> Declare that, under extreme circumstances, the shrinker may need to wait
> upon a request, in which case reset must not itself deadlock in order to
> ensure forward progress of the driver. That is since the shrinker may
> depend upon a reset, any reset cannot touch the shri
== Series Details ==
Series: drm/i915/dp: Remove aux xfer timeout debug message
URL : https://patchwork.freedesktop.org/series/85313/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9533_full -> Patchwork_19226_full
Summary
-
== Series Details ==
Series: drm/i915: Support secure dispatch on gen6/gen7
URL : https://patchwork.freedesktop.org/series/85323/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9533 -> Patchwork_19229
Summary
---
**SU
Chris Wilson writes:
> Since we use a flag within i915_request.flags to indicate when we have
> boosted the request (so that we only apply the boost) once, this can be
> used as the serialisation with i915_request_retire() to avoid having to
> explicitly take the i915_request.lock which is more h
== Series Details ==
Series: drm/i915: Support secure dispatch on gen6/gen7
URL : https://patchwork.freedesktop.org/series/85323/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9533_full -> Patchwork_19229_full
Summary
-
The reason why we did not enable preemption on Broadwater was due to
missing GPGPU workarounds. Since this only applies to rcs0, only
restrict rcs0 (and our global capabilities).
While this does not affect exposing a preemption capability to
userspace, it does affect our internal decisions on whet
Quoting Arnd Bergmann (2020-12-30 15:39:14)
> From: Arnd Bergmann
>
> Randconfig builds on 32-bit machines show lots of warnings for
> the i915 driver for incorrect bit masks like:
mask is a u8.
VCS0 is 2, I915_MAX_VCS 4
(u8 & GENMASK(5, 2)) >> 2
> drivers/gpu/drm/i915/gem/i915_gem_execbuffer
Fix the use of the legacy ring selection after the default context had
an engine map installed.
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_fence.c | 30 --
1 file changed, 16 insertions(+), 14 deletions(-)
diff --git a/tests/i915/gem_exec_fence.c b/tests/i91
Provide complete engine coverage by switching from the legacy ring
selection abi into the engine map.
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_whisper.c | 35 ---
1 file changed, 20 insertions(+), 15 deletions(-)
diff --git a/tests/i915/gem_exec_whispe
Cover all engines with the engine map API.
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_suspend.c | 69 +--
1 file changed, 25 insertions(+), 44 deletions(-)
diff --git a/tests/i915/gem_exec_suspend.c b/tests/i915/gem_exec_suspend.c
index 42b0ab705..a31dd6
On Wed, Dec 30, 2020 at 10:48:34AM +, Chris Wilson wrote:
> Since multiple connectors may run intel_dp_aux_xfer conncurrently, a
> single global pm_qos does not suffice. (One connector may disable the
> dma-latency boost prematurely while the second is still depending on
> it.) Instead of a sin
Since multiple connectors may run intel_dp_aux_xfer conncurrently, a
single global pm_qos does not suffice. (One connector may disable the
dma-latency boost prematurely while the second is still depending on
it.) Instead of a single global pm_qos, track the pm_qos request for
each intel_dp.
v2: Mo
On Wed, Dec 30, 2020 at 05:07:34PM +, Chris Wilson wrote:
> Since multiple connectors may run intel_dp_aux_xfer conncurrently, a
> single global pm_qos does not suffice. (One connector may disable the
> dma-latency boost prematurely while the second is still depending on
> it.) Instead of a sin
Since multiple connectors may run intel_dp_aux_xfer conncurrently, a
single global pm_qos does not suffice. (One connector may disable the
dma-latency boost prematurely while the second is still depending on
it.) Instead of a single global pm_qos, track the pm_qos request for
each intel_dp.
v2: Mo
== Series Details ==
Series: drm/i915/gt: Only disable preemption on gen8 render engines (rev2)
URL : https://patchwork.freedesktop.org/series/85311/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9534 -> Patchwork_19230
Sum
== Series Details ==
Series: series starting with [1/2] drm/i915/dp: Remove aux xfer timeout debug
message (rev2)
URL : https://patchwork.freedesktop.org/series/85315/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9534 -> Patchwork_19231
==
Since multiple connectors may run intel_dp_aux_xfer conncurrently, a
single global pm_qos does not suffice. (One connector may disable the
dma-latency boost prematurely while the second is still depending on
it.) Instead of a single global pm_qos, track the pm_qos request for
each intel_dp.
v2: Mo
== Series Details ==
Series: drm/i915/dp: Track pm_qos per connector
URL : https://patchwork.freedesktop.org/series/85333/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9534 -> Patchwork_19232
Summary
---
**FAILURE**
Chris Wilson writes:
> Since we process schedule-in of a context after submitting the request,
> if we decide to reset the context at that time, we also have to cancel
> the requets we have marked for submission.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> .../drm/i915
== Series Details ==
Series: drm/i915/dp: Track pm_qos per connector (rev2)
URL : https://patchwork.freedesktop.org/series/85333/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9534 -> Patchwork_19233
Summary
---
**SU
Since we process schedule-in of a context after submitting the request,
if we decide to reset the context at that time, we also have to cancel
the requets we have marked for submission.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
.../drm/i915/gt/intel_execlists_submission.c | 22
== Series Details ==
Series: drm/i915/gt: Only disable preemption on gen8 render engines (rev2)
URL : https://patchwork.freedesktop.org/series/85311/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9534_full -> Patchwork_19230_full
===
== Series Details ==
Series: drm/i915/gt: Cancel submitted requests upon context reset
URL : https://patchwork.freedesktop.org/series/85336/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9534 -> Patchwork_19234
Summary
Set the KCR init during the boot time, which is
required by hardware, to allow us doing further
protection operation such as sending commands to
GPU or TEE.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/g
PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
that helps to establish the hardware protected session and manage
the status of the alive software session, as well as its life cycle.
This patch series is to allow the kernel space to create and
manage a single hardware session (
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation. This arbitrary session n
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
software session state was marked as alive after resume. So to
handle such case, PXP should terminate all the hardware sessions
and cleanup all the software states after t
Implement the intel_pxp_gem_object_status() to allow i915 display
querying the current PXP session state. In the design, display
should not perform protection flip on the protected buffers if
there is no PXP session alive.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 9
Create the irq worker that serves as callback handler, those
callback stubs should be called while the hardware key teardown
occurs.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 4 +
drivers/gpu/drm/i915/i915_reg.h | 3 +-
drivers/gpu/drm/i915/
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. So as a result, PXP should
handle such case and terminate the type0 sessions, which including
arb session
Signed-off-by: Huang, Sean
Implement the functions to allow PXP to send a GPU command, in
order to terminate the hardware session, so hardware can recycle
this session slot for the next usage.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/pxp/intel_pxp.c |
From: Vitaly Lubart
Export PAVP client to work with i915_cp driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig | 1
From: Bommu Krishnaiah
This api allow user mode to create Protected buffer and context creation.
Signed-off-by: Bommu Krishnaiah
Cc: Telukuntla Sreedhar
Cc: Kondapally Kalyan
Cc: Gupta Anshuman
Cc: Huang Sean Z
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 ++--
drivers/gp
From: Bommu Krishnaiah
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen joonas.lahti...@linux.i
PXP (Protected Xe Path) is an i915 component, available on
GEN12+ that helps to establish the hardware protected session
and manage the status of the alive software session, as well
as its life cycle.
This patch series is to allow the kernel space to create and
manage a single hardware session (a.
From: Anshuman Gupta
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PAVP session is enabled.
2. Buffer object is protected.
v2:
- Rebased to libva_cp-drm-tip_tgl_cp tree.
- Used gen fb obj user
Implement the funcs to create the TEE channel, so kernel can
send the TEE commands directly to TEE for creating the arbitrary
(defualt) session.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i
== Series Details ==
Series: drm/i915/dp: Track pm_qos per connector (rev2)
URL : https://patchwork.freedesktop.org/series/85333/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9534_full -> Patchwork_19233_full
Summary
-
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev16)
URL : https://patchwork.freedesktop.org/series/84620/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8aed24199142 drm/i915/pxp: Introduce Intel PXP component
-:118: WARNING:FILE_PATH_CHANGES
On Mon, Dec 28, 2020 at 11:42:35AM +0530, Tejas Upadhyay wrote:
> We have TGP PCH support for Tigerlake and Rocketlake. Similarly
> now TGP PCH can be used with Cometlake CPU.
Based on the 'compatibility' section of bspec 49181, I think the TGP PCH
can technically be compatible with any gen9bc pla
On Wed, Dec 30, 2020 at 10:37:42AM +, Chris Wilson wrote:
> The timeouts are frequent and expected. We will complain if we retry so
> often as to lose patience and give up, so the cacophony from individual
> complaints is redundant.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matt Roper
>
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev16)
URL : https://patchwork.freedesktop.org/series/84620/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9534 -> Patchwork_19235
Summary
--
On Wed, 2020-12-30 at 16:02 -0800, Matt Roper wrote:
> On Wed, Dec 30, 2020 at 10:37:42AM +, Chris Wilson wrote:
> > The timeouts are frequent and expected. We will complain if we
> > retry so
> > often as to lose patience and give up, so the cacophony from
> > individual
> > complaints is redu
== Series Details ==
Series: drm/i915/gt: Cancel submitted requests upon context reset
URL : https://patchwork.freedesktop.org/series/85336/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9534_full -> Patchwork_19234_full
Su
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