== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev7)
URL : https://patchwork.freedesktop.org/series/84620/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0cae6c13cf00 drm/i915/pxp: Introduce Intel PXP component
-:111: WARNING:FILE_PATH_CHANGES:
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev7)
URL : https://patchwork.freedesktop.org/series/84620/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
Error: Cannot open file ./drivers/gpu/drm/i915/gt/intel_lrc.c
WARNING: kernel
On Thu, Dec 10, 2020 at 8:42 PM Thomas Gleixner wrote:
> First of all drivers have absolutely no business to dig into the internals
> of an irq descriptor. That's core code and subject to change. All of this
> information is readily available to /proc/interrupts in a safe and race
> free way.
>
>
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev7)
URL : https://patchwork.freedesktop.org/series/84620/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9474 -> Patchwork_19121
Summary
---
PXP (Protected Xe Path) is an i915 componment, available on GEN12+,
that helps to establish the hardware protected session and manage
the status of the alive software session, as well as its life cycle.
This patch series is to allow the kernel space to create and
manage a single hardware session (
Set the KCR init during the boot time, which is
required by hardware, to allow us doing further
protection operation such as sending commands to
GPU or TEE.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/g
Create the irq worker that serves as callback handler, those
callback stubs should be called while the hardware key teardown
occurs.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 4 +
drivers/gpu/drm/i915/i915_reg.h | 3 +-
drivers/gpu/drm/i915/
Implement the intel_pxp_gem_object_status() to allow i915 display
querying the current PXP session state. In the design, display
should not perform protection flip on the protected buffers if
there is no PXP session alive.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 9
PXP (Protected Xe Path) is an i915 componment, available on
GEN12+ that helps to establish the hardware protected session
and manage the status of the alive software session, as well
as its life cycle.
[commit #1 - #13]
This patch series is to allow the kernel space to create and
manage a single h
Implement the ioctl action to allow userspace driver sends TEE
commands via PXP ioctl, instead of TEE iotcl. So we can
centralize those protection operations at PXP.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 48 +---
drivers/gpu/drm/i915/pxp/inte
Teardown is triggered when the display topology changes and no
long meets the secure playback requirement, and hardware trashes
all the encryption keys for display. So as a result, PXP should
handle such case and terminate the type0 sessions, which including
arb session
Signed-off-by: Huang, Sean
From: Alexander Usyskin
Add API to support vtag in communication on mei bus.
Add mei_cldev_send_vtag, mei_cldev_recv_vtag and
mei_cldev_recv_nonblock_vtag functions to allow sending a message
with vtag set and to receive vtag of an incoming message.
Cc: Sean Z Huang
Signed-off-by: Alexander Us
Enable the PXP ioctl action to allow userspace driver to query the
PXP tag, which is a 32-bit bitwise value indicating the current
session info, including protection type, session id, and whether
the session is enabled.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c
With this ioctl action, userspace driver can reserve one or
multiple session slot/id assigned by kernel PXP, as the first
step of PXP session establishment flow. The session info is
stored in the session list structure.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile
Implement the functions to allow PXP to send a GPU command, in
order to terminate the hardware session, so hardware can recycle
this session slot for the next usage.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 1 +
drivers/gpu/drm/i915/pxp/intel_pxp_cmd.c | 156
Implement the PXP ioctl action to allow userspace driver to
terminate the hardware session and cleanup its software session
state. PXP sends the session termination command to GPU once
receves this ioctl action.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/pxp/intel_pxp.c | 10 +++
From: Bommu Krishnaiah
This api allow user mode to create Protected buffer and context creation.
Signed-off-by: Bommu Krishnaiah
Cc: Telukuntla Sreedhar
Cc: Kondapally Kalyan
Cc: Gupta Anshuman
Cc: Huang Sean Z
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 15 ++--
drivers/gp
During the power event S3+ sleep/resume, hardware will lose all the
encryption keys for every hardware session, even though the
software session state was marked as alive after resume. So to
handle such case, PXP should terminate all the hardware sessions
and cleanup all the software states after t
From: Vitaly Lubart
Export PAVP client to work with i915_cp driver,
for binding it uses kernel component framework.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
---
drivers/misc/mei/Kconfig | 2 +
drivers/misc/mei/Makefile | 1 +
drivers/misc/mei/pxp/Kconfig | 1
From: Tomas Winkler
Added vtag parameter to mei_pxp_send_message and
mei_pxp_receive_message functions.
Signed-off-by: Vitaly Lubart
Signed-off-by: Tomas Winkler
---
drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 4 ++--
drivers/misc/mei/pxp/mei_pxp.c | 10 ++
include/drm/i915_
From: Anshuman Gupta
Add support to enable/disable PLANE_SURF Decryption Request bit.
It requires only to enable plane decryption support when following
condition met.
1. PAVP session is enabled.
2. Buffer object is protected.
v2:
- Rebased to libva_cp-drm-tip_tgl_cp tree.
- Used gen fb obj user
In the previous commits, we have implemented the PXP ioctl
functions. Now we enable those handlers and expose them as PXP
ioctl, so allow the userspace driver can establish, set, or
destory the protected session via this ioctl.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/i915_drv.c
Implement the funcs to create the TEE channel, so kernel can
send the TEE commands directly to TEE for creating the arbitrary
(defualt) session.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/Makefile| 3 +-
drivers/gpu/drm/i915/i915_drv.c | 1 +
drivers/gpu/drm/i
Create the arbitrary session, with the fixed session id 0xf, after
system boot, for the case that application allocates the protected
buffer without establishing any protection session. Because the
hardware requires at least one alive session for protected buffer
creation. This arbitrary session n
With this ioctl action, userspace driver can set the session in
state "session in play", after dirver reserved the session slot/id
from kernel PXP, and sent the TEE commands to activate the
corresponding hardware session. Session state "session in play"
means this session is ready for secure playba
PXP should terminate the hardware session and cleanup the software
state gracefully when the application has established the
protection session, but doesn't close the session correctly due to
some cases like application crash.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/i915_drv.c
From: Bommu Krishnaiah
Same old gem_create but with now with extensions support. This is needed
to support various upcoming usecases. For now we use the extensions
mechanism to support PAVP.
Signed-off-by: Bommu Krishnaiah
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen joonas.lahti...@linux.i
Add several PXP-related reg into allowlist to allow user space
driver to read the those register values.
Signed-off-by: Huang, Sean Z
---
drivers/gpu/drm/i915/i915_reg.h | 6
drivers/gpu/drm/i915/intel_uncore.c | 50 -
2 files changed, 41 insertions(+), 15 d
On 2020-12-11 at 12:49:35 +0530, Ramalingam C wrote:
> On 2020-12-10 at 11:56:39 +0530, Anshuman Gupta wrote:
> > Add support for HDCP 2.2 DP MST shim callback.
> > This adds existing DP HDCP shim callback for Link Authentication
> > and Encryption and HDCP 2.2 stream encryption
> > callback.
> >
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev8)
URL : https://patchwork.freedesktop.org/series/84620/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
69d2fc1c153b drm/i915/pxp: Introduce Intel PXP component
-:111: WARNING:FILE_PATH_CHANGES:
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev8)
URL : https://patchwork.freedesktop.org/series/84620/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
Error: Cannot open file ./drivers/gpu/drm/i915/gt/intel_lrc.c
WARNING: kernel
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev7)
URL : https://patchwork.freedesktop.org/series/84620/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9474_full -> Patchwork_19121_full
S
On Thu, 10 Dec 2020, Ville Syrjälä wrote:
> On Thu, Dec 10, 2020 at 08:25:49PM +0100, Thomas Gleixner wrote:
>> Nothing uses the result and nothing should ever use it in driver code.
>>
>> Signed-off-by: Thomas Gleixner
>> Cc: Jani Nikula
>> Cc: Joonas Lahtinen
>> Cc: Rodrigo Vivi
>> Cc: Davi
On Thu, 10 Dec 2020, Thomas Gleixner wrote:
> Driver code has no business with the internals of the irq descriptor.
>
> Aside of that the count is per interrupt line and therefore takes
> interrupts from other devices into account which share the interrupt line
> and are not handled by the graphic
On Thu, 10 Dec 2020, Thomas Gleixner wrote:
> First of all drivers have absolutely no business to dig into the internals
> of an irq descriptor. That's core code and subject to change. All of this
> information is readily available to /proc/interrupts in a safe and race
> free way.
>
> Remove the
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev8)
URL : https://patchwork.freedesktop.org/series/84620/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9474 -> Patchwork_19122
Summary
---
On Fri, Dec 11 2020 at 07:17, Jürgen Groß wrote:
> On 11.12.20 00:20, boris.ostrov...@oracle.com wrote:
>>
>> On 12/10/20 2:26 PM, Thomas Gleixner wrote:
>>> All event channel setups bind the interrupt on CPU0 or the target CPU for
>>> percpu interrupts and overwrite the affinity mask with the cor
On 10/12/2020 19:25, Thomas Gleixner wrote:
Driver code has no business with the internals of the irq descriptor.
Aside of that the count is per interrupt line and therefore takes
interrupts from other devices into account which share the interrupt line
and are not handled by the graphics driv
On 11.12.20 00:20, boris.ostrov...@oracle.com wrote:
On 12/10/20 2:26 PM, Thomas Gleixner wrote:
All event channel setups bind the interrupt on CPU0 or the target CPU for
percpu interrupts and overwrite the affinity mask with the corresponding
cpumask. That does not make sense.
The XEN impleme
On Fri, 2020-12-04 at 22:08 +0530, Anshuman Gupta wrote:
> On 2020-11-06 at 15:44:42 +0530, Gwan-gyeong Mun wrote:
> > It is a preliminary work for supporting multiple EDP PSR and
> > DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
> > supportable PSR.
> > And this moves and rena
On Wed, 2020-11-18 at 13:11 +0200, Jani Nikula wrote:
> On Fri, 06 Nov 2020, Gwan-gyeong Mun
> wrote:
> > In order to support the PSR state of each transcoder, it adds
> > i915_psr_status to sub-directory of each transcoder.
> >
> > v2: Change using of Symbolic permissions 'S_IRUGO' to using of
>
On Fri, 2020-12-04 at 21:36 +0530, Anshuman Gupta wrote:
> On 2020-11-18 at 16:42:29 +0530, Jani Nikula wrote:
> > On Fri, 06 Nov 2020, Gwan-gyeong Mun
> > wrote:
> > > In order to support the PSR state of each transcoder, it adds
> > > i915_psr_status to sub-directory of each transcoder.
> > >
>
On 2020-12-11 at 12:49:35 +0530, Ramalingam C wrote:
> On 2020-12-10 at 11:56:39 +0530, Anshuman Gupta wrote:
> > Add support for HDCP 2.2 DP MST shim callback.
> > This adds existing DP HDCP shim callback for Link Authentication
> > and Encryption and HDCP 2.2 stream encryption
> > callback.
> >
By using the double wide cmpxchg64 on 32bit, we can use the same
algorithm on both 32/64b systems.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_active.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_active.c
b/drivers/gpu/drm/i
== Series Details ==
Series: Introduce Intel PXP component - Mesa single session (rev8)
URL : https://patchwork.freedesktop.org/series/84620/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9474_full -> Patchwork_19122_full
S
Quoting Matthew Brost (2020-12-10 17:37:13)
> On Mon, Dec 07, 2020 at 07:38:11PM +, Chris Wilson wrote:
> > Let's only wait for the list iterator when decoupling the virtual
> > breadcrumb, as the signaling of all the requests may take a long time,
> > during which we do not want to keep the ta
== Series Details ==
Series: drm/i915: Use cmpxchg64 for 32b compatilibity
URL : https://patchwork.freedesktop.org/series/84831/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
Error: Cannot open file ./drivers/gpu/drm/i915/gt/intel_lrc.c
WARNING: kernel-doc './scrip
== Series Details ==
Series: drm/i915: Use cmpxchg64 for 32b compatilibity
URL : https://patchwork.freedesktop.org/series/84831/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9474 -> Patchwork_19123
Summary
---
**SUC
On Fri, Dec 11 2020 at 13:10, Jürgen Groß wrote:
> On 11.12.20 00:20, boris.ostrov...@oracle.com wrote:
>>
>> On 12/10/20 2:26 PM, Thomas Gleixner wrote:
>>> All event channel setups bind the interrupt on CPU0 or the target CPU for
>>> percpu interrupts and overwrite the affinity mask with the cor
On Fri, Dec 11 2020 at 10:13, Tvrtko Ursulin wrote:
> On 10/12/2020 19:25, Thomas Gleixner wrote:
>>
>> Aside of that the count is per interrupt line and therefore takes
>> interrupts from other devices into account which share the interrupt line
>> and are not handled by the graphics driver.
>>
On Wed, 09 Dec 2020, Rodrigo Vivi wrote:
> On Wed, Dec 09, 2020 at 04:16:36PM -0500, Sean Paul wrote:
>> From: Sean Paul
>>
>> No need to spam syslog/console when we can ignore/fix the flag.
>
> besides that we are calling from multiple places anyway..
>
>>
>> Signed-off-by: Sean Paul
>
>
> Re
== Series Details ==
Series: drm/i915: Use cmpxchg64 for 32b compatilibity
URL : https://patchwork.freedesktop.org/series/84831/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9474_full -> Patchwork_19123_full
Summary
--
This v8 version has fixed the cosmetics eview comment
from ram. No functional change.
It has been tested manually with below IGT series on TGL and ICL.
https://patchwork.freedesktop.org/series/82987/
[PATCH v8 12/19] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len
has an Ack from Tomas to merg
When crtc state need_modeset is true it is not necessary
it is going to be a real modeset, it can turns to be a
fastset instead of modeset.
This turns content protection property to be DESIRED and hdcp
update_pipe left with property to be in DESIRED state but
actual hdcp->value was ENABLED.
This i
Get DRM connector reference count while scheduling a prop work
to avoid any possible destroy of DRM connector when it is in
DRM_CONNECTOR_REGISTERED state.
Fixes: a6597faa2d59 ("drm/i915: Protect workers against disappearing
connectors")
Cc: Sean Paul
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Handle CP_IRQ in DEVICE_SERVICE_IRQ_VECTOR_ESI0
It requires to call intel_hdcp_handle_cp_irq() in case
of CP_IRQ is triggered by a sink in DP-MST topology.
Cc: "Ville Syrjälä"
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Reviewed-by: Ramalingam C
Tested-by: Karthik B S
Signed-off-by: Anshuman Gu
There can be situation when DP MST connector is created without
mst modeset being done, in those cases connector->encoder will be
NULL. MST connector->encoder initializes after modeset.
Don't enable HDCP in such cases to prevent any crash.
Cc: Ramalingam C
Cc: Juston Li
Tested-by: Karthik B S
S
Gen12 has H/W delta with respect to HDCP{1.x,2.x} display engine
instances lies in Transcoder instead of DDI as in Gen11.
This requires hdcp driver to use mst_master_transcoder for link
authentication and stream transcoder for stream encryption
separately.
This will be used for both HDCP 1.4 and
DP MST stream encryption status requires time of a link frame
in order to change its status, but as there were some HDCP
encryption timeout observed earlier, it is safer to use
ENCRYPT_STATUS_CHANGE_TIMEOUT_MS timeout for stream status too,
it requires to move the macro to a header.
It will be used
Both HDCP_{1.x,2.x} requires to select/deselect Multistream HDCP bit
in TRANS_DDI_FUNC_CTL in order to enable/disable stream HDCP
encryption over DP MST Transport Link.
HDCP 1.4 stream encryption requires to validate the stream encryption
status in HDCP_STATUS_{TRANSCODER,PORT} register driving th
Enable HDCP 1.4 DP MST stream encryption.
Enable stream encryption once encryption is enabled on
the DP transport driving the link for each stream which
has requested encryption.
Disable stream encryption for each stream that no longer
requires encryption before disabling HDCP encryption on
the l
Enable HDCP 1.4 over DP MST for Gen12.
v2:
- Enable HDCP for <= Gen12 platforms. [Ram]
v3:
- Connector detials in debug msg. [Ram]
Cc: Ramalingam C
Reviewed-by: Ramalingam C
Tested-by: Karthik B S
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 +++
1 fi
Pass dig_port as an argument to intel_hdcp_init()
and intel_hdcp2_init().
This will be required for HDCP 2.2 stream encryption.
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Reviewed-by: Ramalingam C
Tested-by: Karthik B S
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_h
hdcp_port_data is specific to a port on which HDCP
encryption is getting enabled, so encapsulate it to
intel_digital_port.
This will be required to enable HDCP 2.2 stream encryption.
v2:
- 's/port_data/hdcp_port_data'. [Ram]
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Reviewed-by: Ramalingam C
T
Fix the size of WIRED_REPEATER_AUTH_STREAM_REQ cmd buffer size.
It is based upon the actual number of MST streams and size
of wired_cmd_repeater_auth_stream_req_in.
Excluding the size of hdcp_cmd_header.
v2:
- hdcp_cmd_header size annotation nitpick. [Tomas]
Cc: Tomas Winkler
Cc: Ramalingam C
A
Let's define Maximum MST content streams up to four
generically which can be supported by modern display
controllers.
Cc: Sean Paul
Cc: Ramalingam C
Acked-by: Maarten Lankhorst
Reviewed-by: Uma Shankar
Reviewed-by: Ramalingam C
Tested-by: Karthik B S
Signed-off-by: Anshuman Gupta
---
inclu
Add support for multiple mst stream in hdcp port data
which will be used by RepeaterAuthStreamManage msg and
HDCP 2.2 security f/w for m' validation.
Security f/w doesn't have any provision to mark the stream_type
for each stream separately, it just take single input of
stream_type while authentic
This requires for HDCP 2.2 MST check link.
As for DP/HDMI shims check_2_2_link retrieves the connector
from dig_port, this is not sufficient or DP MST connector,
there can be multiple DP MST topology connector associated
with same dig_port.
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Reviewed-by:
Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS
and HDCP2_AUTH_STREAM register in i915_reg header.
B.Spec: 21780
B.Spec: 14410
B.Spec: 50573
v2
- Modified naming convention of HDCP2_STREAM_STATUS
for pre-gen12 platforms inline with B.Spec.
Cc: Ramalingam C
Reviewed-by: Uma Shankar
Reviewed-by: Ramal
Add support for HDCP 2.2 DP MST shim callback.
This adds existing DP HDCP shim callback for Link Authentication
and Encryption and HDCP 2.2 stream encryption
callback.
v2:
- Added a WARN_ON() instead of drm_err. [Uma]
- Cosmetic changes. [Uma]
v3:
- 's/port_data/hdcp_port_data' [Ram]
- skip redund
Authenticate and enable port encryption only once for
an active HDCP 2.2 session, once port is authenticated
and encrypted enable encryption for each stream that
requires encryption on this port.
Similarly disable the stream encryption for each encrypted
stream, once all encrypted stream encryptio
Enable HDCP 2.2 MST support till Gen12.
Cc: Ramalingam C
Tested-by: Karthik B S
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
b/drivers/gpu/drm/i915/disp
On Fri, 04 Dec 2020, Anshuman Gupta wrote:
> Reading backlight status from PPS register doesn't require
> AUX power on the platform which has South Display Engine on PCH.
> It invokes a unnecessary power well enable/disable noise.
> optimize it wherever is possible.
Three aspects here:
1. What's
On 11.12.20 11:13, Thomas Gleixner wrote:
On Fri, Dec 11 2020 at 07:17, Jürgen Groß wrote:
On 11.12.20 00:20, boris.ostrov...@oracle.com wrote:
On 12/10/20 2:26 PM, Thomas Gleixner wrote:
All event channel setups bind the interrupt on CPU0 or the target CPU for
percpu interrupts and overwrite
From: Thomas Gleixner
> Sent: 11 December 2020 12:58
..
> > After my failed hasty sketch from last night I had a different one which
> > was kind of heuristics based (re-reading the upper dword and retrying if
> > it changed on 32-bit).
>
> The problem is that there will be two seperate modificati
On 12/10/20 2:26 PM, Thomas Gleixner wrote:
> Signed-off-by: Thomas Gleixner
> Cc: Boris Ostrovsky
> Cc: Juergen Gross
> Cc: Stefano Stabellini
> Cc: xen-de...@lists.xenproject.org
> ---
> drivers/xen/events/events_base.c |6 --
> 1 file changed, 6 deletions(-)
>
> --- a/drivers/xen/
Replace a comma between expression statements by a semicolon.
Signed-off-by: Zheng Yongjun
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
On Thu, Dec 10, 2020 at 08:25:48PM +0100, Thomas Gleixner wrote:
> The irq descriptor is already there, no need to look it up again.
>
> Signed-off-by: Thomas Gleixner
> Cc: Christian Borntraeger
> Cc: Heiko Carstens
> Cc: linux-s...@vger.kernel.org
> ---
> arch/s390/kernel/irq.c |2 +-
>
On 12/10/20 2:26 PM, Thomas Gleixner wrote:
> All event channel setups bind the interrupt on CPU0 or the target CPU for
> percpu interrupts and overwrite the affinity mask with the corresponding
> cpumask. That does not make sense.
>
> The XEN implementation of irqchip::irq_set_affinity() already
RC6 should work before suspend, and continue to increment while idle
after suspend. Should.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/i915/perf_pmu.c | 36 +++-
1 file changed, 31 insertions(+), 5 deletions(-)
diff --git a/tests/i915/perf_pmu.c b/
On Wed, 09 Dec 2020, Lyude Paul wrote:
> Noticed this while moving all of the VESA backlight code in i915 over to
> DRM helpers: it would appear that we calculate the frequency value we want
> to write to DP_EDP_BACKLIGHT_FREQ_SET twice even though this value never
> actually changes during runtim
On Wed, 09 Dec 2020, Lyude Paul wrote:
> Since we're about to implement eDP backlight support in nouveau using the
> standard protocol from VESA, we might as well just take the code that's
> already written for this and move it into a set of shared DRM helpers.
>
> Note that these helpers are inte
RC6 should work before suspend, and continue to increment while idle
after suspend. Should.
v2: Include a longer sleep after suspend; it appears we are reticent to
idle so soon after waking up.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
tests/i915/perf_pmu.c | 42 ++
== Series Details ==
Series: HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev7)
URL : https://patchwork.freedesktop.org/series/82998/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu
== Series Details ==
Series: HDCP 2.2 and HDCP 1.4 Gen12 DP MST support (rev7)
URL : https://patchwork.freedesktop.org/series/82998/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
Error: Cannot open file ./drivers/gpu/drm/i915/gt/intel_lrc.c
WARNING: kernel-doc './s
== Series Details ==
Series: gpu: drm: i915: convert comma to semicolon
URL : https://patchwork.freedesktop.org/series/84845/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
Error: Cannot open file ./drivers/gpu/drm/i915/gt/intel_lrc.c
WARNING: kernel-doc './scripts/
Also try to clarify a bit when dma_buf_begin/end_cpu_access should
be called.
Signed-off-by: Daniel Vetter
Cc: Thomas Zimmermann
Cc: Sumit Semwal
Cc: "Christian König"
Cc: linux-me...@vger.kernel.org
Cc: linaro-mm-...@lists.linaro.org
---
drivers/dma-buf/dma-buf.c | 20 ++--
i
Noticed while reviewing the output. Adds a bunch more links and fixes
the function interface quoting.
Signed-off-by: Daniel Vetter
Cc: Thomas Zimmermann
Cc: Sumit Semwal
Cc: "Christian König"
Cc: linux-me...@vger.kernel.org
Cc: linaro-mm-...@lists.linaro.org
---
drivers/dma-buf/dma-buf.c | 31
At least amdgpu and i915 do, so lets just document this as the rule.
Signed-off-by: Daniel Vetter
Cc: Thomas Zimmermann
Cc: Sumit Semwal
Cc: "Christian König"
Cc: linux-me...@vger.kernel.org
Cc: linaro-mm-...@lists.linaro.org
---
drivers/dma-buf/dma-buf.c | 4
1 file changed, 4 insertion
Motivated by a discussion with Christian and Thomas: Try to untangle a
bit what's relevant for importers and what's relevant for exporters.
Also add an assert that really only dynamic importers use the api
function, anything else doesn't make sense.
Signed-off-by: Daniel Vetter
Cc: Thomas Zimmer
On 11.12.20 00:20, boris.ostrov...@oracle.com wrote:
On 12/10/20 2:26 PM, Thomas Gleixner wrote:
All event channel setups bind the interrupt on CPU0 or the target CPU for
percpu interrupts and overwrite the affinity mask with the corresponding
cpumask. That does not make sense.
The XEN impleme
== Series Details ==
Series: gpu: drm: i915: convert comma to semicolon
URL : https://patchwork.freedesktop.org/series/84845/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9476 -> Patchwork_19125
Summary
---
**SUCCES
== Series Details ==
Series: series starting with [1/4] dma-buf: Remove kmap kerneldoc vestiges
URL : https://patchwork.freedesktop.org/series/84849/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/ge
On Fri, Oct 23, 2020 at 04:56:20PM +0200, Daniel Vetter wrote:
> On Fri, Oct 23, 2020 at 4:54 PM Christian König
> wrote:
> >
> > Am 23.10.20 um 14:21 schrieb Daniel Vetter:
> > > ttm_resource_manager->use_type is only used for runtime changes by
> > > vmwgfx. I think ideally we'd push this functi
Hi Dave,
I love your patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20201211]
[cannot apply to v5.10-rc7]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch
It is a preliminary work for supporting multiple EDP PSR and
DP PanelReplay. And it refactors singleton PSR to Multi Transcoder
supportable PSR.
And this moves and renames the i915_psr structure of drm_i915_private's to
intel_dp's intel_psr structure.
It also causes changes in PSR interrupt handlin
In order to support the PSR state of each transcoder, it adds
i915_psr_status to sub-directory of each transcoder.
v2: Change using of Symbolic permissions 'S_IRUGO' to using of octal
permissions '0444'
v5: Addressed JJani Nikula's review comments
- Remove checking of Gen12 for i915_psr_statu
== Series Details ==
Series: series starting with [v5,1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/84853/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c3088251ff36 drm/i915/display: Support PSR Multiple Transcoders
-:1
== Series Details ==
Series: series starting with [v5,1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/84853/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be chec
== Series Details ==
Series: series starting with [v5,1/2] drm/i915/display: Support PSR Multiple
Transcoders
URL : https://patchwork.freedesktop.org/series/84853/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
Error: Cannot open file ./drivers/gpu/drm/i915/gt/inte
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