[Intel-gfx] [PATCH 12/61] drm/i915: Reject more ioctls for userptr

2020-10-02 Thread Maarten Lankhorst
Allow set_domain to fail silently, waiting for idle should be good enough. set_tiling and set_caching are rejected with -ENXIO, there's no valid reason to allow it. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_domain.

[Intel-gfx] [PATCH 35/61] drm/i915: Lock ww in ucode objects correctly

2020-10-02 Thread Maarten Lankhorst
In the ucode functions, the calls are done before userspace runs, when debugging using debugfs, or when creating semi-permanent mappings; we can safely use the unlocked versions that does the ww dance for us. Because there is no pin_pages_unlocked yet, add it as convenience function. This removes

[Intel-gfx] [PATCH 45/61] drm/i915/selftests: Prepare execbuf tests for obj->mm.lock removal.

2020-10-02 Thread Maarten Lankhorst
Also quite simple, a single call needs to use the unlocked version. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_execbuffer.c b/driver

[Intel-gfx] [PATCH 55/61] drm/i915/selftests: Prepare timeline tests for obj->mm.lock removal

2020-10-02 Thread Maarten Lankhorst
We can no longer call intel_timeline_pin with a null argument, so add a ww loop that locks the backing object. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gt/selftest_timeline.c | 26 ++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/d

[Intel-gfx] [PATCH 26/61] drm/i915: Make __engine_unpark() compatible with ww locking.

2020-10-02 Thread Maarten Lankhorst
Take the ww lock around engine_unpark. Because of the many many places where rpm is used, I chose the safest option and used a trylock to opportunistically take this lock for __engine_unpark. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gt/intel_engine_pm.c | 4 +++- 1 file changed,

[Intel-gfx] [PATCH 22/61] drm/i915: Add object locking to vm_fault_cpu

2020-10-02 Thread Maarten Lankhorst
Take a simple lock so we hold ww around (un)pin_pages as needed. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gem/i915_gem_mman.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c b/drivers/gpu/drm/i915/gem/i915_gem_mman.c index 5aa037

[Intel-gfx] [PATCH 13/61] drm/i915: Reject UNSYNCHRONIZED for userptr

2020-10-02 Thread Maarten Lankhorst
We should not allow this any more, as it will break with the new userptr implementation, it could still be made to work, but there's no point in doing so. Signed-off-by: Maarten Lankhorst --- .../gpu/drm/i915/gem/i915_gem_execbuffer.c| 2 + drivers/gpu/drm/i915/gem/i915_gem_object.h| 4

[Intel-gfx] [PATCH 00/61] drm/i915: Remove obj->mm.lock!

2020-10-02 Thread Maarten Lankhorst
Finally there, just needs a lot of fixes! A lot of places were calling certain calls without any object lock held, with the removal of mm.lock we can no longer do this, and have to fix it. Phys page handling has to be redone, as nothing protects obj->ops structure, we have to remove swapping it,

[Intel-gfx] [PATCH 57/61] drm/i915/selftests: Prepare memory region tests for obj->mm.lock removal

2020-10-02 Thread Maarten Lankhorst
Use the unlocked variants for pin_map and pin_pages, and add lock around unpinning/putting pages. Signed-off-by: Maarten Lankhorst --- .../drm/i915/selftests/intel_memory_region.c | 18 +++--- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/selft

[Intel-gfx] [PATCH 29/61] drm/i915: Fix pread/pwrite to work with new locking rules.

2020-10-02 Thread Maarten Lankhorst
We are removing obj->mm.lock, and need to take the reservation lock before we can pin pages. Move the pinning pages into the helper, and merge gtt pwrite/pread preparation and cleanup paths. The fence lock is also removed; it will conflict with fence annotations, because of memory allocations done

[Intel-gfx] [PATCH 32/61] drm/i915: Add igt_spinner_pin() to allow for ww locking around spinner.

2020-10-02 Thread Maarten Lankhorst
By default, we assume that it's called inside igt_create_request to keep existing selftests working, but allow for manual pinning when passing a ww context. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/selftests/igt_spinner.c | 136 --- drivers/gpu/drm/i915/selftests

[Intel-gfx] [PATCH 17/61] drm/i915: Populate logical context during first pin.

2020-10-02 Thread Maarten Lankhorst
This allows us to remove pin_map from state allocation, which saves us a few retry loops. We won't need this until first pin, anyway. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gt/intel_context_types.h | 13 ++- drivers/gpu/drm/i915/gt/intel_lrc.c | 107 +---

[Intel-gfx] [PATCH 56/61] drm/i915/selftests: Prepare i915_request tests for obj->mm.lock removal

2020-10-02 Thread Maarten Lankhorst
Straightforward conversion by using unlocked versions. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/selftests/i915_request.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests/i915_request.c b/drivers/gpu/drm/i915/selftests

[Intel-gfx] [PATCH 42/61] drm/i915/selftests: Prepare coherency tests for obj->mm.lock removal.

2020-10-02 Thread Maarten Lankhorst
Straightforward conversion, just convert a bunch of calls to unlocked versions. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gem/selftests/i915_gem_coherency.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_coheren

[Intel-gfx] [PATCH 48/61] drm/i915/selftests: Prepare object blit tests for obj->mm.lock removal.

2020-10-02 Thread Maarten Lankhorst
Use some unlocked versions where we're not holding the ww lock. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object_blt.c b/driv

[Intel-gfx] [PATCH 50/61] drm/i915/selftests: Prepare context selftest for obj->mm.lock removal

2020-10-02 Thread Maarten Lankhorst
Only needs to convert a single call to the unlocked version. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gt/selftest_context.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_context.c b/drivers/gpu/drm/i915/gt/selftest_cont

[Intel-gfx] [PATCH 43/61] drm/i915/selftests: Prepare context tests for obj->mm.lock removal.

2020-10-02 Thread Maarten Lankhorst
Straightforward conversion, just convert a bunch of calls to unlocked versions. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_co

[Intel-gfx] [PATCH 39/61] drm/i915: Use a single page table lock for each gtt.

2020-10-02 Thread Maarten Lankhorst
We may create page table objects on the fly, but we may need to wait with the ww lock held. Instead of waiting on a freed obj lock, ensure we have the same lock for each object to keep -EDEADLK working. This ensures that i915_vma_pin_ww can lock the page tables when required. Signed-off-by: Maarte

[Intel-gfx] [PATCH 53/61] drm/i915/selftests: Prepare mocs tests for obj->mm.lock removal

2020-10-02 Thread Maarten Lankhorst
Use pin_map_unlocked when we're not holding locks. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c index b25eba50c88

[Intel-gfx] [PATCH 41/61] drm/i915/selftests: Prepare client blit for obj->mm.lock removal.

2020-10-02 Thread Maarten Lankhorst
Straightforward conversion, just convert a bunch of calls to unlocked versions. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_cl

[Intel-gfx] [PATCH 60/61] drm/i915: Finally remove obj->mm.lock.

2020-10-02 Thread Maarten Lankhorst
With all callers and selftests fixed to use ww locking, we can now finally remove this lock. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gem/i915_gem_object.c| 2 - drivers/gpu/drm/i915/gem/i915_gem_object.h| 5 +-- .../gpu/drm/i915/gem/i915_gem_object_types.h | 1 - dr

[Intel-gfx] [PATCH 59/61] drm/i915/selftests: Prepare gtt tests for obj->mm.lock removal

2020-10-02 Thread Maarten Lankhorst
We need to lock the global gtt dma_resv, use i915_vm_lock_objects to handle this correctly. Add ww handling for this where required. Add the object lock around unpin/put pages, and use the unlocked versions of pin_pages and pin_map where required. Signed-off-by: Maarten Lankhorst --- drivers/gp

[Intel-gfx] [PATCH 38/61] drm/i915: Fix ww locking in shmem_create_from_object

2020-10-02 Thread Maarten Lankhorst
Quick fix, just use the unlocked version. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gt/shmem_utils.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/shmem_utils.c b/drivers/gpu/drm/i915/gt/shmem_utils.c index 43c7acbdc79d..8c8dfa41e032

[Intel-gfx] [PATCH 49/61] drm/i915/selftests: Prepare igt_gem_utils for obj->mm.lock removal

2020-10-02 Thread Maarten Lankhorst
igt_emit_store_dw needs to use the unlocked version, as it's not holding a lock. This fixes igt_gpu_fill_dw() which is used by some other selftests. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

[Intel-gfx] [PATCH 54/61] drm/i915/selftests: Prepare ring submission for obj->mm.lock removal

2020-10-02 Thread Maarten Lankhorst
Use unlocked versions when the ww lock is not held. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gt/selftest_ring_submission.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_ring_submission.c b/drivers/gpu/drm/i915/gt/selfte

[Intel-gfx] [PATCH 51/61] drm/i915/selftests: Prepare hangcheck for obj->mm.lock removal

2020-10-02 Thread Maarten Lankhorst
Convert a few calls to use the unlocked versions. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gt/selftest_hangcheck.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/selftest_hangcheck.c b/drivers/gpu/drm/i915/gt/selftest_hangche

[Intel-gfx] [PATCH 47/61] drm/i915/selftests: Prepare object tests for obj->mm.lock removal.

2020-10-02 Thread Maarten Lankhorst
Convert a single pin_pages call to use the unlocked version. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_object.c b/drivers/gpu/drm/i915/

[Intel-gfx] [PATCH 19/61] drm/i915: Handle ww locking in init_status_page

2020-10-02 Thread Maarten Lankhorst
Try to pin to ggtt first, and use a full ww loop to handle eviction correctly. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/gt/intel_engine_cs.c | 37 +++ 1 file changed, 24 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Remove obj->mm.lock!

2020-10-02 Thread Patchwork
== Series Details == Series: drm/i915: Remove obj->mm.lock! URL : https://patchwork.freedesktop.org/series/82337/ State : success == Summary == CI Bug Log - changes from CI_DRM_9092 -> Patchwork_18613 Summary --- **SUCCESS** No re

[Intel-gfx] [PATCH] drm/i915/gt: Track the most recent pulse for the heartbeat

2020-10-02 Thread Chris Wilson
Since we track the idle_pulse for flushing the barriers and avoid re-emitting the pulse upon idling if no futher action is required, this also impacts the heartbeat. Before emitting a fresh heartbeat, we look at the engine idle status and assume that if the pulse was the last request emitted along

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Track the most recent pulse for the heartbeat

2020-10-02 Thread Patchwork
== Series Details == Series: drm/i915/gt: Track the most recent pulse for the heartbeat URL : https://patchwork.freedesktop.org/series/82339/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9092 -> Patchwork_18614 Summary ---

[Intel-gfx] [PATCH v2] drm/i915/gt: Track the most recent pulse for the heartbeat

2020-10-02 Thread Chris Wilson
Since we track the idle_pulse for flushing the barriers and avoid re-emitting the pulse upon idling if no futher action is required, this also impacts the heartbeat. Before emitting a fresh heartbeat, we look at the engine idle status and assume that if the pulse was the last request emitted along

Re: [Intel-gfx] [PATCH rdma-next v4 1/4] lib/scatterlist: Add support in dynamic allocation of SG table from pages

2020-10-02 Thread Jason Gunthorpe
On Sun, Sep 27, 2020 at 09:46:44AM +0300, Leon Romanovsky wrote: > +struct scatterlist *__sg_alloc_table_from_pages(struct sg_table *sgt, > + struct page **pages, unsigned int n_pages, unsigned int offset, > + unsigned long size, unsigned int max_segment, > + str

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Track the most recent pulse for the heartbeat (rev2)

2020-10-02 Thread Patchwork
== Series Details == Series: drm/i915/gt: Track the most recent pulse for the heartbeat (rev2) URL : https://patchwork.freedesktop.org/series/82339/ State : success == Summary == CI Bug Log - changes from CI_DRM_9092 -> Patchwork_18615 Summ

Re: [Intel-gfx] [PATCH rdma-next v4 1/4] lib/scatterlist: Add support in dynamic allocation of SG table from pages

2020-10-02 Thread Maor Gottlieb
On 10/2/2020 6:02 PM, Jason Gunthorpe wrote: On Sun, Sep 27, 2020 at 09:46:44AM +0300, Leon Romanovsky wrote: +struct scatterlist *__sg_alloc_table_from_pages(struct sg_table *sgt, + struct page **pages, unsigned int n_pages, unsigned int offset, + unsigned long siz

Re: [Intel-gfx] [PATCH rdma-next v4 1/4] lib/scatterlist: Add support in dynamic allocation of SG table from pages

2020-10-02 Thread Jason Gunthorpe
On Fri, Oct 02, 2020 at 07:11:33PM +0300, Maor Gottlieb wrote: > > On 10/2/2020 6:02 PM, Jason Gunthorpe wrote: > > On Sun, Sep 27, 2020 at 09:46:44AM +0300, Leon Romanovsky wrote: > > > +struct scatterlist *__sg_alloc_table_from_pages(struct sg_table *sgt, > > > + struct page **pages, uns

[Intel-gfx] [PATCH][next] drm/i915: fix size_t greater or equal to zero comparison

2020-10-02 Thread Colin King
From: Colin Ian King Currently the check that the unsigned size_t variable i is >= 0 is always true because the unsigned variable will never be negative, causing the loop to run forever. Fix this by changing the pre-decrement check to a zero check on i followed by a decrement of i. Addresses-Co

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: fix size_t greater or equal to zero comparison

2020-10-02 Thread Patchwork
== Series Details == Series: drm/i915: fix size_t greater or equal to zero comparison URL : https://patchwork.freedesktop.org/series/82342/ State : failure == Summary == Applying: drm/i915: fix size_t greater or equal to zero comparison Using index info to reconstruct a base tree... M dr

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Remove obj->mm.lock!

2020-10-02 Thread Patchwork
== Series Details == Series: drm/i915: Remove obj->mm.lock! URL : https://patchwork.freedesktop.org/series/82337/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9092_full -> Patchwork_18613_full Summary --- **FAILURE*

[Intel-gfx] [PULL] drm-intel-next-fixes

2020-10-02 Thread Rodrigo Vivi
Hi Dave and Daniel, Here goes our first next-fixes. Please be aware this includes both drm-intel-next and drm-intel-gt-next. Also, most of patches from drm-intel-gt-next were accumulated for not being part of current drm-intel-fixes flow while we are defining the new split and flow. So, there ar

Re: [Intel-gfx] [PATCH 00/61] drm/i915: Remove obj->mm.lock!

2020-10-02 Thread Chris Wilson
Quoting Maarten Lankhorst (2020-10-02 13:58:38) > Finally there, just needs a lot of fixes! You are joking, right? -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt: Track the most recent pulse for the heartbeat (rev2)

2020-10-02 Thread Patchwork
== Series Details == Series: drm/i915/gt: Track the most recent pulse for the heartbeat (rev2) URL : https://patchwork.freedesktop.org/series/82339/ State : success == Summary == CI Bug Log - changes from CI_DRM_9092_full -> Patchwork_18615_full

Re: [Intel-gfx] [PATCH 10/61] drm/i915: Disable userptr pread/pwrite support.

2020-10-02 Thread Ruhl, Michael J
>-Original Message- >From: Intel-gfx On Behalf Of >Maarten Lankhorst >Sent: Friday, October 2, 2020 8:59 AM >To: intel-gfx@lists.freedesktop.org >Subject: [Intel-gfx] [PATCH 10/61] drm/i915: Disable userptr pread/pwrite >support. > >Userptr should not need the kernel for a userspace memcpy

[Intel-gfx] [PATCH] drm/i915/tgl/psr: Fix glitches when doing frontbuffer modifications

2020-10-02 Thread José Roberto de Souza
Writes to CURSURFLIVE in TGL are causing IOMMU errors and visual glitches that are often reproduced when executing CPU intensive workloads while a eDP 4K panel is attached. Manually exiting PSR causes the frontbuffer to be updated without glitches and the IOMMU errors are also gone but this comes

[Intel-gfx] [PATCH 0/6] Allow privileged user to map the OA buffer

2020-10-02 Thread Umesh Nerlige Ramappa
Allow user to map the OA buffer and also trigger reports into it. CI fixes: v1: Fixes a memory corruption due to addition of OA whitelist on demand. v2: Spinlock when applying whitelist v3: Use uncore->lock. Do not check for wal->count when applying whitelist. v4: Refresh and rerun with newly adde

[Intel-gfx] [PATCH 1/6] drm/i915/perf: Ensure observation logic is not clock gated

2020-10-02 Thread Umesh Nerlige Ramappa
From: Piotr Maciejewski A clock gating switch can control if the performance monitoring and observation logic is enaled or not. Ensure that we enable the clocks. v2: Separate code from other patches (Lionel) v3: Reset PMON enable when disabling perf to save power (Lionel) v4: Use intel_uncore_rm

[Intel-gfx] [PATCH 6/6] drm/i915/perf: Map OA buffer to user space for gen12 performance query

2020-10-02 Thread Umesh Nerlige Ramappa
i915 used to support time based sampling mode which is good for overall system monitoring, but is not enough for query mode used to measure a single draw call or dispatch. Gen9-Gen11 are using current i915 perf implementation for query, but Gen12+ requires a new approach for query based on triggere

[Intel-gfx] [PATCH 2/6] drm/i915/gt: Lock intel_engine_apply_whitelist with uncore->lock

2020-10-02 Thread Umesh Nerlige Ramappa
Refactor intel_engine_apply_whitelist into locked and unlocked versions so that a caller who already has the lock can apply whitelist. Signed-off-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 44 +++-- 1 file changed, 31 insertions(+), 13 deletions(-

[Intel-gfx] [PATCH 5/6] drm/i915/perf: Whitelist OA counter and buffer registers

2020-10-02 Thread Umesh Nerlige Ramappa
It is useful to have markers in the OA reports to identify triggered reports. Whitelist some OA counters that can be used as markers. A triggered report can be found faster if we can sample the HW tail and head registers when the report was triggered. Whitelist OA buffer specific registers. v2: -

[Intel-gfx] [PATCH 3/6] drm/i915/perf: Whitelist OA report trigger registers

2020-10-02 Thread Umesh Nerlige Ramappa
OA reports can be triggered into the OA buffer by writing into the OAREPORTTRIG registers. Whitelist the registers to allow non-privileged user to trigger reports. Whitelist registers only if perf_stream_paranoid is set to 0. In i915_perf_open_ioctl, this setting is checked and the whitelist is en

[Intel-gfx] [PATCH 4/6] drm/i915/gt: Refactor _wa_add to reuse wa_index and wa_list_grow

2020-10-02 Thread Umesh Nerlige Ramappa
Switch the search and grow code of the _wa_add to use _wa_index and _wa_list_grow. Signed-off-by: Umesh Nerlige Ramappa --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 54 +++-- 1 file changed, 17 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_workar

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl/psr: Fix glitches when doing frontbuffer modifications

2020-10-02 Thread Patchwork
== Series Details == Series: drm/i915/tgl/psr: Fix glitches when doing frontbuffer modifications URL : https://patchwork.freedesktop.org/series/82351/ State : success == Summary == CI Bug Log - changes from CI_DRM_9093 -> Patchwork_18617 Su

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Allow privileged user to map the OA buffer

2020-10-02 Thread Patchwork
== Series Details == Series: Allow privileged user to map the OA buffer URL : https://patchwork.freedesktop.org/series/82353/ State : warning == Summary == $ dim checkpatch origin/drm-tip febfa8b6a73d drm/i915/perf: Ensure observation logic is not clock gated ed4d60599ff2 drm/i915/gt: Lock int

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Allow privileged user to map the OA buffer

2020-10-02 Thread Patchwork
== Series Details == Series: Allow privileged user to map the OA buffer URL : https://patchwork.freedesktop.org/series/82353/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. +drivers/gpu/drm/i915/g

[Intel-gfx] [PATCH 1/5] drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programming

2020-10-02 Thread Imre Deak
The BIOS of at least one ASUS-Z170M system with an SKL I have programs the 101b WRPLL PDIV divider value, which is the encoding for PDIV=7 with bit#0 incorrectly set. This happens with the "3840x2160": 30 262750 3840 3888 3920 4000 2160 2163 2168 2191 0x48 0x9 HDMI mode (scaled from a 1024x768 s

[Intel-gfx] [PATCH 3/5] drm/i915: Check for unsupported DP link rates during initial commit

2020-10-02 Thread Imre Deak
Some BIOSes set an unsupported/imprecise DP link rate (for instance on TGL A stepping). Make sure that we do an encoder recompute and a modeset in this case. Cc: Ville Syrjälä Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/intel_dp.c | 12 1 file changed, 12 insertions(+

[Intel-gfx] [PATCH 0/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock

2020-10-02 Thread Imre Deak
This patchset replaces [1]. That version's solution to work around broken TGL A BIOSes turned out to be papering over something. The real root cause was the lack of a full encoder recompute/modeset during the initial commit and leaking the incorrect link rate into the PLL frequency calculation code

[Intel-gfx] [PATCH 4/5] drm/i915: Add an encoder hook to sanitize its state during init/resume

2020-10-02 Thread Imre Deak
Atm, if a full modeset is performed during the initial modeset the link training will happen with uninitialized max DP rate and lane count. Make sure the corresponding encoder state is initialized by adding an encoder hook called during driver init and system resume. A better alternative would be

[Intel-gfx] [PATCH 2/5] drm/i915: Move the initial fastset commit check to encoder hooks

2020-10-02 Thread Imre Deak
Move the checks to decide whether a fastset is possible during the initial commit to an encoder hook. This check is really encoder specific and the next patch will also require this adding a DP encoder specific check. Cc: Ville Syrjälä Signed-off-by: Imre Deak --- drivers/gpu/drm/i915/display/i

[Intel-gfx] [PATCH 5/5] drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock

2020-10-02 Thread Imre Deak
Apply Display WA #22010492432 for combo PHY PLLs too. This should fix a problem where the PLL output frequency is slightly off with the current PLL fractional divider value. I haven't seen an actual case where this causes a problem, but let's follow the spec. It's also needed on some EHL platforms

[Intel-gfx] ✓ Fi.CI.BAT: success for Allow privileged user to map the OA buffer

2020-10-02 Thread Patchwork
== Series Details == Series: Allow privileged user to map the OA buffer URL : https://patchwork.freedesktop.org/series/82353/ State : success == Summary == CI Bug Log - changes from CI_DRM_9093 -> Patchwork_18618 Summary --- **SUCCES

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev2)

2020-10-02 Thread Patchwork
== Series Details == Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev2) URL : https://patchwork.freedesktop.org/series/82173/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be chec

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev2)

2020-10-02 Thread Patchwork
== Series Details == Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev2) URL : https://patchwork.freedesktop.org/series/82173/ State : success == Summary == CI Bug Log - changes from CI_DRM_9093 -> Patchwork_18619 ==

[Intel-gfx] [PATCH v2 2/5] drm/i915: Move the initial fastset commit check to encoder hooks

2020-10-02 Thread Imre Deak
Move the checks to decide whether a fastset is possible during the initial commit to an encoder hook. This check is really encoder specific and the next patch will also require this adding a DP encoder specific check. v2: Fix negated condition in gen11_dsi_initial_fastset_check(). Cc: Ville Syrjä

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl/psr: Fix glitches when doing frontbuffer modifications

2020-10-02 Thread Patchwork
== Series Details == Series: drm/i915/tgl/psr: Fix glitches when doing frontbuffer modifications URL : https://patchwork.freedesktop.org/series/82351/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9093_full -> Patchwork_18617_full ==

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3)

2020-10-02 Thread Patchwork
== Series Details == Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3) URL : https://patchwork.freedesktop.org/series/82173/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be chec

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3)

2020-10-02 Thread Patchwork
== Series Details == Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3) URL : https://patchwork.freedesktop.org/series/82173/ State : success == Summary == CI Bug Log - changes from CI_DRM_9093 -> Patchwork_18620 ==

Re: [Intel-gfx] [PATCH 2/6] drm/i915/gt: Lock intel_engine_apply_whitelist with uncore->lock

2020-10-02 Thread kernel test robot
Hi Umesh, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on drm-intel/for-linux-next] [also build test WARNING on drm-tip/drm-tip linus/master v5.9-rc7 next-20201002] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting

[Intel-gfx] ✗ Fi.CI.IGT: failure for Allow privileged user to map the OA buffer

2020-10-02 Thread Patchwork
== Series Details == Series: Allow privileged user to map the OA buffer URL : https://patchwork.freedesktop.org/series/82353/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9093_full -> Patchwork_18618_full Summary ---

[Intel-gfx] [PATCH 2/2] drm/i915: Update gen12 multicast register ranges

2020-10-02 Thread Matt Roper
The updated bspec forcewake table also provides us with new multicast ranges that should be reflected in our workaround code. Note that there are different types of multicast registers with different styles of replication and different steering registers. The i915 MCR range lists we're updating h

[Intel-gfx] [PATCH 1/2] drm/i915: Update gen12 forcewake table

2020-10-02 Thread Matt Roper
The bspec's forcewake page was very stale and out of date for recent platforms. The hardware team finally provided us with an updated gen12 table (which applies to TGL, RKL, and DG1) and there are a lot of changes. Bspec: 66696 Cc: Caz Yokoyama Cc: Daniele Ceraolo Spurio Signed-off-by: Matt Rop

[Intel-gfx] [PATCH 0/2] Gen12 forcewake and multicast updates

2020-10-02 Thread Matt Roper
The hardware architects have finally provided an updated MMIO table for gen12 platforms (TGL, RKL, DG1). We should update our driver's forcewake and MCR programming accordingly. Bspec: 66696 Cc: Caz Yokoyama Cc: Daniele Ceraolo Spurio Matt Roper (2): drm/i915: Update gen12 forcewake table

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Gen12 forcewake and multicast updates

2020-10-02 Thread Patchwork
== Series Details == Series: Gen12 forcewake and multicast updates URL : https://patchwork.freedesktop.org/series/82359/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./include/linux/spinlock.

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3)

2020-10-02 Thread Patchwork
== Series Details == Series: drm/i915/tgl: Fix Combo PHY DPLL fractional divider for 38.4MHz ref clock (rev3) URL : https://patchwork.freedesktop.org/series/82173/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9093_full -> Patchwork_18620_full

[Intel-gfx] ✓ Fi.CI.BAT: success for Gen12 forcewake and multicast updates

2020-10-02 Thread Patchwork
== Series Details == Series: Gen12 forcewake and multicast updates URL : https://patchwork.freedesktop.org/series/82359/ State : success == Summary == CI Bug Log - changes from CI_DRM_9093 -> Patchwork_18621 Summary --- **SUCCESS**

Re: [Intel-gfx] [PATCH v2] drm/i915/display/ehl: Limit eDP to HBR2

2020-10-02 Thread Matt Roper
On Mon, Sep 28, 2020 at 01:03:09PM -0700, José Roberto de Souza wrote: > Recent update in documentation defeatured eDP HBR3 for EHL and JSL. > > v2: > - Remove dead code in ehl_get_combo_buf_trans() > > BSpec: 32247 > Cc: Matt Roper > Cc: Vidya Srinivas > Signed-off-by: José Roberto de Souza

[Intel-gfx] ✗ Fi.CI.IGT: failure for Gen12 forcewake and multicast updates

2020-10-02 Thread Patchwork
== Series Details == Series: Gen12 forcewake and multicast updates URL : https://patchwork.freedesktop.org/series/82359/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9093_full -> Patchwork_18621_full Summary --- **F

[Intel-gfx] [drm-intel:drm-intel-next-queued 14/14] drivers/gpu/drm/i915/display/intel_lspcon.c:533:6: error: no previous prototype for function 'lspcon_init'

2020-10-02 Thread kernel test robot
tree: git://anongit.freedesktop.org/drm-intel drm-intel-next-queued head: f542d671ffcec772a561cd41c7e2394392d9dafb commit: f542d671ffcec772a561cd41c7e2394392d9dafb [14/14] drm/i915: Init lspcon after HPD in intel_dp_detect() config: x86_64-randconfig-a005-20201001 (attached as .config) compile

Re: [Intel-gfx] [PATCH] Memory leak fix

2020-10-02 Thread Chris Wilson
Quoting Steve Hampson (2020-10-02 05:52:15) > Static analysis detected a memory leak if the second kmalloc fails > and the first allocation is not freed. > > Signed-off-by: Steve Hampson > --- > drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-

[Intel-gfx] [PATCH] drm/i915/gt: Undo forced context restores after trivial preemptions

2020-10-02 Thread Chris Wilson
We may try to preempt the currently executing request, only to find that after unravelling all the dependencies that the original executing context is still the earliest in the topological sort and re-submitted back to HW (if we do detect some change in the ELSP that requires re-submission). Howeve

[Intel-gfx] [PATCH] drm/i915: Make lspcon_init() static

2020-10-02 Thread Ville Syrjala
From: Ville Syrjälä Make lspcon_init() static since it's no longer needed outside the compilation unit. This was correct in Kai-Heng's lspcon patch, but I fumbled this when applying it. Cc: Kai-Heng Feng Reported-by: kernel test robot Fixes: f542d671ffce ("drm/i915: Init lspcon after HPD in in

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt: Undo forced context restores after trivial preemptions

2020-10-02 Thread Patchwork
== Series Details == Series: drm/i915/gt: Undo forced context restores after trivial preemptions URL : https://patchwork.freedesktop.org/series/82325/ State : success == Summary == CI Bug Log - changes from CI_DRM_9091 -> Patchwork_18610 Su

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Make lspcon_init() static

2020-10-02 Thread Patchwork
== Series Details == Series: drm/i915: Make lspcon_init() static URL : https://patchwork.freedesktop.org/series/82328/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. -O:drivers/gpu/drm/i915/displa

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Make lspcon_init() static

2020-10-02 Thread Patchwork
== Series Details == Series: drm/i915: Make lspcon_init() static URL : https://patchwork.freedesktop.org/series/82328/ State : success == Summary == CI Bug Log - changes from CI_DRM_9091 -> Patchwork_18611 Summary --- **SUCCESS**

Re: [Intel-gfx] [PATCH v3 1/2] drm/i915/jsl: Split EHL/JSL platform info and PCI ids

2020-10-02 Thread Ville Syrjälä
On Fri, Oct 02, 2020 at 02:54:34AM +0530, Tejas Upadhyay wrote: > Split the basic platform definition, macros, and PCI IDs to > differentiate between EHL and JSL platforms. > > Changes since V2 : > - Added IS_EHL_JSL to replace IS_ELKHARTLAKE > - EHL/JSL PCI ids split added > Changes s

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/gt: Undo forced context restores after trivial preemptions

2020-10-02 Thread Patchwork
== Series Details == Series: drm/i915/gt: Undo forced context restores after trivial preemptions URL : https://patchwork.freedesktop.org/series/82325/ State : failure == Summary == CI Bug Log - changes from CI_DRM_9091_full -> Patchwork_18610_full ==

Re: [Intel-gfx] linux-next: manual merge of the akpm tree with the drm-intel tree

2020-10-02 Thread Joonas Lahtinen
Quoting Daniel Vetter (2020-10-01 18:13:26) > On Thu, Oct 1, 2020 at 5:08 PM Jani Nikula > wrote: > > > > On Thu, 01 Oct 2020, Daniel Vetter wrote: > > > On Thu, Oct 1, 2020 at 3:53 PM Christoph Hellwig wrote: > > >> > > >> On Thu, Oct 01, 2020 at 08:39:17PM +1000, Stephen Rothwell wrote: > > >

Re: [Intel-gfx] [PATCH v3 2/2] drm/i915/edp/jsl: Update vswing table for HBR and HBR2

2020-10-02 Thread Ville Syrjälä
On Fri, Oct 02, 2020 at 02:54:35AM +0530, Tejas Upadhyay wrote: > JSL has update in vswing table for eDP. > > BSpec: 21257 > > Changes since V2 : > - Added IS_EHL_JSL to replace IS_ELKHARTLAKE > - EHL/JSL PCI ids split added > - Changes rebased as per new drm top commit > > Cha

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Make lspcon_init() static

2020-10-02 Thread Patchwork
== Series Details == Series: drm/i915: Make lspcon_init() static URL : https://patchwork.freedesktop.org/series/82328/ State : success == Summary == CI Bug Log - changes from CI_DRM_9091_full -> Patchwork_18611_full Summary --- **WAR

Re: [Intel-gfx] [PATCH] drm/i915: Make lspcon_init() static

2020-10-02 Thread Chris Wilson
Quoting Ville Syrjala (2020-10-02 10:04:46) > From: Ville Syrjälä > > Make lspcon_init() static since it's no longer needed outside > the compilation unit. This was correct in Kai-Heng's lspcon > patch, but I fumbled this when applying it. > > Cc: Kai-Heng Feng > Reported-by: kernel test robot

Re: [Intel-gfx] [V14 5/5] drm/i915/dsi: Enable software vblank counter

2020-10-02 Thread Ville Syrjälä
On Thu, Sep 24, 2020 at 06:12:09PM +0530, Vandita Kulkarni wrote: > In case of DSI cmd mode, we get hw vblank counter > updated after the TE comes in, if we try to read > the hw vblank counter in te handler we wouldnt have > the udpated vblank counter yet. > This will lead to a state where we would

Re: [Intel-gfx] [PATCH v4 0/7] Convert the intel iommu driver to the dma-iommu api

2020-10-02 Thread Lu Baolu
Hi Joerg, On 2020/10/1 20:17, Joerg Roedel wrote: Hi Baolu, On Tue, Sep 29, 2020 at 08:11:35AM +0800, Lu Baolu wrote: I have no preference. It depends on which patch goes first. Let the maintainers help here. No preference on my side, except that it is too late for this now to make it into v

[Intel-gfx] [PATCH 03/11] mm: add a vmap_pfn function

2020-10-02 Thread Christoph Hellwig
Add a proper helper to remap PFNs into kernel virtual space so that drivers don't have to abuse alloc_vm_area and open coded PTE manipulation for it. Signed-off-by: Christoph Hellwig --- include/linux/vmalloc.h | 1 + mm/Kconfig | 3 +++ mm/vmalloc.c| 45 ++

[Intel-gfx] [PATCH 06/11] drm/i915: use vmap in shmem_pin_map

2020-10-02 Thread Christoph Hellwig
shmem_pin_map somewhat awkwardly reimplements vmap using alloc_vm_area and manual pte setup. The only practical difference is that alloc_vm_area prefeaults the vmalloc area PTEs, which doesn't seem to be required here (and could be added to vmap using a flag if actually required). Switch to use v

[Intel-gfx] [PATCH 01/11] mm: update the documentation for vfree

2020-10-02 Thread Christoph Hellwig
From: "Matthew Wilcox (Oracle)" * Document that you can call vfree() on an address returned from vmap() * Remove the note about the minimum size -- the minimum size of a vmalloc allocation is one page * Add a Context: section * Fix capitalisation * Reword the prohibition on calling from N

[Intel-gfx] [PATCH 04/11] mm: allow a NULL fn callback in apply_to_page_range

2020-10-02 Thread Christoph Hellwig
Besides calling the callback on each page, apply_to_page_range also has the effect of pre-faulting all PTEs for the range. To support callers that only need the pre-faulting, make the callback optional. Based on a patch from Minchan Kim . Signed-off-by: Christoph Hellwig --- mm/memory.c | 16 +

[Intel-gfx] remove alloc_vm_area v4

2020-10-02 Thread Christoph Hellwig
Hi Andrew, this series removes alloc_vm_area, which was left over from the big vmalloc interface rework. It is a rather arkane interface, basicaly the equivalent of get_vm_area + actually faulting in all PTEs in the allocated area. It was originally addeds for Xen (which isn't modular to start w

[Intel-gfx] [PATCH 08/11] drm/i915: use vmap in i915_gem_object_map

2020-10-02 Thread Christoph Hellwig
i915_gem_object_map implements fairly low-level vmap functionality in a driver. Split it into two helpers, one for remapping kernel memory which can use vmap, and one for I/O memory that uses vmap_pfn. The only practical difference is that alloc_vm_area prefeaults the vmalloc area PTEs, which doe

[Intel-gfx] [PATCH 09/11] xen/xenbus: use apply_to_page_range directly in xenbus_map_ring_pv

2020-10-02 Thread Christoph Hellwig
Replacing alloc_vm_area with get_vm_area_caller + apply_page_range allows to fill put the phys_addr values directly instead of doing another loop over all addresses. Signed-off-by: Christoph Hellwig Reviewed-by: Boris Ostrovsky --- drivers/xen/xenbus/xenbus_client.c | 30 ---

[Intel-gfx] [PATCH 10/11] x86/xen: open code alloc_vm_area in arch_gnttab_valloc

2020-10-02 Thread Christoph Hellwig
Replace the last call to alloc_vm_area with an open coded version using an iterator in struct gnttab_vm_area instead of the triple indirection magic in alloc_vm_area. Signed-off-by: Christoph Hellwig Reviewed-by: Boris Ostrovsky --- arch/x86/xen/grant-table.c | 27 --- 1

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