[Intel-gfx] [PATCH v6 12/24] drm/i915/dg1: gmbus pin mapping

Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC. >From spec we have registers GPIO_CTL[1-4], so we should not do the 4->9 mapping as in ICL/TGL. The values for VBT seem wrong in BSpec. For the current boards we actually have a 1:1 mapping. BSpec: 49311, 49945, 20124 Cc: A

[Intel-gfx] [PATCH v6 17/24] drm/i915/dg1: provide port/phy mapping for vbt

From: Matt Roper As with RKL, DG1's VBT outputs are indexed according to PHY rather than DDI. Signed-off-by: Matt Roper Reviewed-by: Lucas De Marchi Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_bios.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) dif

[Intel-gfx] [PATCH v6 21/24] drm/i915/dg1: Add initial DG1 workarounds

From: Stuart Summers DG1 shares some workarounds with TGL and RKL and also has some additional workarounds of its own. v2: Correct location of Wa_1408615072 (JohnH). v3: Apply WAs 1606700617, 18011464164 and 22010931296 to DG1 (José) v4 (Anusha) - Add Wa_22010271021 - s/Wa_14010096844/Wa_140

[Intel-gfx] [PATCH v6 05/24] drm/i915/dg1: Increase mmio size to 4MB

From: Venkata Sandeep Dhanalakota On DGFX the register range has been extended to go up to 8MB. However we only actually use up to address 28h, so let's increase it to 4MB. v2 (Lucas): add bspec reference and reword commit message to explain the 4 vs 8 MB used (requested by Matt Roper)

[Intel-gfx] [PATCH v6 13/24] drm/i915/dg1: Enable first 2 ports for DG1

From: Aditya Swarup Enable PORTS A and B for DG1 initially, the other ports still need more plumbing code in order to be enabled. Cc: Clinton Taylor Cc: Matt Roper Cc: Lucas De Marchi Signed-off-by: Aditya Swarup Reviewed-by: Lucas De Marchi Signed-off-by: Lucas De Marchi --- drivers/gpu/

[Intel-gfx] [PATCH v6 18/24] drm/i915/dg1: map/unmap pll clocks

DG1 uses 2 registers for the ddi clock mapping, with PHY A and B using DPCLKA_CFGCR0 and PHY C and D using DPCLKA1_CFGCR0. Hide this behind a single macro that chooses the correct register according to the phy being accessed, use the correct bitfields for each pll/phy and implement separate functio

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