On Tue, 15 Sep 2020, Lyude Paul wrote:
> This reverts commit 0883ce8146ed6074c76399f4e70dbed788582e12. Originally
> these quirks were added because of the issues with using the eDP
> backlight interfaces on certain laptop panels, which made it impossible
> to properly probe for DPCD backlight supp
On Tue, 15 Sep 2020, Aditya Swarup wrote:
> Gen 10+ and Gen11+ platforms specify different max plane width for
> planar formats. Add max plane width for GLK and ICL based on
> BSpec: 7666
>
> Fixes: 372b9ffb5799 ("drm/i915: Fix skl+ max plane width")
>
Fixes is part of the tags; no blank lines he
On Tue, Sep 15, 2020 at 7:35 PM Linus Torvalds
wrote:
>
> On Tue, Sep 15, 2020 at 1:39 AM Thomas Gleixner wrote:
> >
> > OTOH, having a working 'preemptible()' or maybe better named
> > 'can_schedule()' check makes tons of sense to make decisions about
> > allocation modes or other things.
>
> No
On Mon, Sep 14, 2020 at 05:45:09PM +0100, Tvrtko Ursulin wrote:
>
> On 23/07/2020 18:21, Chris Wilson wrote:
> > Since the debugfs may peek into the GEM contexts as the corresponding
> > client/fd is being closed, we may try and follow a dangling pointer.
> > However, the context closure itself is
On Tue, 15 Sep 2020, Rodrigo Vivi wrote:
> On Tue, Sep 15, 2020 at 01:29:35PM -0400, Lyude Paul wrote:
>> Since we're about to start adding support for Intel's magic HDR
>> backlight interface over DPCD, we need to ensure we're properly
>> programming this field so that Intel specific sink service
On Wed, Sep 02, 2020 at 03:21:41PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> With the dbuf code mostly converted over to the new global state
> handling we can remove the leftovers of the old global state
> stuff.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/displa
On Tue, Jul 14, 2020 at 06:26:26PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Since we now have proper old and new cdclk state we no longer
> need to keep this flag to indicate that the force min cdclk has
> changed. Instead just check if the old vs. new value are different.
>
> Signe
== Series Details ==
Series: Add support for mipi dsi cmd mode (rev11)
URL : https://patchwork.freedesktop.org/series/69290/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_9016_full -> Patchwork_18508_full
Summary
---
Hi Lakshmi,
On Tue, 2020-09-15 at 15:39 +, Vudum, Lakshminarayana wrote:
> Hi Janusz,
>
> I have filed https://gitlab.freedesktop.org/drm/intel/-/issues/2469 for
> igt@core_hotunplug@hotrebind-lateclose failure.
> Is it GUC issue?
Wow, I thought that issue got hidden behind another one and
On 16/09/2020 08:42, Daniel Vetter wrote:
On Mon, Sep 14, 2020 at 05:45:09PM +0100, Tvrtko Ursulin wrote:
On 23/07/2020 18:21, Chris Wilson wrote:
Since the debugfs may peek into the GEM contexts as the corresponding
client/fd is being closed, we may try and follow a dangling pointer.
Howeve
Quoting Greg KH (2020-09-16 07:33:58)
> On Tue, Sep 15, 2020 at 01:41:48PM +0100, Chris Wilson wrote:
> > On Tigerlake, we are seeing a repeat of commit d8f505311717 ("drm/i915/icl:
> > Forcibly evict stale csb entries") where, presumably, due to a missing
> > Global Observation Point synchronisati
On Wed, Sep 16, 2020 at 09:26:58AM +0100, Chris Wilson wrote:
> Quoting Greg KH (2020-09-16 07:33:58)
> > On Tue, Sep 15, 2020 at 01:41:48PM +0100, Chris Wilson wrote:
> > > On Tigerlake, we are seeing a repeat of commit d8f505311717
> > > ("drm/i915/icl:
> > > Forcibly evict stale csb entries") w
Now that we have drm-intel-gt-next merged, we also get the gt fixes.
The following commits failed to cherry-pick:
56f581bad4bf ("drm/i915/gt: Only transfer the virtual context to the new engine
if active")
b3786b29379c ("drm/i915/gt: Distinguish the virtual breadcrumbs from the irq
breadcrumb
As the error capture will compress user buffers as directed to by the
user, it can take an arbitrary amount of time and space. Break up the
compression loops with a call to cond_resched(), that will allow other
processes to schedule (avoiding the soft lockups) and also serve as a
warning should we
Shrink the hold time for the error capture mutex to just around the
acquire/release of the PTE used for reading back the object via the
Global GTT. For platforms that do not need the GGTT read back, we can
skip the mutex entirely and allow concurrent error capture. Where we do
use the GGTT, by rest
When debugging the engine state, include the user properties that may,
or may not, have been adjusted by the user/test.
For example,
vecs0
...
Properties:
heartbeat_interval_ms: 2500 [default 2500]
max_busywait_duration_ns: 8000 [default 8000]
On Mon, Sep 14, 2020 at 01:25:20PM +0200, Thomas Zimmermann wrote:
> This patch updates dma_buf_vmap() and dma-buf's vmap callback to use
> struct dma_buf_map.
>
> The interfaces used to return a buffer address. This address now gets
> stored in an instance of the structure that is given as an add
On Mon, Sep 14, 2020 at 01:25:18PM +0200, Thomas Zimmermann wrote:
> Dma-buf provides vmap() and vunmap() for retrieving and releasing mappings
> of dma-buf memory in kernel address space. The functions operate with plain
> addresses and the assumption is that the memory can be accessed with load
>
We have to be very careful while walking the timeline->requests list
under the RCU guard, as the requests (and so rq->link) use
SLAB_TYPESAFE_BY_RCU and so the requests may be reallocated within an
rcu grace period. As the requests are reallocated, they are removed from
one list and placed on anoth
Currently, we check we can send a pulse prior to disabling the
heartbeat to verify that we can change the heartbeat, but since we may
re-evaluate execution upon changing the heartbeat interval we need another
pulse afterwards to refresh execution.
Fixes: 9a40bddd47ca ("drm/i915/gt: Expose heartbea
We only allow persistent requests to remain on the GPU past the closure
of their containing context (and process) so long as they are continuously
checked for hangs or allow other requests to preempt them, as we need to
ensure forward progress of the system. If we allow persistent contexts
to remai
Verify that if a context is active at the time it is closed, that it is
either persistent and preemptible (with hangcheck running) or it shall
be removed from execution.
Fixes: 9a40bddd47ca ("drm/i915/gt: Expose heartbeat interval via sysfs")
Testcase: igt/gem_ctx_persistence/heartbeat-close
Signe
Flush all the pending requests from the mock engine when they are
cancelled.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/mock_engine.c | 29 +++
1 file changed, 25 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/mock_engine.c
b/drivers/gpu
After marking the requests on an engine as cancelled upon wedging, send
any signals for their completions.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/
If we manage to hit the intel_gt_set_wedged_on_fini() while active, i.e.
module unload during a stress test, we may cancel the requests but not
clean up. This leads to a slow module unload as we wait for something or
other to trigger the retirement flushing. Instead if we explicitly
cancel then cle
On Tue, Sep 15, 2020 at 04:59:41PM +0200, Thomas Zimmermann wrote:
> GEM object functions deprecate several similar callback interfaces in
> struct drm_driver. This patch replaces the per-driver callbacks with
> per-instance callbacks in exynos. The only exception is gem_prime_mmap,
> which is non-
Hi
Am 16.09.20 um 12:03 schrieb Daniel Vetter:
> On Tue, Sep 15, 2020 at 04:59:41PM +0200, Thomas Zimmermann wrote:
>> GEM object functions deprecate several similar callback interfaces in
>> struct drm_driver. This patch replaces the per-driver callbacks with
>> per-instance callbacks in exynos.
Hi
Am 16.09.20 um 11:37 schrieb Daniel Vetter:
> On Mon, Sep 14, 2020 at 01:25:18PM +0200, Thomas Zimmermann wrote:
>> Dma-buf provides vmap() and vunmap() for retrieving and releasing mappings
>> of dma-buf memory in kernel address space. The functions operate with plain
>> addresses and the assu
Since we store a pointer to the fake iommu device that is allocated on
the stack, as soon as we leave the function it goes out of scope and any
future dereference is undefined behaviour. Just in case we may need to
look at the fake iommu device after initialiation, move the allocation
from the stac
Just in case the caller passes in 0 for both slow&fast timeouts, make
sure we initialise the stack value returned. Add an assert so that we
don't make the mistake of passing 0 timeouts for the wait.
drivers/gpu/drm/i915/intel_uncore.c:2011 __intel_wait_for_register_fw() error:
uninitialized symbo
On Tue, Sep 15, 2020 at 04:59:40PM +0200, Thomas Zimmermann wrote:
> GEM object functions deprecate several similar callback interfaces in
> struct drm_driver. This patch replaces the per-driver callbacks with
> per-instance callbacks in etnaviv. The only exception is gem_prime_mmap,
> which is non
On Wed, Sep 16, 2020 at 12:36:28PM +0200, Thomas Zimmermann wrote:
> Hi
>
> Am 16.09.20 um 12:03 schrieb Daniel Vetter:
> > On Tue, Sep 15, 2020 at 04:59:41PM +0200, Thomas Zimmermann wrote:
> >> GEM object functions deprecate several similar callback interfaces in
> >> struct drm_driver. This pat
On Tue, Sep 15, 2020 at 04:59:42PM +0200, Thomas Zimmermann wrote:
> GEM object functions deprecate several similar callback interfaces in
> struct drm_driver. This patch replaces the per-driver callbacks with
> per-instance callbacks in gma500.
>
> Signed-off-by: Thomas Zimmermann
Reviewed-by:
On Tue, Sep 15, 2020 at 04:59:44PM +0200, Thomas Zimmermann wrote:
> GEM object functions deprecate several similar callback interfaces in
> struct drm_driver. This patch replaces the per-driver callbacks with
> per-instance callbacks in mediatek. The only exception is gem_prime_mmap,
> which is no
On Tue, Sep 15, 2020 at 04:59:45PM +0200, Thomas Zimmermann wrote:
> GEM object functions deprecate several similar callback interfaces in
> struct drm_driver. This patch replaces the per-driver callbacks with
> per-instance callbacks in msm. The only exception is gem_prime_mmap,
> which is non-tri
On Tue, Sep 15, 2020 at 04:59:46PM +0200, Thomas Zimmermann wrote:
> GEM object functions deprecate several similar callback interfaces in
> struct drm_driver. This patch replaces the per-driver callbacks with
> per-instance callbacks in nouveau.
>
> Signed-off-by: Thomas Zimmermann
Hm ttm and g
On Tue, Sep 15, 2020 at 04:59:50PM +0200, Thomas Zimmermann wrote:
> GEM object functions deprecate several similar callback interfaces in
> struct drm_driver. This patch replaces the per-driver callbacks with
> per-instance callbacks in rockchip. The only exception is gem_prime_mmap,
> which is no
On Tue, Sep 15, 2020 at 04:59:54PM +0200, Thomas Zimmermann wrote:
> GEM object functions deprecate several similar callback interfaces in
> struct drm_driver. This patch replaces virtgpu's per-driver PRIME export
> function with a per-object function.
>
> Signed-off-by: Thomas Zimmermann
Review
On Tue, Sep 15, 2020 at 04:59:58PM +0200, Thomas Zimmermann wrote:
> Several GEM and PRIME callbacks have been deprecated in favor of
> per-instance GEM object functions. Remove the callbacks as they are
> now unused. The only exception is .gem_prime_mmap, which is still
> in use by several drivers
On Wed, Sep 16, 2020 at 12:48:20PM +0200, Thomas Zimmermann wrote:
> Hi
>
> Am 16.09.20 um 11:37 schrieb Daniel Vetter:
> > On Mon, Sep 14, 2020 at 01:25:18PM +0200, Thomas Zimmermann wrote:
> >> Dma-buf provides vmap() and vunmap() for retrieving and releasing mappings
> >> of dma-buf memory in k
== Series Details ==
Series: series starting with [1/3] drm/i915/gt: Show engine properties in the
pretty printer
URL : https://patchwork.freedesktop.org/series/81727/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
22a8bb51bc47 drm/i915/gt: Show engine properties in the pretty
== Series Details ==
Series: series starting with [1/3] drm/i915/gt: Show engine properties in the
pretty printer
URL : https://patchwork.freedesktop.org/series/81727/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be
On 9/15/2020 7:17 PM, Ville Syrjälä wrote:
On Mon, Sep 14, 2020 at 11:26:26AM +0530, Karthik B S wrote:
Add enable/disable flip done functions and the flip done handler
function which handles the flip done interrupt.
Enable the flip done interrupt in IER.
Enable flip done function is called
On 9/15/2020 7:18 PM, Ville Syrjälä wrote:
On Mon, Sep 14, 2020 at 11:26:27AM +0530, Karthik B S wrote:
Set the Async Address Update Enable bit in plane ctl
when async flip is requested.
v2: -Move the Async flip enablement to individual patch (Paulo)
v3: -Rebased.
v4: -Add separate plane ho
On 9/15/2020 7:33 PM, Ville Syrjälä wrote:
On Mon, Sep 14, 2020 at 11:26:28AM +0530, Karthik B S wrote:
If flip is requested on any other plane, reject it.
Make sure there is no change in fbc, offset and framebuffer modifiers
when async flip is requested.
If any of these are modified, reject
On 9/15/2020 7:37 PM, Ville Syrjälä wrote:
On Mon, Sep 14, 2020 at 11:26:29AM +0530, Karthik B S wrote:
Since the flip done event will be sent in the flip_done_handler,
no need to add the event to the list and delay it for later.
v2: -Moved the async check above vblank_get as it
was cau
On 9/15/2020 7:40 PM, Ville Syrjälä wrote:
On Mon, Sep 14, 2020 at 11:26:30AM +0530, Karthik B S wrote:
This hook is added to avoid writing other plane registers in case of
async flips, so that we do not write the double buffered registers
during async surface address update.
v7: -Plane ctl n
On 9/15/2020 7:49 PM, Ville Syrjälä wrote:
On Mon, Sep 14, 2020 at 11:26:31AM +0530, Karthik B S wrote:
In Gen 9 and Gen 10 platforms, async address update enable bit is
double buffered. Due to this, during the transition from async flip
to sync flip we have to wait until this bit is updated b
== Series Details ==
Series: series starting with [1/3] drm/i915/gt: Show engine properties in the
pretty printer
URL : https://patchwork.freedesktop.org/series/81727/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9019 -> Patchwork_18509
==
Am 16.09.20 um 14:24 schrieb Daniel Vetter:
On Wed, Sep 16, 2020 at 12:48:20PM +0200, Thomas Zimmermann wrote:
Hi
Am 16.09.20 um 11:37 schrieb Daniel Vetter:
On Mon, Sep 14, 2020 at 01:25:18PM +0200, Thomas Zimmermann wrote:
Dma-buf provides vmap() and vunmap() for retrieving and releasing ma
On 9/15/2020 8:11 PM, Ville Syrjälä wrote:
On Mon, Sep 14, 2020 at 11:26:30AM +0530, Karthik B S wrote:
This hook is added to avoid writing other plane registers in case of
async flips, so that we do not write the double buffered registers
during async surface address update.
v7: -Plane ctl n
== Series Details ==
Series: series starting with [1/4] drm/i915/gem: Hold request reference for
canceling an active context
URL : https://patchwork.freedesktop.org/series/81728/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8e90943e9601 drm/i915/gem: Hold request reference fo
== Series Details ==
Series: series starting with [1/4] drm/i915/gem: Hold request reference for
canceling an active context
URL : https://patchwork.freedesktop.org/series/81728/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commi
Hi
Am 16.09.20 um 14:59 schrieb Christian König:
> Am 16.09.20 um 14:24 schrieb Daniel Vetter:
>> On Wed, Sep 16, 2020 at 12:48:20PM +0200, Thomas Zimmermann wrote:
>>> Hi
>>>
>>> Am 16.09.20 um 11:37 schrieb Daniel Vetter:
On Mon, Sep 14, 2020 at 01:25:18PM +0200, Thomas Zimmermann wrote:
>>
== Series Details ==
Series: series starting with [1/4] drm/i915/gem: Hold request reference for
canceling an active context
URL : https://patchwork.freedesktop.org/series/81728/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9019 -> Patchwork_18510
===
== Series Details ==
Series: series starting with [1/3] drm/i915/gt: Signal cancelled requests
URL : https://patchwork.freedesktop.org/series/81729/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
On Fri, 11 Sep 2020, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/pll: Centralize PLL_ENABLE register lookup (rev4)
> URL : https://patchwork.freedesktop.org/series/81150/
> State : warning
>
> == Summary ==
>
> $ dim checkpatch origin/drm-tip
> dac234339c17 drm/i915/pll: Central
On 14/09/20 21:42, Thomas Gleixner wrote:
> CONFIG_PREEMPT_COUNT is now unconditionally enabled and will be
> removed. Cleanup the leftovers before doing so.
>
> Signed-off-by: Thomas Gleixner
> Cc: Ingo Molnar
> Cc: Peter Zijlstra
> Cc: Juri Lelli
> Cc: Vincent Guittot
> Cc: Dietmar Eggeman
On 14/09/20 21:42, Thomas Gleixner wrote:
> CONFIG_PREEMPT_COUNT is now unconditionally enabled and will be
> removed. Cleanup the leftovers before doing so.
>
> Signed-off-by: Thomas Gleixner
> Cc: Ingo Molnar
> Cc: Peter Zijlstra
> Cc: Juri Lelli
> Cc: Vincent Guittot
> Cc: Dietmar Eggeman
Hi Tomas,
Thanks for the patch.
On Tue, Sep 15, 2020 at 08:53:46AM -0700, Laurent Pinchart wrote:
> Hi Thomas,
>
> Thank you for the patch.
>
> On Tue, Sep 15, 2020 at 04:59:57PM +0200, Thomas Zimmermann wrote:
> > The xlnx driver uses CMA helpers with default callback functions.
> > Initialize
== Series Details ==
Series: series starting with [1/3] drm/i915/gt: Signal cancelled requests
URL : https://patchwork.freedesktop.org/series/81729/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9019 -> Patchwork_18511
Summ
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Initialise outparam for error
return from wait_for_register
URL : https://patchwork.freedesktop.org/series/81731/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
870f8ace9fa6 drm/i915: Initialise outparam for e
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Initialise outparam for error
return from wait_for_register
URL : https://patchwork.freedesktop.org/series/81731/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each c
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Initialise outparam for error
return from wait_for_register
URL : https://patchwork.freedesktop.org/series/81731/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9019 -> Patchwork_18512
===
On Wed, 2020-09-16 at 10:43 +0300, Jani Nikula wrote:
> On Tue, 15 Sep 2020, Rodrigo Vivi wrote:
> > On Tue, Sep 15, 2020 at 01:29:35PM -0400, Lyude Paul wrote:
> > > Since we're about to start adding support for Intel's magic HDR
> > > backlight interface over DPCD, we need to ensure we're proper
This hook is added to avoid writing other plane registers in case of
async flips, so that we do not write the double buffered registers
during async surface address update.
v7: -Plane ctl needs bits from skl_plane_ctl_crtc as well. (Ville)
-Add a vfunc for skl_program_async_surface_address
In Gen 9 and Gen 10 platforms, async address update enable bit is
double buffered. Due to this, during the transition from async flip
to sync flip we have to wait until this bit is updated before continuing
with the normal commit for sync flip.
v9: -Rename skl_toggle_async_sync() to skl_disable_as
Without async flip support in the kernel, fullscreen apps where game
resolution is equal to the screen resolution, must perform an extra blit
per frame prior to flipping.
Asynchronous page flips will also boost the FPS of Mesa benchmarks.
v2: -Few patches have been squashed and patches have been
If flip is requested on any other plane, reject it.
Make sure there is no change in fbc, offset and framebuffer modifiers
when async flip is requested.
If any of these are modified, reject async flip.
v2: -Replace DRM_ERROR (Paulo)
-Add check for changes in OFFSET, FBC, RC(Paulo)
v3: -Remov
Since the flip done event will be sent in the flip_done_handler,
no need to add the event to the list and delay it for later.
v2: -Moved the async check above vblank_get as it
was causing issues for PSR.
v3: -No need to wait for vblank to pass, as this wait was causing a
16ms delay once
Set the Async Address Update Enable bit in plane ctl
when async flip is requested.
v2: -Move the Async flip enablement to individual patch (Paulo)
v3: -Rebased.
v4: -Add separate plane hook for async flip case (Ville)
v5: -Rebased.
v6: -Move the plane hook to separate patch. (Paulo)
-Remov
Add the details of the implementation of asynchronous flips for i915.
v7: -Rebased.
v8: -Rebased.
v9: -Rebased.
Signed-off-by: Karthik B S
Signed-off-by: Vandita Kulkarni
---
Documentation/gpu/i915.rst | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/gpu/i915.rst b/Doc
Add enable/disable flip done functions and the flip done handler
function which handles the flip done interrupt.
Enable the flip done interrupt in IER.
Enable flip done function is called before writing the
surface address register as the write to this register triggers
the flip done interrupt
F
Enable asynchronous flips in i915 for gen9+ platforms.
v2: -Async flip enablement should be a stand alone patch (Paulo)
v3: -Move the patch to the end of the series (Paulo)
v4: -Rebased.
v5: -Rebased.
v6: -Rebased.
v7: -Rebased.
v8: -Rebased.
v9: -Rebased.
Signed-off-by: Karthik B S
Signe
== Series Details ==
Series: Asynchronous flip implementation for i915 (rev9)
URL : https://patchwork.freedesktop.org/series/74386/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ed031e0bb186 drm/i915: Add enable/disable flip done and flip done handler
bd5ec737f6d0 drm/i915: Add
== Series Details ==
Series: Asynchronous flip implementation for i915 (rev9)
URL : https://patchwork.freedesktop.org/series/74386/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/dr
On 9/16/2020 6:30 PM, Karthik B S wrote:
On 9/15/2020 8:11 PM, Ville Syrjälä wrote:
On Mon, Sep 14, 2020 at 11:26:30AM +0530, Karthik B S wrote:
This hook is added to avoid writing other plane registers in case of
async flips, so that we do not write the double buffered registers
during asy
== Series Details ==
Series: Asynchronous flip implementation for i915 (rev9)
URL : https://patchwork.freedesktop.org/series/74386/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9019 -> Patchwork_18513
Summary
---
**
In case of dual link, we get the TE on slave.
So clear the TE on slave DSI IIR.
If we are operating in TE_GATE mode, after we do
a frame update, the transcoder will send the frame data
to the panel, after it receives a TE. Whereas if we
are operating in NO_GATE mode then the transcoder will
immedi
In TE Gate mode or TE NO_GATE mode on every flip
we need to set the frame update request bit.
After this bit is set transcoder hardware will
automatically send the frame data to the panel
in case of TE NO_GATE mode, where it sends after
it receives the TE event in case of TE_GATE mode.
Once the fr
Configure TE interrupt as part of the vblank
enable call flow.
v2: Hide the private flags check inside configure_te (Jani)
v3: Fix the position of masking de_port_masked for DSI_TE.
v4: Simplify the caller of configure_te (Jani)
v5: Clear IIR, remove the usage of private_flags
v6: including ic
This series contain interrupt handling part of cmd mode.
Configuration patches were merged already.
v10: Address the review comments on patch 3 and 4
v11: fix compilation issue introduced in v10
v12: fix check patch errors on patch 3
Vandita Kulkarni (4):
drm/i915/dsi: Add details about TE in g
We need details about enabling TE on which port
before we enable TE through vblank enable path.
This is based on the configuration that we receive
from the VBT wrt ports, dual_link.
Signed-off-by: Vandita Kulkarni
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c | 30
== Series Details ==
Series: series starting with [1/3] drm/i915/gt: Show engine properties in the
pretty printer
URL : https://patchwork.freedesktop.org/series/81727/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9019_full -> Patchwork_18509_full
For platforms without selective fetch this register is reserved so
do not write 0 to it.
Cc: Gwan-gyeong Mun
Cc: Ville Syrjälä
Reviewed-by: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
dif
Due to the debugfs flag, has_psr2 in CRTC state could have a different
value than psr.psr2_enabled and it was causing PSR2 subfeatures(DC3CO
and selective fetch) to be set to not a expected state.
So here only taking in consideration the parameter and debugfs flag
when computing PSR state, this wa
Another step towards PSR2 selective fetch, here programming plane
selective fetch registers and MAN_TRK_CTL enabling selective fetch but
for now it is fetching the whole area of the planes.
The damaged area calculation will come as next and final step.
v2:
- removed warn on when no plane is visibl
== Series Details ==
Series: Add support for mipi dsi cmd mode (rev12)
URL : https://patchwork.freedesktop.org/series/69290/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9019 -> Patchwork_18514
Summary
---
**WARNING
From: Matthew Brost
The new GuC interface has removed GUC_CTL_CTXINFO from initialization
params.
Cc: John Harrison
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c | 18 --
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 15 +--
2 files c
From: Matthew Brost
The new GuC requires the additional data structure and associated
'private_data' pointer to be setup. This is basically a scratch area
of memory that the GuC owns. The size is read from the CSS header.
Cc: John Harrison
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915
From: Michal Wajdeczko
Starting from Gen11, the ID to be provided to GuC needs to contain
the engine class in bits [0..2] and the instance in bits [3..6].
NOTE: this patch breaks pointer dereferences in some existing GuC
functions that use the guc_id to dereference arrays but these functions
are
From: John Harrison
Was hitting null pointers and similar issues when running various
module load/unload and inject failure type tests. So clear those
pointers down when the objects have been de-allocated.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 1 +
drive
From: John Harrison
The ADS layout changes significantly with GuC firmware v42. This patch
updates the shared structure (but does not fill in the new tables,
that comes later as part of the GuC submission support). It also adds
better documentation of the layout.
Signed-off-by: John Harrison
--
From: Michal Wajdeczko
Starting GuC firmware version 40.0 reg_state_buffer is maintained
internally by the GuC as part of "private data".
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 2 --
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 2 +-
2 files changed,
From: John Harrison
Update to the latest GuC firmware and enable by default.
Signed-off-by: John Harrison
Daniele Ceraolo Spurio (1):
drm/i915/uc: turn on GuC/HuC auto mode by default
John Harrison (5):
drm/i915/guc: ADS changes for GuC v42
drm/i915/guc: Increased engine classes in ADS
From: Michal Wajdeczko
While i915 does not use GuC doorbells, the firmware requires that some
initialisation is done.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 9 +
drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 2 +-
d
From: John Harrison
GuC v46 partially increased the number of engine classes supported in
the ADS. GuC v48 then finished the change off by cleaning up the
per class engine mask fields.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 16 +---
drivers/g
From: Matthew Brost
The new GuC FW introduces a physical to logical engine mapping table in
the GuC additional data structures which needs to be configured in order
for the firmware to load. This patch initializes the table with a 1 to 1
mapping.
Signed-off-by: Matthew Brost
CC: John Harrison
From: Daniele Ceraolo Spurio
This will enable HuC loading for Gen11+ by default if the binaries
are available on the system. GuC submission still requires explicit
enabling by the user.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1
From: John Harrison
Note that the GuC major version jumped from 35 to 40. This is because
the v40 firmware included a significant re-write of the API. The 'new
GuC API' patch series is required to make use of command submission
with this new GuC firmware. Versions 36 through 39 are reserved for
u
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