Chris Wilson writes:
> Unlike rcs where we have conclusive evidence from our selftesting that
> disabling the preparser before performing the TLB invalidate and
> relocations does impact upon the GPU execution, the evidence for the
> same requirement on xcs is much more circumstantial. Let's appl
Chris Wilson writes:
> Whether this is an arbitrary stall or a vital ingredient, neverthess the
> impact is noticeable. If we do not have the stall around the xcs
> invalidation before a request, writes within that request sometimes go
> astray.
>
> Closes: https://gitlab.freedesktop.org/drm/inte
Nicolas Boichat writes:
> On Thu, Jul 23, 2020 at 9:17 PM Felipe Balbi wrote:
>>
>> Nicolas Boichat writes:
>>
>> > trace_printk should not be used in production code, replace it
>> > call with dev_dbg.
>> >
>> > Signed-off-by: Nicolas Boichat
>> >
>> > ---
>> >
>> > Unclear why a trace_printk
Quoting Mika Kuoppala (2020-07-24 08:38:56)
> Chris Wilson writes:
>
> > Whether this is an arbitrary stall or a vital ingredient, neverthess the
> > impact is noticeable. If we do not have the stall around the xcs
> > invalidation before a request, writes within that request sometimes go
> > ast
Quoting Umesh Nerlige Ramappa (2020-07-24 01:19:00)
> From: Piotr Maciejewski
>
> It is useful to have markers in the OA reports to identify triggered
> reports. Whitelist some OA counters that can be used as markers.
>
> A triggered report can be found faster if we can sample the HW tail and
>
Quoting Umesh Nerlige Ramappa (2020-07-24 01:18:59)
> From: Piotr Maciejewski
>
> OA reports can be triggered into the OA buffer by writing into the
> OAREPORTTRIG registers. Whitelist the registers to allow user to trigger
> reports.
>
> v2:
> - Move related change to this patch (Lionel)
> - Bu
On 23/07/2020 20:51, Chris Wilson wrote:
The flags passed to the wait_entry.func are passed onwards to
try_to_wake_up(), which has a very particular interpretation for its
wake_flags. In particular, beyond the published WF_SYNC, it has a few
internal flags as well. Since we passed the fence->erro
Quoting Andrew Parsons (2020-07-24 02:55:04)
> Hello all,
>
> TL;DR: my questions concern the following two topics:
> - CRTCs and Intel integrated GPUs
> - intel-virtual-output utility
>
> I have a laptop with both an Intel integrated GPU and an AMD discrete GPU.
>
> ```
> ➜ ~ xrandr --listprov
On 24/07/2020 12:26, Chris Wilson wrote:
Quoting Umesh Nerlige Ramappa (2020-07-24 01:18:59)
From: Piotr Maciejewski
OA reports can be triggered into the OA buffer by writing into the
OAREPORTTRIG registers. Whitelist the registers to allow user to trigger
reports.
v2:
- Move related change t
Quoting Lionel Landwerlin (2020-07-24 11:07:18)
> On 24/07/2020 12:26, Chris Wilson wrote:
> > Quoting Umesh Nerlige Ramappa (2020-07-24 01:18:59)
> >> diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> >> b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> >> index febc9e6692ba..3b1d3db
Quoting Chris Wilson (2020-07-24 11:19:05)
> Quoting Lionel Landwerlin (2020-07-24 11:07:18)
> > On 24/07/2020 12:26, Chris Wilson wrote:
> > > Quoting Umesh Nerlige Ramappa (2020-07-24 01:18:59)
> > >> diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
> > >> b/drivers/gpu/drm/i915/gt/se
On 24/07/2020 13:19, Chris Wilson wrote:
Quoting Lionel Landwerlin (2020-07-24 11:07:18)
On 24/07/2020 12:26, Chris Wilson wrote:
Quoting Umesh Nerlige Ramappa (2020-07-24 01:18:59)
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
b/drivers/gpu/drm/i915/gt/selftest_workarounds.c
in
On 24/07/2020 13:23, Chris Wilson wrote:
Quoting Chris Wilson (2020-07-24 11:19:05)
Quoting Lionel Landwerlin (2020-07-24 11:07:18)
On 24/07/2020 12:26, Chris Wilson wrote:
Quoting Umesh Nerlige Ramappa (2020-07-24 01:18:59)
diff --git a/drivers/gpu/drm/i915/gt/selftest_workarounds.c
b/drive
Quoting Lionel Landwerlin (2020-07-24 11:33:38)
> On 24/07/2020 13:23, Chris Wilson wrote:
> > Quoting Chris Wilson (2020-07-24 11:19:05)
> >> Quoting Lionel Landwerlin (2020-07-24 11:07:18)
> >>> On 24/07/2020 12:26, Chris Wilson wrote:
> Quoting Umesh Nerlige Ramappa (2020-07-24 01:18:59)
>
Whether this is an arbitrary stall or a vital ingredient, neverthess the
impact is noticeable. If we do not have the stall around the xcs
invalidation before a request, writes within that request sometimes go
astray.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2169
Signed-off-by: Chr
Unlike rcs where we have conclusive evidence from our selftesting that
disabling the preparser before performing the TLB invalidate and
relocations does impact upon the GPU execution, the evidence for the
same requirement on xcs is much more circumstantial. Let's apply the
preparser disable between
Since we want to read the values from the HWSP as written to by the GPU,
warn the compiler that the values are volatile.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/selftest_timeline.c | 23 +++--
1 file changed, 12 insertions(+), 11 deletions(-)
d
Chris Wilson writes:
> Quoting Chris Wilson (2020-07-23 19:33:48)
>> Avoid exposing a partially constructed context by deferring the
>> list_add() from the initial construction to the end of registration.
>> Otherwise, if we peek into the list of contexts from inside debugfs, we
>> may see the pa
Chris Wilson writes:
> Since we want to read the values from the HWSP as written to by the GPU,
> warn the compiler that the values are volatile.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/selftest_timeline.c | 23 +
Chris Wilson writes:
> Whether this is an arbitrary stall or a vital ingredient, neverthess the
> impact is noticeable. If we do not have the stall around the xcs
> invalidation before a request, writes within that request sometimes go
> astray.
>
> Closes: https://gitlab.freedesktop.org/drm/inte
== Series Details ==
Series: series starting with [1/3] drm/i915/gt: Disable preparser around xcs
invalidations on tgl
URL : https://patchwork.freedesktop.org/series/79846/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e60c2dc861ee drm/i915/gt: Disable preparser around xcs inv
== Series Details ==
Series: series starting with [1/3] drm/i915/gt: Disable preparser around xcs
invalidations on tgl
URL : https://patchwork.freedesktop.org/series/79846/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won'
Quoting Mika Kuoppala (2020-07-24 12:55:39)
> Chris Wilson writes:
>
> > Quoting Chris Wilson (2020-07-23 19:33:48)
> >> Avoid exposing a partially constructed context by deferring the
> >> list_add() from the initial construction to the end of registration.
> >> Otherwise, if we peek into the li
Avoid exposing a partially constructed context by deferring the
list_add() from the initial construction to the end of registration.
Otherwise, if we peek into the list of contexts from inside debugfs, we
may see the partially constructed context and chase down some dangling
incomplete pointers.
R
Chris Wilson writes:
> Quoting Mika Kuoppala (2020-07-24 12:55:39)
>> Chris Wilson writes:
>>
>> > Quoting Chris Wilson (2020-07-23 19:33:48)
>> >> Avoid exposing a partially constructed context by deferring the
>> >> list_add() from the initial construction to the end of registration.
>> >> Ot
== Series Details ==
Series: series starting with [1/3] drm/i915/gt: Disable preparser around xcs
invalidations on tgl
URL : https://patchwork.freedesktop.org/series/79846/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8783 -> Patchwork_18238
=
== Series Details ==
Series: drm/i915/gem: Delay tracking the GEM context until it is registered
(rev2)
URL : https://patchwork.freedesktop.org/series/79822/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ea0e7079cf62 drm/i915/gem: Delay tracking the GEM context until it is reg
== Series Details ==
Series: drm/i915/gem: Delay tracking the GEM context until it is registered
(rev2)
URL : https://patchwork.freedesktop.org/series/79822/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked se
Quoting Umesh Nerlige Ramappa (2020-07-24 01:19:01)
> From: Piotr Maciejewski
>
> i915 used to support time based sampling mode which is good for overall
> system monitoring, but is not enough for query mode used to measure a
> single draw call or dispatch. Gen9-Gen11 are using current i915 perf
== Series Details ==
Series: drm/i915/gem: Delay tracking the GEM context until it is registered
(rev2)
URL : https://patchwork.freedesktop.org/series/79822/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8783 -> Patchwork_18239
On Fri, Jul 24, 2020 at 01:42:33PM +0100, Chris Wilson wrote:
Quoting Umesh Nerlige Ramappa (2020-07-24 01:19:01)
From: Piotr Maciejewski
i915 used to support time based sampling mode which is good for overall
system monitoring, but is not enough for query mode used to measure a
single draw ca
Quoting Umesh Nerlige Ramappa (2020-07-24 17:29:56)
> On Fri, Jul 24, 2020 at 01:42:33PM +0100, Chris Wilson wrote:
> >Quoting Umesh Nerlige Ramappa (2020-07-24 01:19:01)
> >> From: Piotr Maciejewski
> >>
> >> i915 used to support time based sampling mode which is good for overall
> >> system moni
Some very low hanging fruit, but contention on the pool->lock is
noticeable between intel_gt_get_buffer_pool() and pool_retire(), with
the majority of the hold time due to the locked list iteration. If we
make the node itself RCU protected, we can perform the search for an
suitable node just under
== Series Details ==
Series: drm/i915/gt: Delay taking the spinlock for grabbing from the buffer pool
URL : https://patchwork.freedesktop.org/series/79855/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separ
== Series Details ==
Series: drm/i915/gt: Delay taking the spinlock for grabbing from the buffer pool
URL : https://patchwork.freedesktop.org/series/79855/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8783 -> Patchwork_18240
===
Since we likely know all the old devices, an unknown device is most
likely a future device, so use -1u instead of 0 for its generation.
Signed-off-by: Chris Wilson
---
lib/intel_device_info.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/lib/intel_device_info.c b/lib/in
Don't use the encoded information within the PCI-ID for the GT value, as
the rules keep changing. Use the device info instead.
Signed-off-by: Chris Wilson
---
lib/intel_chipset.h | 1 -
lib/intel_device_info.c | 23 ---
tools/intel_l3_parity.c | 5 +++--
tools/int
commit a048d54f58dd ("lib: Sync i915 PCI ids") added the ids for
Rocketlake, but no identification tables.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2217
Signed-off-by: Chris Wilson
---
lib/intel_chipset.h | 2 ++
lib/intel_device_info.c | 7 +++
2 files changed, 9 insert
IGT disallows ':' in its subtest names, and as we use the engine name
for dynamic subtest names, pick a name that doesn't accidentally cause
IGT to assert (even when those tests are not being run).
Signed-off-by: Chris Wilson
---
lib/i915/gem_engine_topology.c | 2 +-
1 file changed, 1 insertion
Some very low hanging fruit, but contention on the pool->lock is
noticeable between intel_gt_get_buffer_pool() and pool_retire(), with
the majority of the hold time due to the locked list iteration. If we
make the node itself RCU protected, we can perform the search for an
suitable node just under
== Series Details ==
Series: drm/i915/gt: Delay taking the spinlock for grabbing from the buffer
pool (rev2)
URL : https://patchwork.freedesktop.org/series/79855/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be check
== Series Details ==
Series: drm/i915/gt: Delay taking the spinlock for grabbing from the buffer
pool (rev2)
URL : https://patchwork.freedesktop.org/series/79855/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8784 -> Patchwork_18241
===
On Fri, Jul 24, 2020 at 05:34:11PM +0100, Chris Wilson wrote:
Quoting Umesh Nerlige Ramappa (2020-07-24 17:29:56)
On Fri, Jul 24, 2020 at 01:42:33PM +0100, Chris Wilson wrote:
>Quoting Umesh Nerlige Ramappa (2020-07-24 01:19:01)
>> From: Piotr Maciejewski
>>
>> i915 used to support time based s
Quoting Umesh Nerlige Ramappa (2020-07-24 19:47:37)
> On Fri, Jul 24, 2020 at 05:34:11PM +0100, Chris Wilson wrote:
> >Quoting Umesh Nerlige Ramappa (2020-07-24 17:29:56)
> >> On Fri, Jul 24, 2020 at 01:42:33PM +0100, Chris Wilson wrote:
> >> >Quoting Umesh Nerlige Ramappa (2020-07-24 01:19:01)
> >
On Fri, Jul 24, 2020 at 07:55:06PM +0100, Chris Wilson wrote:
Quoting Umesh Nerlige Ramappa (2020-07-24 19:47:37)
On Fri, Jul 24, 2020 at 05:34:11PM +0100, Chris Wilson wrote:
>Quoting Umesh Nerlige Ramappa (2020-07-24 17:29:56)
>> On Fri, Jul 24, 2020 at 01:42:33PM +0100, Chris Wilson wrote:
>>
Quoting Umesh Nerlige Ramappa (2020-07-24 20:35:11)
> I agree, but strangely, with mmap sequence below, I don't see
> i915_perf_release() called at all. So destroy() is not called.
>
> perf_fd = i915_perf_open_ioctl()
> mmap(..., perf_fd...)
> close(perf_fd)
> delay for a few seconds.
>
> If I
Reviewed-by: Daniele Ceraolo Spurio
Daniele
On 7/10/2020 2:32 PM, john.c.harri...@intel.com wrote:
From: John Harrison
The above workaround was added as an engine workaround not a GT
workaround. Moved it to the correct location.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/in
From: Aditya Swarup
Add entries for dg1 plls and setup dg1_pll_mgr to reuse icl callbacks.
Initial setup for shared dplls DPLL0/1 for DDIA/B and DPLL2/3 for
DDIC/D. Configure dpll cfgcrx registers to drive the plls on DG1.
Signed-off-by: Aditya Swarup
Signed-off-by: Lucas De Marchi
---
driver
Add tables to map the GMBUS pin pairs to GPIO registers and port to DDC.
The values for VBT are currently not in BSpec. If we assume the latest
is ICL (like we did for TGL), then the mapping is wrong per VBT we can
currently parse.
>From spec we have registers GPIO_CTL[1-4], so we should not do t
From: Uma Shankar
Most of TGL power wells are re-used for DG1. However, AUDIO Power
Domain is moved from PG3 to PG0. Handle the change and initialize
power wells with the new power well structure.
Some of the Audio Streaming logic still remains in PW3 so still
it needs to be enabled.
DDIA, DDIB
From: Matt Roper
The only bit we use in PHY_MISC is DE_IO_COMP_PWR_DOWN, and the bspec
details for that bit tell us that it need only be set for PHY-A and
PHY-B. It also turns out that there isn't even an instance of the
PHY_MISC register for PHY-D on this platform. Let's extend the EHL/RKL
log
From: Aditya Swarup
DG1 has 4 DPLLs where DPLL0 and DPLL1 drive DDIA/B and
DPLL2 and DPLL3 drive DDIC/DDID.
Introduce DG1_DPLL_CFCRx() helper macros to configure
DPLL registers.
Bspec: 50288, 50299
Cc: Matt Roper
Signed-off-by: Aditya Swarup
Signed-off-by: Lucas De Marchi
---
drivers/gpu/d
From: Aditya Swarup
Enable PORTS A and B for DG1 initially, the other ports still need more
plumbing code in order to be enabled.
Cc: Clinton Taylor
Cc: Matt Roper
Cc: Lucas De Marchi
Signed-off-by: Aditya Swarup
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display
DG1 has one more combo phy port, no TC and all irq handling goes through
SDE, like for MCC.
v2: Also change intel_hpd_pin_default() to include DG1 mapping
Cc: Anshuman Gupta
Cc: José Roberto de Souza
Cc: Imre Deak
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_hotplug.
From: Matt Roper
DG1 always uses a 38.4 MHz rawclk rather than the 19.2/24 MHz
frequencies on CNP+. Note that register bits associated with this
frequency confusingly use 37 for the divider field rather than 38 as you
might expect.
For simplicity, let's just assume that this 38.4 MHz frequency
From: Anshuman Gupta
DGFX devices have different DMC_DEBUG* counter MMIO address
offset. Incorporate these changes in i915_reg.h for DG1 DC5/DC6
counter and handle i915_dmc_info accordingly.
Cc: Uma Shankar
Signed-off-by: Anshuman Gupta
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915
v4:
- Remove already applied patches and rebase the rest
- Add new workarounds
- Add change to DMC_DEBUG register
v3:
- Make sure we don't bind the driver to the device while the driver is
not complete. This should unblock us to have these basic patches
merged so the next parts can be develope
From: Matt Atwood
Add support to load DMC v2.0.2 on DG1
While we're at it, tweak the TGL and RKL firmware size definition to
follow the convention used in previous platforms. Remove obsolete
commenting.
Bpec: 49230
Cc: Matt Roper
Signed-off-by: Matt Atwood
Signed-off-by: Lucas De Marchi
---
From: Matt Roper
DG1 does some additional pcode/uncore handshaking at
boot time; this handshaking must complete before various other pcode
commands are effective and before general work is submitted to the GPU.
We need to poll a new pcode mailbox during startup until it reports that
this handshak
From: Stuart Summers
DG1 shares some workarounds with TGL and RKL and also has some
additional workarounds of its own.
Media power gating should not be applied so we just set it to
nop_init_clock_gating().
v2: Corrected location of Wa_1408615072 (JohnH).
v3: Aplying WAs 1606700617, 18011464164
From: Matt Roper
As with RKL, DG1's VBT outputs are indexed according to PHY rather than
DDI.
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_bios.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915
For DG1 we have a little of mix up wrt to DDI/port names and indexes.
Bspec refers to the ports as DDIA, DDIB, DDI USBC1 and DDI USBC2
(besides the DDIA, DDIB, DDIC, DDID), but the previous naming is the
most unambiguous one. This means that for any register on Display Engine
we should use the inde
From: Matt Roper
DG1's vswing tables are the same for eDP and HDMI but have slight
differences from ICL/TGL for DP.
Bspec: 49291
Cc: Clinton Taylor
Cc: José Roberto de Souza
Cc: Radhakrishna Sripada
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/i
DG1 has a new MOCS table. We still use the old definition of the table,
but as for any dgfx card it doesn't contain the control_value values
(these values don't matter as we won't program them).
Bspec: 45101
Cc: Daniele Ceraolo Spurio
Cc: Rodrigo Vivi
Signed-off-by: Lucas De Marchi
---
driver
From: Anshuman Gupta
DC6 is not supported on DG1, so change the allowed DC mask for DG1.
Cc: Uma Shankar
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_power.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/in
From: Aditya Swarup
Add DG1 DPLL Enable register macro and use the macro to enable the
correct DPLL based on PLL id.
Bspec: 49443, 49206
Cc: Clinton Taylor
Cc: Matt Roper
Signed-off-by: Aditya Swarup
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 30
DG1 uses 2 registers for the ddi clock mapping, with PHY A and B using
DPCLKA_CFGCR0 and PHY C and D using DPCLKA1_CFGCR0. Hide this behind a
single macro that chooses the correct register according to the phy
being accessed, use the correct bitfields for each pll/phy and implement
separate functio
From: Clinton A Taylor
HPD pins are inverted for DG1 platform.
Bspec: 49956
Cc: José Roberto de Souza
Cc: Matt Roper
Signed-off-by: Clinton A Taylor
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_irq.c | 9 +
drivers/gpu/drm/i915/i915_reg.h | 4
2 files changed, 1
From: Matt Roper
As with RKL, DG1's PHY C acts as a comp master for PHY D.
Bspec: 49291
Signed-off-by: Matt Roper
Signed-off-by: Lucas De Marchi
Reviewed-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/display/intel_combo_phy.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --g
From: Venkata Sandeep Dhanalakota
On dgfx register range has been extended to go up to 4MB.
Cc: Daniele Ceraolo Spurio
Cc: Michael J. Ruhl
Signed-off-by: Venkata Sandeep Dhanalakota
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/intel_uncore.c | 4
1 file changed, 4 insertions
== Series Details ==
Series: Introduce DG1
URL : https://patchwork.freedesktop.org/series/79863/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8f74e276b41a drm/i915/dg1: Initialize RAWCLK properly
c2699a393ba3 drm/i915/dg1: Define MOCS table for DG1
da0e39cc42f3 drm/i915/dg1: A
== Series Details ==
Series: Introduce DG1
URL : https://patchwork.freedesktop.org/series/79863/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.
___
In
On Fri, Jul 24, 2020 at 08:46:16PM +0100, Chris Wilson wrote:
Quoting Umesh Nerlige Ramappa (2020-07-24 20:35:11)
I agree, but strangely, with mmap sequence below, I don't see
i915_perf_release() called at all. So destroy() is not called.
perf_fd = i915_perf_open_ioctl()
mmap(..., perf_fd...)
On Tue, Jun 16, 2020 at 08:34:07PM +0300, Ville Syrjälä wrote:
> On Tue, Jun 16, 2020 at 09:34:06AM -0700, Matt Atwood wrote:
> > Add minimum width to planes, variable with specific formats, for gen11+.
> >
> > Signed-off-by: Matt Atwood
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c |
== Series Details ==
Series: Introduce DG1
URL : https://patchwork.freedesktop.org/series/79863/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8786 -> Patchwork_18242
Summary
---
**FAILURE**
Serious unknown change
Em seg, 2020-07-20 às 17:01 +0530, Karthik B S escreveu:
> Without async flip support in the kernel, fullscreen apps where game
> resolution is equal to the screen resolution, must perform an extra blit
> per frame prior to flipping.
>
> Asynchronous page flips will also boost the FPS of Mesa benc
Em seg, 2020-07-20 às 17:01 +0530, Karthik B S escreveu:
> Set the Async Address Update Enable bit in plane ctl
> when async flip is requested.
>
> v2: -Move the Async flip enablement to individual patch (Paulo)
>
> v3: -Rebased.
>
> v4: -Add separate plane hook for async flip case (Ville)
>
>
Em seg, 2020-07-20 às 17:01 +0530, Karthik B S escreveu:
> Add enable/disable flip done functions and the flip done handler
> function which handles the flip done interrupt.
>
> Enable the flip done interrupt in IER.
>
> Enable flip done function is called before writing the
> surface address reg
On Thu, Jul 23, 2020 at 03:10:21PM -0700, José Roberto de Souza wrote:
> Although the WA description targets the platforms it is a workaround
> for the affected PCHs, that is why it is being checked.
>
> BSpec: 52890
> BSpec: 53273
> BSpec: 52888
> Signed-off-by: José Roberto de Souza
> ---
> dr
79 matches
Mail list logo
