Let userspace know if they can trust timeslicing by including it as part
of the I915_PARAM_HAS_SCHEDULER::I915_SCHEDULER_CAP_TIMESLICING
v2: Only declare timeslicing if we can safely preempt userspace.
Fixes: 8ee36e048c98 ("drm/i915/execlists: Minimalistic timeslicing")
Link: https://gitlab.freed
A key prolem with legacy ring buffer submission is that it is an inheret
FIFO queue across all clients; if one blocks, they all block. A
scheduler allows us to avoid that limitation, and ensures that all
clients can submit in parallel, removing the resource contention of the
global ringbuffer.
Hav
It is reasonably common for userspace (even modern drivers like iris) to
reuse an active address for a new buffer. This would cause the
application to stall under its mutex (originally struct_mutex) until the
old batches were idle and it could synchronously remove the stale PTE.
However, we can que
If we fail during engine setup, we may leave some engines not yet setup.
During the error cleanup, we have to be careful not to try and use the
uninitialise engines before discarding them.
[ 16.136152] RIP: 0010:__flush_work+0x198/0x1b0
[ 16.136168] Code: ff ff 8b 0b 48 8b 53 08 83 e1 08 48 0f
We allow exported sync_file fences to be used as submit fences, but they
are not the only source of user fences. We also accept an array of
syncobj, and as with sync_file these are dma_fences underneath and so
feature the same set of controls. The submit-fence allows for a request
to be scheduled a
Allocate a few dma fence context id that we can use to associate async work
[for the CPU] launched on behalf of this context. For extra fun, we allow
a configurable concurrency width.
A current example would be that we spawn an unbound worker for every
userptr get_pages. In the future, we wish to
Although we may chide userspace for reusing the same batches
concurrently from multiple threads, at the same time we must be very
careful to only execute the batch and its relocations as supplied by the
user. If we are not careful, we may allow another thread to rewrite the
current batch with its o
If the execbuf is interrupted after building the cmdparser pipeline, and
before we commit to submitting the request to HW, we would attempt to
clean up the cmdparser early. While we held active references to the vma
being parsed and constructed, we did not hold an active reference for
the buffer po
This was removed in commit 478ffad6d690 ("drm/i915: drop
engine_pin/unpin_breadcrumbs_irq") as the last user had been removed,
but now there is a promise of a new user in the next patch.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_breadcrumbs.c | 22 +
drive
If a syncobj has not yet been assigned, treat it as a future fence and
install and wait upon a dma-fence-proxy. The proxy will be replace by
the real fence later, and that fence will be responsible for signaling
our waiter.
Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4854
Signe
Ever noticed that our interrupt handlers are where we spend most of our
time on a busy system? In part this is unavoidable as each interrupt
requires to poll and reset several registers, but we can try and so as
efficiently as possible.
Function old new de
If we get interrupted in the middle of chaining up the relocation
entries, we will fail to submit the relocation batch. However, we will
report having already completed some of the relocations, and so the
reloc.presumed_offset will no longer match the batch contents, causing
confusion and invalid f
This timeout is only used in one place, to provide a tiny bit of grace
for slow igt to cleanup after themselves. If we are a bit stricter and
opt to kill outstanding requsts rather than wait, we can speed up igt by
not waiting for 200ms after a hang.
Signed-off-by: Chris Wilson
---
drivers/gpu/d
Pull the routines for writing CS packets out of intel_ring_submission
into their own files. These are low level operations for building CS
instructions, rather than the logic for filling the global ring buffer
with requests, and we will wnat to reuse them outside of this context.
Signed-off-by: Ch
Sometimes an engine might need to keep forcewake active while it is busy
submitting requests for a particular workaround. Track such nuisance
with engine->fw_domain.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_types.h | 9 +
drivers/gpu/drm/i915/gt/intel_ring_s
To support legacy ring buffer scheduling, we want a virtual ringbuffer
for each client. These rings are purely for holding the requests as they
are being constructed on the CPU and never accessed by the GPU, so they
should not be bound into the GGTT, and we can use plain old WB mapped
pages.
As th
Couple up the context in/out accounting to record how long each engine
is busy handling requests. This is exposed to userspace for more accurate
measurements, and also enables our soft-rps timer.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_stats.h | 49 +++
driv
Often we need to create a fence for a future event that has not yet been
associated with a fence. We can store a proxy fence, a placeholder, in
the timeline and replace it later when the real fence is known. Any
listeners that attach to the proxy fence will automatically be signaled
when the real f
One more list iterator variant, for when we want to unwind from inside
one list iterator with the intention of restarting from the current
entry as the new head of the list.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_utils.h | 6 ++
1 file changed, 6 insertions(+)
diff --git
Should we gain per-client timelines, we can then utilise the separate
HWSP in order to use MI_SEMAPHORE_MBOX with the unique GGTT addresses
required for synchronising between clients across different engines.
Teach the emit_semaphore_wait about MI_SEMAPHORE_MBOX for the older
generations.
Note tha
Asynchronous waits and signaling form a traditional semaphore with all
the usual ordering problems with taking multiple locks. If we want to
add more than one wait on a shared resource by the GPU, we must ensure
that all the associated timelines are advanced atomically, ergo we must
lock all the ti
Over the next couple of patches, we will want to lock all the modified
vma for relocation processing under a single ww_mutex. We neither want
to have to include the vma that are skipped (due to no modifications
required) nor do we want those to be marked as written too. So separate
out the reloc va
If the real target for a proxy fence is known at the time we are
attaching our awaits, use the real target in preference to hooking up to
the proxy. If use the real target instead, we can optimize the awaits,
e.g. if it along the same engine, we can order the submission and avoid
the wait-for-compl
Build a bare bones scheduler to sit on top the global legacy ringbuffer
submission. This virtual execlists scheme should be applicable to all
older platforms.
A key problem we have with the legacy ring buffer submission is that it
only allows for FIFO queuing. All clients share the global request
Reduce the 3 relocation patches down to the single path that accommodates
all. The primary motivation for this is to guard the relocations with a
natural fence (derived from the i915_request used to write the
relocation from the GPU).
The tradeoff in using async gpu relocations is that it increase
If any engine asks for the tasklet to be kicked from the CS interrupt,
do so.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 17 -
drivers/gpu/drm/i915/gt/intel_gt_irq.h | 3 +++
drivers/gpu/drm/i915/gt/intel_rps.c| 2 +-
drivers/gpu/drm/i915/i915_
Our forcewake utilisation is split into categories: automatic and
manual. Around bare register reads, we look up the right forcewake
domain and automatically acquire and release [upon a timer] the
forcewake domain. For other access, where we know we require the
forcewake across a group of register
Allow the callers to supply a dma-fence-proxy for asynchronous waiting on
future fences.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/drm_syncobj.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/drm_syncobj.c b/drivers/gpu/drm/drm_syncobj.c
index 4
Since we have reduced the relocations paths to just use the async GPU,
we can lift the request allocation to the start of the relocations.
Knowing that we use one request for all relocations will simplify
tracking the relocation fence.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_ge
Switch over from FIFO global submission to the priority-sorted
topographical scheduler. At the cost of more busy work on the CPU to
keep the GPU supplied with the next packet of requests, this allows us
to reorder requests around submission stalls.
This also enables the timer based RPS, with the e
Use the central mechanism for recording and verifying that we restore
the w/a for the older devices as well.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gt/intel_ring_submission.c | 28 -
drivers/gpu/drm/i915/gt/intel_workarounds.c | 31 +++
2 files chang
Currently, if an error is raised we always call the cleanup locally
[and skip the main work callback]. However, some future users may need
to take a mutex to cleanup and so we cannot immediately execute the
cleanup as we may still be in interrupt context.
With the execute-immediate flag, for most
Sometimes we have to be very careful not to allocate underneath a mutex
(or spinlock) and yet still want to track activity. Enter
i915_active_acquire_for_context(). This raises the activity counter on
i915_active prior to use and ensures that the fence-tree contains a slot
for the context.
Signed-
It is illegal to wait on an another vma while holding the vm->mutex, as
that easily leads to ABBA deadlocks (we wait on a second vma that waits
on us to release the vm->mutex). So while the vm->mutex exists, move the
waiting outside of the lock into the async binding pipeline.
Signed-off-by: Chris
In preparation for making eb_vma bigger and heavy to run inn parallel,
we need to stop apply an in-place swap() to reorder around ww_mutex
deadlocks. Keep the array intact and reorder the locks using a dedicated
list.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c
If we allow for per-client timelines, even with legacy ring submission,
we open the door to a world full of possiblities [scheduling and
semaphores].
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/gen6_engine_cs.c | 21 +
1 file changed, 9 insertions(+), 12 deletions
== Series Details ==
Series: series starting with [01/36] drm/i915: Handle very early engine
initialisation failure
URL : https://patchwork.freedesktop.org/series/77857/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
96d738818236 drm/i915: Handle very early engine initialisatio
Currently the plane property doesn't have support for YCBCR_BT2020,
which enables the corresponding color conversion mode on plane CSC.
Enabling the plane property for the planes for GLK & ICL+ platforms.
Also as per spec, update the Plane Color CSC from YUV601_TO_RGB709
to YUV601_TO_RGB601.
V2: E
== Series Details ==
Series: series starting with [01/36] drm/i915: Handle very early engine
initialisation failure
URL : https://patchwork.freedesktop.org/series/77857/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't b
On Fri, May 29, 2020 at 04:57:38PM -0700, Manasi Navare wrote:
> On Tue, May 26, 2020 at 12:48:52PM +0300, Stanislav Lisovskiy wrote:
> > Previous patch didn't take into account all pipes
> > but only those in state, which could cause wrong
> > CDCLK conclcusions and calculations.
> > Also there wa
== Series Details ==
Series: series starting with [01/36] drm/i915: Handle very early engine
initialisation failure
URL : https://patchwork.freedesktop.org/series/77857/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8560 -> Patchwork_17826
On Fri, May 29, 2020 at 08:11:43AM +0300, Ville Syrjälä wrote:
> On Thu, May 28, 2020 at 10:58:52PM +0300, Lisovskiy, Stanislav wrote:
> > On Thu, May 28, 2020 at 10:38:52PM +0300, Lisovskiy, Stanislav wrote:
> > > On Wed, May 27, 2020 at 11:02:45PM +0300, Ville Syrjala wrote:
> > > > From: Ville S
Couple up the context in/out accounting to record how long each engine
is busy handling requests. This is exposed to userspace for more accurate
measurements, and also enables our soft-rps timer.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_stats.h | 49 ++
drive
== Series Details ==
Series: drm/i915: Add Plane color encoding support for YCBCR_BT2020 (rev6)
URL : https://patchwork.freedesktop.org/series/75660/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8560 -> Patchwork_17827
Sum
== Series Details ==
Series: series starting with [01/36] drm/i915: Handle very early engine
initialisation failure (rev2)
URL : https://patchwork.freedesktop.org/series/77857/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b0896ff73ea4 drm/i915: Handle very early engine initia
== Series Details ==
Series: series starting with [01/36] drm/i915: Handle very early engine
initialisation failure (rev2)
URL : https://patchwork.freedesktop.org/series/77857/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit
== Series Details ==
Series: series starting with [01/36] drm/i915: Handle very early engine
initialisation failure (rev2)
URL : https://patchwork.freedesktop.org/series/77857/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8560 -> Patchwork_17828
=
== Series Details ==
Series: drm/i915: Add Plane color encoding support for YCBCR_BT2020 (rev6)
URL : https://patchwork.freedesktop.org/series/75660/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8560_full -> Patchwork_17827_full
===
Gen12 hw are failing to enable lpsp configuration due to PG3 was left on
due to valid usgae count of POWER_DOMAIN_AUDIO.
It is not required to get POWER_DOMAIN_AUDIO ref-count when enabling
a crtc, it should be always i915_audio_component request to get/put
AUDIO_POWER_DOMAIN.
Cc: sta...@vger.kern
== Series Details ==
Series: series starting with [01/36] drm/i915: Handle very early engine
initialisation failure (rev2)
URL : https://patchwork.freedesktop.org/series/77857/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8560_full -> Patchwork_17828_full
===
== Series Details ==
Series: drm/i915: Add Plane color encoding support for YCBCR_BT2020 (rev6)
URL : https://patchwork.freedesktop.org/series/75660/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8560_full -> Patchwork_17827_full
===
== Series Details ==
Series: drm/i915: lpsp with hdmi/dp outputs
URL : https://patchwork.freedesktop.org/series/77866/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8561 -> Patchwork_17829
Summary
---
**SUCCESS**
Chris Wilson writes:
> If we fail during engine setup, we may leave some engines not yet setup.
> During the error cleanup, we have to be careful not to try and use the
> uninitialise engines before discarding them.
>
> [ 16.136152] RIP: 0010:__flush_work+0x198/0x1b0
> [ 16.136168] Code: ff f
Quoting Patchwork (2020-06-01 12:00:40)
> == Series Details ==
>
> Series: series starting with [01/36] drm/i915: Handle very early engine
> initialisation failure (rev2)
> URL : https://patchwork.freedesktop.org/series/77857/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from
Chris Wilson writes:
> Ever noticed that our interrupt handlers are where we spend most of our
> time on a busy system? In part this is unavoidable as each interrupt
> requires to poll and reset several registers, but we can try and so as
> efficiently as possible.
>
> Function
Quoting Mika Kuoppala (2020-06-01 12:49:49)
> Chris Wilson writes:
>
> > Ever noticed that our interrupt handlers are where we spend most of our
> > time on a busy system? In part this is unavoidable as each interrupt
> > requires to poll and reset several registers, but we can try and so as
> >
> -Original Message-
> From: Kadiyala, Kishore
> Sent: Monday, June 1, 2020 1:06 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Kadiyala, Kishore ; Ville Syrjala
> ; Nikula, Jani ;
> Shankar,
> Uma
> Subject: [PATCH v6] drm/i915: Add Plane color encoding support for
> YCBCR_BT2020
>
Quoting Chris Wilson (2020-06-01 13:00:43)
> Quoting Mika Kuoppala (2020-06-01 12:49:49)
> > Chris Wilson writes:
> >
> > > Ever noticed that our interrupt handlers are where we spend most of our
> > > time on a busy system? In part this is unavoidable as each interrupt
> > > requires to poll and
Ever noticed that our interrupt handlers are where we spend most of our
time on a busy system? In part this is unavoidable as each interrupt
requires to poll and reset several registers, but we can try and do so as
efficiently as possible.
Function old new
Chris Wilson writes:
> Sometimes an engine might need to keep forcewake active while it is busy
> submitting requests for a particular workaround. Track such nuisance
> with engine->fw_domain.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_en
Chris Wilson writes:
> Our forcewake utilisation is split into categories: automatic and
> manual. Around bare register reads, we look up the right forcewake
> domain and automatically acquire and release [upon a timer] the
> forcewake domain. For other access, where we know we require the
> forc
> -Original Message-
> From: Intel-gfx On Behalf Of
> Anshuman Gupta
> Sent: Monday, June 1, 2020 3:45 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: sta...@vger.kernel.org
> Subject: [Intel-gfx] [RFC] drm/i915: lpsp with hdmi/dp outputs
>
> Gen12 hw are failing to enable lpsp configura
Chris Wilson writes:
> Ever noticed that our interrupt handlers are where we spend most of our
> time on a busy system? In part this is unavoidable as each interrupt
> requires to poll and reset several registers, but we can try and do so as
> efficiently as possible.
>
> Function
== Series Details ==
Series: drm/i915: Trim the ironlake+ irq handler
URL : https://patchwork.freedesktop.org/series/77871/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8562 -> Patchwork_17830
Summary
---
**FAILURE*
From: Sean Paul
If the backlight is updated while the panel is being enabled, the value
from userspace (which is stored in panel->backlight.device->props.brightness)
can be replaced by the hardware's minimum level. There's really no good
way to tell if this is happening in enable_backlight() sinc
Hi Stanislav,
url:
https://github.com/0day-ci/linux/commits/Stanislav-Lisovskiy/drm-i915-Fix-wrong-CDCLK-adjustment-changes/20200526-180642
base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
config: i386-randconfig-m021-20200531 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-13) 9.
Ever noticed that our interrupt handlers are where we spend most of our
time on a busy system? In part this is unavoidable as each interrupt
requires to poll and reset several registers, but we can try and do so as
efficiently as possible.
Function old new
On Mon, Jun 01, 2020 at 03:45:16PM +0530, Anshuman Gupta wrote:
> Gen12 hw are failing to enable lpsp configuration due to PG3 was left on
> due to valid usgae count of POWER_DOMAIN_AUDIO.
> It is not required to get POWER_DOMAIN_AUDIO ref-count when enabling
> a crtc, it should be always i915_audi
On Mon, Jun 01, 2020 at 05:01:08PM +0300, Dan Carpenter wrote:
> Hi Stanislav,
>
> url:
> https://github.com/0day-ci/linux/commits/Stanislav-Lisovskiy/drm-i915-Fix-wrong-CDCLK-adjustment-changes/20200526-180642
> base: git://anongit.freedesktop.org/drm/drm-tip drm-tip
> config: i386-randconf
On Mon, Jun 01, 2020 at 10:59:29AM +0300, Lisovskiy, Stanislav wrote:
> On Fri, May 29, 2020 at 08:11:43AM +0300, Ville Syrjälä wrote:
> > On Thu, May 28, 2020 at 10:58:52PM +0300, Lisovskiy, Stanislav wrote:
> > > On Thu, May 28, 2020 at 10:38:52PM +0300, Lisovskiy, Stanislav wrote:
> > > > On Wed
Chris Wilson writes:
> As we rewrite the batches on the fly to implement the non-preemptible
> lock, we need to tell Tigerlake to read the batch afresh each time.
> Amusingly, the disable is a part of an arb-check, so we have to be
> careful not to include the arbitration point inside our unpreem
== Series Details ==
Series: drm/i915: lpsp with hdmi/dp outputs
URL : https://patchwork.freedesktop.org/series/77866/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8561_full -> Patchwork_17829_full
Summary
---
**FAI
== Series Details ==
Series: drm/i915/panel: Reduce race window between bl_update_status and
bl_enable
URL : https://patchwork.freedesktop.org/series/77873/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bca376137784 drm/i915/panel: Reduce race window between bl_update_status a
== Series Details ==
Series: drm/i915/panel: Reduce race window between bl_update_status and
bl_enable
URL : https://patchwork.freedesktop.org/series/77873/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8565 -> Patchwork_17831
=
Quoting Mika Kuoppala (2020-06-01 15:56:55)
> Chris Wilson writes:
>
> > As we rewrite the batches on the fly to implement the non-preemptible
> > lock, we need to tell Tigerlake to read the batch afresh each time.
> > Amusingly, the disable is a part of an arb-check, so we have to be
> > careful
== Series Details ==
Series: drm/i915: Trim the ironlake+ irq handler (rev2)
URL : https://patchwork.freedesktop.org/series/77871/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8565 -> Patchwork_17832
Summary
---
**S
Allow batch buffers to read their own _local_ cumulative HW runtime of
their logical context.
Fixes: 0f2f39758341 ("drm/i915: Add gen9 BCS cmdparsing")
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
Cc: # v5.4+
---
drivers/gpu/drm/i915/i915_cmd_parser.c | 4
1 file changed, 4 insertions(+)
== Series Details ==
Series: drm/i915: Whitelist context-local timestamp in the gen9 cmdparser
URL : https://patchwork.freedesktop.org/series/77877/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8565 -> Patchwork_17833
Summ
On Wed, May 27, 2020 at 11:53:32AM +0200, Daniel Vetter wrote:
> Only when vblanks are supported ofc.
>
> Some drivers do this already, but most unfortunately missed it. This
> opens up bugs after driver load, before the crtc is enabled for the
> first time. syzbot spotted this when loading vkms a
Previous patch didn't take into account all pipes
but only those in state, which could cause wrong
CDCLK conclcusions and calculations.
Also there was a severe issue with min_cdclk being
assigned to 0 every compare cycle.
Too bad this was found by me only after merge.
This could be also causing th
On Sat, 2020-05-30 at 04:56 +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/tgl: Update TC DP vswing table
> URL : https://patchwork.freedesktop.org/series/77806/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_8557_full -> Patchwork_17824_full
> ==
Chris Wilson writes:
> Allow batch buffers to read their own _local_ cumulative HW runtime of
> their logical context.
>
> Fixes: 0f2f39758341 ("drm/i915: Add gen9 BCS cmdparsing")
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Cc: # v5.4+
Reviewed-by: Mika Kuoppala
> ---
> drivers/gp
An important property for multi-client systems is that each client gets
a 'fair' allotment of system time. (Where fairness is at the whim of the
context properties, such as priorities.) This test forks N independent
clients (albeit they happen to share a single vm), and does an equal
amount of work
== Series Details ==
Series: drm/i915: Fix wrong CDCLK adjustment changes (rev2)
URL : https://patchwork.freedesktop.org/series/77654/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8566 -> Patchwork_17834
Summary
---
An important property for multi-client systems is that each client gets
a 'fair' allotment of system time. (Where fairness is at the whim of the
context properties, such as priorities.) This test forks N independent
clients (albeit they happen to share a single vm), and does an equal
amount of work
On Tue, 2020-05-12 at 20:41 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> IBX supports vswing level 3 and pre-emphasis level 3. Don't
> limit it to level 2 for those.
Matches
https://01.org/linuxgraphics/documentation/driver-documentation-prms/2010-intel-core-processor-family
Reviewed-
If we only submit the first port, leaving the second empty yet have
ready requests pending in the queue, use that to set the timeslicing
priority (i.e. the priority at which we will decided to enabling
timeslicing and evict the currently active context if the queue is of
equal priority after its qu
Use the plain msec_to_jiffies() rather than the _timeout variant so we
round down and do not add an extra jiffy to our interval. For example,
with timeslicing we do not want to err on the longer side as any
fairness depends on catching hogging contexts on the GPU. Bring on
CFS.
Signed-off-by: Chri
We may choose not to submit for a number of reasons, yet not fill both
ELSP. In which case we must start timeslicing (there will be no ACK
event on which to hook the start) if the queue would benefit from the
currently active context being evicted.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm
On Mon, Jun 01, 2020 at 10:49:54AM +0300, Lisovskiy, Stanislav wrote:
> On Fri, May 29, 2020 at 04:57:38PM -0700, Manasi Navare wrote:
> > On Tue, May 26, 2020 at 12:48:52PM +0300, Stanislav Lisovskiy wrote:
> > > Previous patch didn't take into account all pipes
> > > but only those in state, whic
On Mon, Jun 01, 2020 at 08:30:58PM +0300, Stanislav Lisovskiy wrote:
> Previous patch didn't take into account all pipes
> but only those in state, which could cause wrong
> CDCLK conclcusions and calculations.
> Also there was a severe issue with min_cdclk being
> assigned to 0 every compare cycle
== Series Details ==
Series: series starting with [1/3] drm/i915: Trim set_timer_ms() intervals
URL : https://patchwork.freedesktop.org/series/77888/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8567 -> Patchwork_17835
Sum
An important property for multi-client systems is that each client gets
a 'fair' allotment of system time. (Where fairness is at the whim of the
context properties, such as priorities.) This test forks N independent
clients (albeit they happen to share a single vm), and does an equal
amount of work
== Series Details ==
Series: drm/i915/panel: Reduce race window between bl_update_status and
bl_enable
URL : https://patchwork.freedesktop.org/series/77873/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8565_full -> Patchwork_17831_full
===
fake_lmem_start does not need to be mutable via module param sysfs. It's
only used during driver probe.
Fixes: 1629224324b6 ("drm/i915/lmem: add the fake lmem region")
Cc: Matthew Auld
Cc: Joonas Lahtinen
Cc: Chris Wilson
Reviewed-by: Rodrigo Vivi
Signed-off-by: Jani Nikula
---
drivers/gpu/d
Only support runtime changes through the debugfs.
i915.verbose_state_checks remains an exception, and is not exposed via
debugfs.
This depends on IGT having been updated to use the debugfs for modifying
the parameters.
Cc: Juha-Pekka Heikkilä
Cc: Venkata Sandeep Dhanalakota
Reviewed-by: Juha-P
The parameter only makes sense as a module parameter only.
Fixes: c43c5a8818d4 ("drm/i915/params: add i915 parameters to debugfs")
Cc: Juha-Pekka Heikkilä
Cc: Venkata Sandeep Dhanalakota
Reviewed-by: Juha-Pekka Heikkila
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/params: don't expose
inject_probe_failure in debugfs
URL : https://patchwork.freedesktop.org/series/77889/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
acf490748fe6 drm/i915/params: don't expose inject_probe_
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/params: don't expose
inject_probe_failure in debugfs
URL : https://patchwork.freedesktop.org/series/77889/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit wo
== Series Details ==
Series: drm/i915: Trim the ironlake+ irq handler (rev2)
URL : https://patchwork.freedesktop.org/series/77871/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8565_full -> Patchwork_17832_full
Summary
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