Hi,
This patch is just changing the order of includes and couple of vars moved.
That is the case when it is pure 100% that it is false positive.
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
_
Asynchronous waits and signaling form a traditional semaphore with all
the usual ordering problems with taking multiple locks. If we want to
add more than one wait on a shared resource by the GPU, we must ensure
that all the associated timelines are advanced atomically, ergo we must
lock all the ti
One more list iterator variant, for when we want to unwind from inside
one list iterator with the intention of restarting from the current
entry as the new head of the list.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_utils.h | 6 ++
1 file changed, 6 insertions(+)
diff --git
Leave the error propagation in place, but limit the warnings to only
show up in CI if the unlikely errors are hit.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 3 +--
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 3 +--
drivers/gpu/drm/i915/gem/i915_gem_shm
Although we may chide userspace for reusing the same batches
concurrently from multiple threads, at the same time we must be very
careful to only execute the batch and its relocations as supplied by the
user. If we are not careful, we may allow another thread to rewrite the
current batch with its o
Since we have reduced the relocations paths to just use the async GPU,
we can lift the request allocation to the start of the relocations.
Knowing that we use one request for all relocations will simplify
tracking the relocation fence.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_ge
If the real target for a proxy fence is known at the time we are
attaching our awaits, use the real target in preference to hooking up to
the proxy. If use the real target instead, we can optimize the awaits,
e.g. if it along the same engine, we can order the submission and avoid
the wait-for-compl
Reduce the 3 relocation patches down to the single path that accommodates
all. The primary motivation for this is to guard the relocations with a
natural fence (derived from the i915_request used to write the
relocation from the GPU).
The tradeoff in using async gpu relocations is that it increase
In order to keep userptr distinct from ggtt mmaps in the eyes of
lockdep, we need to avoid marking those userptr vma as PIN_GLOBAL. (So
long as we comply with only using them as local PIN_USER!)
References: https://gitlab.freedesktop.org/drm/intel/-/issues/1880
Signed-off-by: Chris Wilson
---
dr
Often we need to create a fence for a future event that has not yet been
associated with a fence. We can store a proxy fence, a placeholder, in
the timeline and replace it later when the real fence is known. Any
listeners that attach to the proxy fence will automatically be signaled
when the real f
If there are no internal levels and the user priority-shift is zero, we
can help the compiler eliminate some dead code:
Function old new delta
start_timeslice 169 154 -15
__execlists_submission_tasklet 4696
Reduce the irq_work llist for attaching the callbacks to the signal for
both smaller structs (two fewer pointers!) and simpler [debug] code:
Function old new delta
irq_execute_cb35 34 -1
__igt_breadcrumbs_smoketest
Since the worker may rearm, we currently are only guaranteed to flush
the work if we cancel the timer. If the work was running at the time we
try and cancel it, we will wait for it to complete, but it may leave
items in the pool and requeue the work. If we rearrange the immediate
discard of the poo
I have seen those failures in other patches as well, i.e before my patches
landed.
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
From: Chris Wilson
Sent: Saturday, May 23, 2020 2:18:44 A
== Series Details ==
Series: series starting with [01/12] drm/i915/gt: Stop cross-polluting
PIN_GLOBAL with PIN_USER with no-ppgtt
URL : https://patchwork.freedesktop.org/series/77627/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e73ba84bc40f drm/i915/gt: Stop cross-polluting
Quoting Lisovskiy, Stanislav (2020-05-25 09:00:33)
> I have seen those failures in other patches as well, i.e before my patches
> landed.
Look again. CI is very clear, as is the bisect and revert.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freede
== Series Details ==
Series: series starting with [01/12] drm/i915/gt: Stop cross-polluting
PIN_GLOBAL with PIN_USER with no-ppgtt
URL : https://patchwork.freedesktop.org/series/77627/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each
Ok, lets check - in worst case I just need to find a GLK machine and bisect.
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
From: Chris Wilson
Sent: Monday, May 25, 2020 11:03:36 AM
To: Li
This reverts
cac91e671ad5 ("drm/i915: Fix includes and local vars order")
82ea174dc542 ("drm/i915: Remove unneeded hack now for CDCLK")
cd1915460861 ("drm/i915: Adjust CDCLK accordingly to our DBuf bw needs")
Cc: Stanislav Lisovskiy
Cc: Manasi Navare
Cc: "Ville Syrjälä"
---
drivers/gpu/drm/i91
Quoting Lisovskiy, Stanislav (2020-05-25 09:07:03)
> Ok, lets check - in worst case I just need to find a GLK machine and bisect.
Also there is https://gitlab.freedesktop.org/drm/intel/-/issues/1919 on
icl.
-Chris
___
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On Mon, May 25, 2020 at 09:07:31AM +0100, Chris Wilson wrote:
> This reverts
> cac91e671ad5 ("drm/i915: Fix includes and local vars order")
> 82ea174dc542 ("drm/i915: Remove unneeded hack now for CDCLK")
> cd1915460861 ("drm/i915: Adjust CDCLK accordingly to our DBuf bw needs")
>
> Cc: Stanislav L
That one is different patch and moreover could be even won't fix.
If we fail to disable qgv points - we fail. Could remove the message though
if it floods the logs too much.
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
_
Quoting Lisovskiy, Stanislav (2020-05-25 09:07:54)
> On Mon, May 25, 2020 at 09:07:31AM +0100, Chris Wilson wrote:
> > This reverts
> > cac91e671ad5 ("drm/i915: Fix includes and local vars order")
> > 82ea174dc542 ("drm/i915: Remove unneeded hack now for CDCLK")
> > cd1915460861 ("drm/i915: Adjust
On Mon, May 25, 2020 at 09:16:54AM +0100, Chris Wilson wrote:
> Quoting Lisovskiy, Stanislav (2020-05-25 09:07:54)
> > On Mon, May 25, 2020 at 09:07:31AM +0100, Chris Wilson wrote:
> > > This reverts
> > > cac91e671ad5 ("drm/i915: Fix includes and local vars order")
> > > 82ea174dc542 ("drm/i915: R
== Series Details ==
Series: series starting with [01/12] drm/i915/gt: Stop cross-polluting
PIN_GLOBAL with PIN_USER with no-ppgtt
URL : https://patchwork.freedesktop.org/series/77627/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8529 -> Patchwork_17767
=
== Series Details ==
Series: drm/i915: Revert CDCLK changes to unbreak geminilake
URL : https://patchwork.freedesktop.org/series/77628/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c692f23a099e drm/i915: Revert CDCLK changes to unbreak geminilake
-:10: ERROR:GIT_COMMIT_ID: Ple
== Series Details ==
Series: drm/i915: Revert CDCLK changes to unbreak geminilake
URL : https://patchwork.freedesktop.org/series/77628/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8529 -> Patchwork_17768
Summary
---
== Series Details ==
Series: drm/i915: Revert CDCLK changes to unbreak geminilake
URL : https://patchwork.freedesktop.org/series/77628/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8529_full -> Patchwork_17768_full
Summary
Before we return control to the system, and letting it reuse all the
pages being accessed by HW, we must disable the HW. At the moment, we
dare not reset the GPU if it will clobber the display, but once we know
the display has been disabled, we can proceed with the reset as we
shutdown the module.
Avoid a NULL dereference for a mismatched encoder type, hit when
probing state for all encoders.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1892
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_dp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/g
Chris Wilson writes:
> Since the worker may rearm, we currently are only guaranteed to flush
> the work if we cancel the timer. If the work was running at the time we
> try and cancel it, we will wait for it to complete, but it may leave
> items in the pool and requeue the work. If we rearrange t
Chris Wilson writes:
> Leave the error propagation in place, but limit the warnings to only
> show up in CI if the unlikely errors are hit.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 3 +--
> drivers/gpu/drm/i915/gem/i9
== Series Details ==
Series: drm/i915/gt: Force the GT reset on shutdown
URL : https://patchwork.freedesktop.org/series/77633/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8529 -> Patchwork_17769
Summary
---
**FAILU
Quoting Mika Kuoppala (2020-05-25 14:51:18)
> Chris Wilson writes:
>
> > Since the worker may rearm, we currently are only guaranteed to flush
> > the work if we cancel the timer. If the work was running at the time we
> > try and cancel it, we will wait for it to complete, but it may leave
> > i
Before we return control to the system, and letting it reuse all the
pages being accessed by HW, we must disable the HW. At the moment, we
dare not reset the GPU if it will clobber the display, but once we know
the display has been disabled, we can proceed with the reset as we
shutdown the module.
== Series Details ==
Series: series starting with [01/23] Revert "drm/i915/gem: Drop relocation
slowpath".
URL : https://patchwork.freedesktop.org/series/77472/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8511_full -> Patchwork_17730_full
===
Since the worker may rearm, we currently are only guaranteed to flush
the work if we cancel the timer. If the work was running at the time we
try and cancel it, we will wait for it to complete, but it may leave
items in the pool and requeue the work. If we rearrange the immediate
discard of the poo
Leave the error propagation in place, but limit the warnings to only
show up in CI if the unlikely errors are hit.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 3 +--
drivers/gpu/drm/i915/gem/i915_gem_phys.c | 3 +--
drivers/g
== Series Details ==
Series: drm/i915/display: Only query DP state of a DDI encoder
URL : https://patchwork.freedesktop.org/series/77635/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8530 -> Patchwork_17770
Summary
---
== Series Details ==
Series: drm/i915/gt: Force the GT reset on shutdown (rev2)
URL : https://patchwork.freedesktop.org/series/77633/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8530 -> Patchwork_17771
Summary
---
Before we return control to the system, and letting it reuse all the
pages being accessed by HW, we must disable the HW. At the moment, we
dare not reset the GPU if it will clobber the display, but once we know
the display has been disabled, we can proceed with the reset as we
shutdown the module.
On Tue, May 12, 2020 at 11:00 AM Daniel Vetter wrote:
>
> If the scheduler rt thread gets stuck on a mutex that we're holding
> while waiting for gpu workloads to complete, we have a problem.
>
> Add dma-fence annotations so that lockdep can check this for us.
>
> I've tried to quite carefully rev
Chris Wilson writes:
> In order to keep userptr distinct from ggtt mmaps in the eyes of
> lockdep, we need to avoid marking those userptr vma as PIN_GLOBAL. (So
> long as we comply with only using them as local PIN_USER!)
>
> References: https://gitlab.freedesktop.org/drm/intel/-/issues/1880
> Si
On Tue, May 12, 2020 at 11:04 AM Chris Wilson wrote:
>
> Quoting Daniel Vetter (2020-05-12 09:59:29)
> > Design is similar to the lockdep annotations for workers, but with
> > some twists:
> >
> > - We use a read-lock for the execution/worker/completion side, so that
> > this explicit annotation
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Cancel the flush worker more
thoroughly
URL : https://patchwork.freedesktop.org/series/77637/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
31e98f3454a9 drm/i915/gt: Cancel the flush worker more thoroughly
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Cancel the flush worker more
thoroughly
URL : https://patchwork.freedesktop.org/series/77637/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8532 -> Patchwork_17772
== Series Details ==
Series: drm/i915/gt: Force the GT reset on shutdown (rev3)
URL : https://patchwork.freedesktop.org/series/77633/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8532 -> Patchwork_17773
Summary
---
== Series Details ==
Series: drm/i915/display: Only query DP state of a DDI encoder
URL : https://patchwork.freedesktop.org/series/77635/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8530_full -> Patchwork_17770_full
Summa
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/gt: Cancel the flush worker more
thoroughly
URL : https://patchwork.freedesktop.org/series/77637/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8532_full -> Patchwork_17772_full
==
== Series Details ==
Series: drm/i915/gt: Force the GT reset on shutdown (rev3)
URL : https://patchwork.freedesktop.org/series/77633/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8532_full -> Patchwork_17773_full
Summary
-
Once a virtual engine has been bound to a sibling, it will remain bound
until we finally schedule out the last active request. We can not rebind
the context to a new sibling while it is inflight as the context save
will conflict, hence we wait. As we cannot then use any other sibliing
while the con
When we push a virtual request onto the HW, we update the rq->engine to
point to the physical engine. A request that is then submitted by the
user that waits upon the virtual engine, but along the physical engine
in use, will then see that it is due to be submitted to the same engine
and take a sho
Rather than going back and forth between the rb_node entry and the
virtual_engine type, store the ve local and reuse it. As the
container_of conversion from rb_node to virtual_engine requires a
variable offset, performing that conversion just once shaves off a bit
of code.
v2: Keep a single virtua
Having recognised that we do not change the sibling until we schedule
out, we can then defer the decision to resubmit the virtual engine from
the unwind of the active queue to scheduling out of the virtual context.
By keeping the unwind order intact on the local engine, we can preserve
data depend
== Series Details ==
Series: series starting with [1/4] drm/i915/gt: Do not schedule normal requests
immediately along virtual
URL : https://patchwork.freedesktop.org/series/77639/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8534 -> Patchwork_17774
=
== Series Details ==
Series: series starting with [1/4] drm/i915/gt: Do not schedule normal requests
immediately along virtual
URL : https://patchwork.freedesktop.org/series/77639/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8534_full -> Patchwork_17774_full
===
Hi
[This is an automated email]
This commit has been processed because it contains a "Fixes:" tag
fixing commit: 6d06779e8672 ("drm/i915: Load balancing across a virtual
engine").
The bot has tested the following trees: v5.6.14, v5.4.42.
v5.6.14: Build OK!
v5.4.42: Failed to apply! Possible de
On 25-05-2020 05:09, Chris Wilson wrote:
drivers/gpu/drm/i915/display/intel_dsb.c:177 intel_dsb_reg_write() warn:
variable dereferenced before check 'dsb' (see line 175)
Fixes: afeda4f3b1c8 ("drm/i915/dsb: Pre allocate and late cleanup of cmd
buffer")
Signed-off-by: Chris Wilson
Cc: Ville Sy
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