== Series Details ==
Series: drm/i915/selftests: Add tiled blits selftest (rev2)
URL : https://patchwork.freedesktop.org/series/76746/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0cf43fdf0ac0 drm/i915/selftests: Add tiled blits selftest
-:603: WARNING:LINE_SPACING: Missing a
== Series Details ==
Series: drm/i915/selftests: Add tiled blits selftest (rev2)
URL : https://patchwork.freedesktop.org/series/76746/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8399 -> Patchwork_17525
Summary
---
Quoting Chris Wilson (2020-04-30 07:49:57)
> From: Zbigniew Kempczyński
>
> Extend coverage of the blitter client by exercising conversion to and
> from tiled sources. In the process we perform spot checks to verify that
> the tiling/detiling is being applied correctly, along with position
> inva
== Series Details ==
Series: series starting with [CI,1/6] drm/i915/gt: Always enable busy-stats for
execlists
URL : https://patchwork.freedesktop.org/series/76744/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8395_full -> Patchwork_17522_full
===
On Thu, Apr 23, 2020 at 10:58:55AM +0300, Stanislav Lisovskiy wrote:
> Future platforms require per-crtc SAGV evaluation
> and serializing global state when those are changed
> from different commits.
>
> v2: - Add has_sagv check to intel_crtc_can_enable_sagv
> so that it sets bit in reject
On Thu, Apr 30, 2020 at 12:09:22PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 23, 2020 at 10:58:55AM +0300, Stanislav Lisovskiy wrote:
> > Future platforms require per-crtc SAGV evaluation
> > and serializing global state when those are changed
> > from different commits.
> >
> > v2: - Add has_sagv
On Thu, Apr 23, 2020 at 10:58:56AM +0300, Stanislav Lisovskiy wrote:
> We need to calculate SAGV mask also in a non-modeset
> commit, however currently active_pipes are only calculated
> for modesets in global atomic state, thus now we will be
> tracking those also in bw_state in order to be able t
On Thu, Apr 30, 2020 at 12:13:35PM +0300, Lisovskiy, Stanislav wrote:
> On Thu, Apr 30, 2020 at 12:09:22PM +0300, Ville Syrjälä wrote:
> > On Thu, Apr 23, 2020 at 10:58:55AM +0300, Stanislav Lisovskiy wrote:
> > > Future platforms require per-crtc SAGV evaluation
> > > and serializing global state
Slow devices with low CS frequencies may take longer than expected
between the PIPECONTROL timestamp and the OA timestamp, hovering just
above the arbitrary 500ns threshold. The discrepancy seems relatively
stable, just the device taking longer than anticipated without affecting
the results, so mak
On Thu, Apr 30, 2020 at 12:25:38PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 30, 2020 at 12:13:35PM +0300, Lisovskiy, Stanislav wrote:
> > On Thu, Apr 30, 2020 at 12:09:22PM +0300, Ville Syrjälä wrote:
> > > On Thu, Apr 23, 2020 at 10:58:55AM +0300, Stanislav Lisovskiy wrote:
> > > > Future platfor
On Thu, Apr 30, 2020 at 12:52:42PM +0300, Lisovskiy, Stanislav wrote:
> On Thu, Apr 30, 2020 at 12:25:38PM +0300, Ville Syrjälä wrote:
> > On Thu, Apr 30, 2020 at 12:13:35PM +0300, Lisovskiy, Stanislav wrote:
> > > On Thu, Apr 30, 2020 at 12:09:22PM +0300, Ville Syrjälä wrote:
> > > > On Thu, Apr 2
On Thu, Apr 30, 2020 at 12:21:04PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 23, 2020 at 10:58:56AM +0300, Stanislav Lisovskiy wrote:
> > We need to calculate SAGV mask also in a non-modeset
> > commit, however currently active_pipes are only calculated
> > for modesets in global atomic state, thus
On Thu, Apr 30, 2020 at 01:08:20PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 30, 2020 at 12:52:42PM +0300, Lisovskiy, Stanislav wrote:
> > On Thu, Apr 30, 2020 at 12:25:38PM +0300, Ville Syrjälä wrote:
> > > On Thu, Apr 30, 2020 at 12:13:35PM +0300, Lisovskiy, Stanislav wrote:
> > > > On Thu, Apr 3
On Thu, Apr 30, 2020 at 01:05:15PM +0300, Lisovskiy, Stanislav wrote:
> On Thu, Apr 30, 2020 at 12:21:04PM +0300, Ville Syrjälä wrote:
> > On Thu, Apr 23, 2020 at 10:58:56AM +0300, Stanislav Lisovskiy wrote:
> > > We need to calculate SAGV mask also in a non-modeset
> > > commit, however currently
On Thu, Apr 30, 2020 at 01:14:57PM +0300, Lisovskiy, Stanislav wrote:
> On Thu, Apr 30, 2020 at 01:08:20PM +0300, Ville Syrjälä wrote:
> > On Thu, Apr 30, 2020 at 12:52:42PM +0300, Lisovskiy, Stanislav wrote:
> > > On Thu, Apr 30, 2020 at 12:25:38PM +0300, Ville Syrjälä wrote:
> > > > On Thu, Apr 3
On Thu, Apr 30, 2020 at 01:32:17PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 30, 2020 at 01:05:15PM +0300, Lisovskiy, Stanislav wrote:
> > On Thu, Apr 30, 2020 at 12:21:04PM +0300, Ville Syrjälä wrote:
> > > On Thu, Apr 23, 2020 at 10:58:56AM +0300, Stanislav Lisovskiy wrote:
> > > > We need to cal
On Thu, Apr 30, 2020 at 01:47:02PM +0300, Lisovskiy, Stanislav wrote:
> On Thu, Apr 30, 2020 at 01:32:17PM +0300, Ville Syrjälä wrote:
> > On Thu, Apr 30, 2020 at 01:05:15PM +0300, Lisovskiy, Stanislav wrote:
> > > On Thu, Apr 30, 2020 at 12:21:04PM +0300, Ville Syrjälä wrote:
> > > > On Thu, Apr 2
On Thu, Apr 30, 2020 at 01:55:59PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 30, 2020 at 01:47:02PM +0300, Lisovskiy, Stanislav wrote:
> > On Thu, Apr 30, 2020 at 01:32:17PM +0300, Ville Syrjälä wrote:
> > > On Thu, Apr 30, 2020 at 01:05:15PM +0300, Lisovskiy, Stanislav wrote:
> > > > On Thu, Apr 3
In preparation for making eb_vma bigger and heavy to run inn parallel,
we need to stop apply an in-place swap() to reorder around ww_mutex
deadlocks. Keep the array intact and reorder the locks using a dedicated
list.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c
Allocate a few dma fence context id that we can use to associate async work
[for the CPU] launched on behalf of this context. For extra fun, we allow
a configurable concurrency width.
A current example would be that we spawn an unbound worker for every
userptr get_pages. In the future, we wish to
Since the introduction of 'soft-rc6', we aim to park the device quickly
and that results in frequent idling of the whole device. Currently upon
idling we free the batch buffer pool, and so this renders the cache
ineffective for many workloads. If we want to have an effective cache of
recently alloc
Currently, if an error is raised we always call the cleanup locally
[and skip the main work callback]. However, some future users may need
to take a mutex to cleanup and so we cannot immediately execute the
cleanup as we may still be in interrupt context.
With the execute-immediate flag, for most
It is reasonably common for userspace (even modern drivers like iris) to
reuse an active address for a new buffer. This would cause the
application to stall under its mutex (originally struct_mutex) until the
old batches were idle and it could synchronously remove the stale PTE.
However, we can que
As we only restore the default context state upon banning a context, we
only need enough of the state to run the ring and nothing more. That is
we only need our bare protocontext.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
Cc: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel
For our gpu relocs, on the older gen 4 and 5 devices, we must use a
privileged buffer for MI_STORE_DWORD_IMM. This also presumes that we
operate from the global GTT, for consistency we should tell
i915_vma_pin() that it will be used with the global address. While there
is only the single GTT availa
It is illegal to wait on an another vma while holding the vm->mutex, as
that easily leads to ABBA deadlocks (we wait on a second vma that waits
on us to release the vm->mutex). So while the vm->mutex exists, move the
waiting outside of the lock into the async binding pipeline.
Signed-off-by: Chris
Sometimes we have to be very careful not to allocate underneath a mutex
(or spinlock) and yet still want to track activity. Enter
i915_active_acquire_for_context(). This raises the activity counter on
i915_active prior to use and ensures that the fence-tree contains a slot
for the context.
Signed-
On Thu, Apr 30, 2020 at 02:07:02PM +0300, Lisovskiy, Stanislav wrote:
> On Thu, Apr 30, 2020 at 01:55:59PM +0300, Ville Syrjälä wrote:
> > On Thu, Apr 30, 2020 at 01:47:02PM +0300, Lisovskiy, Stanislav wrote:
> > > On Thu, Apr 30, 2020 at 01:32:17PM +0300, Ville Syrjälä wrote:
> > > > On Thu, Apr 3
Quoting Chris Wilson (2020-04-30 12:18:18)
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index cb43381b0d37..da081401142e 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -219,6 +219,8 @@ int i915_gem
On Thu, Apr 30, 2020 at 02:22:02PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 30, 2020 at 02:07:02PM +0300, Lisovskiy, Stanislav wrote:
> > On Thu, Apr 30, 2020 at 01:55:59PM +0300, Ville Syrjälä wrote:
> > > On Thu, Apr 30, 2020 at 01:47:02PM +0300, Lisovskiy, Stanislav wrote:
> > > > On Thu, Apr 3
On Thu, Apr 30, 2020 at 02:29:51PM +0300, Lisovskiy, Stanislav wrote:
> On Thu, Apr 30, 2020 at 02:22:02PM +0300, Ville Syrjälä wrote:
> > On Thu, Apr 30, 2020 at 02:07:02PM +0300, Lisovskiy, Stanislav wrote:
> > > On Thu, Apr 30, 2020 at 01:55:59PM +0300, Ville Syrjälä wrote:
> > > > On Thu, Apr 3
> -Original Message-
> From: Ville Syrjala
> Sent: Thursday, April 30, 2020 12:25 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Gupta, Anshuman ; Shankar, Uma
>
> Subject: [PATCH 1/3] drm/i915: Nuke mode.vrefresh usage
>
> From: Ville Syrjälä
>
> mode.vrefresh is rounded to the near
> -Original Message-
> From: Ville Syrjala
> Sent: Thursday, April 30, 2020 12:25 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Gupta, Anshuman ; Shankar, Uma
>
> Subject: [PATCH 2/3] drm/i915: Rename variables to be consistent with bspec
>
> From: Ville Syrjälä
>
> Since the code s
On Thu, Apr 30, 2020 at 02:40:37PM +0300, Ville Syrjälä wrote:
> On Thu, Apr 30, 2020 at 02:29:51PM +0300, Lisovskiy, Stanislav wrote:
> > On Thu, Apr 30, 2020 at 02:22:02PM +0300, Ville Syrjälä wrote:
> > > On Thu, Apr 30, 2020 at 02:07:02PM +0300, Lisovskiy, Stanislav wrote:
> > > > On Thu, Apr 3
On Wed, Apr 29, 2020 at 08:11:04PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2020-04-29 19:54:57)
> > From: Ville Syrjälä
> >
> > All these ROUNDIND_FACTORs and whatnot are making this thing hard to
> > read. Get rid of them. And let's massage some of the fractions to
> > give us less q
== Series Details ==
Series: series starting with [1/9] drm/i915/gt: Stop holding onto the
pinned_default_state
URL : https://patchwork.freedesktop.org/series/76771/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0e9eeaba9f3e drm/i915/gt: Stop holding onto the pinned_default_st
> -Original Message-
> From: Ville Syrjala
> Sent: Thursday, April 30, 2020 12:25 AM
> To: intel-gfx@lists.freedesktop.org
> Cc: Gupta, Anshuman ; Shankar, Uma
>
> Subject: [PATCH 3/3] drm/i915: Streamline the artihmetic
>
> From: Ville Syrjälä
>
> All these ROUNDIND_FACTORs and what
== Series Details ==
Series: series starting with [1/9] drm/i915/gt: Stop holding onto the
pinned_default_state
URL : https://patchwork.freedesktop.org/series/76771/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8401 -> Patchwork_17526
Quoting Zhenyu Wang (2020-04-26 05:46:19)
> On 2020.04.22 13:12:30 +0800, Zhenyu Wang wrote:
> >
> > Hi,
> >
> > Here's current gvt-next. This removes left non-upstream xen support bits
> > which will be kept out of tree instead. And several guest context shadow
> > optimizations from Yan.
> >
>
: Update DRIVER_DATE to 20200417 (2020-04-17 09:35:00 +0300)
are available in the Git repository at:
git://anongit.freedesktop.org/drm/drm-intel tags/drm-intel-next-2020-04-30
for you to fetch changes up to 230982d8d8df7f9d9aa216840ea2db1df6ad5d37:
drm/i915: Update DRIVER_DATE to 20200430 (20
From: Ville Syrjälä
Remove all the stepping dependent cnl workarounds. Bspec lists
more steppings than this so presumably these are classed as
pre-production. And this is cnl after all so no one should
really care anyway.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/gt/intel_rc6.c
From: Ville Syrjälä
GLK wants the +1 adjustement for the "blocks per line" value
for x-tile/y-tile, just like cnl+.
Also the x-tile and linear cases are almost identical. The only
difference is this +1 which is always done for glk+, and only
done for linear on skl/bxt. Let's unify it to a single
Quoting Lionel Landwerlin (2020-04-28 13:08:16)
> Add 2 new properties to the i915-perf open ioctl to specify an array
> of GEM context handles as well as the length of the array.
>
> This can be used by drivers using multiple GEM contexts to implement a
> single GL context.
>
> Signed-off-by: Li
Quoting Ville Syrjala (2020-04-30 13:58:22)
> From: Ville Syrjälä
>
> Remove all the stepping dependent cnl workarounds. Bspec lists
> more steppings than this so presumably these are classed as
> pre-production. And this is cnl after all so no one should
> really care anyway.
>
> Signed-off-by:
== Series Details ==
Series: drm/i915: Update Slylake PCI IDs
URL : https://patchwork.freedesktop.org/series/76750/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8399_full -> Patchwork_17524_full
Summary
---
**FAILUR
== Series Details ==
Series: series starting with [1/2] drm/i915: Fix glk watermark calculations
URL : https://patchwork.freedesktop.org/series/76774/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8401 -> Patchwork_17527
Su
Hi Ville
I don't fully grok the i915 changes to provide meaningful review.
There are couple of small comments below, but regardless of those
Patches 01-11 and 14-16 are:
Reviewed-by: Emil Velikov
On Tue, 28 Apr 2020 at 18:20, Ville Syrjala
wrote:
> The downside is that drm_mode_expose_to_user
Make all the internal necessary changes before we flip the switch.
v2: Use an unlimited number of intel contexts (Chris)
v3: Handle GEM context with multiple RCS0 logical contexts (Chris)
v4: Let the intel_context create its own timeline (Chris)
Only pin configuration context when needed (Ch
Add 2 new properties to the i915-perf open ioctl to specify an array
of GEM context handles as well as the length of the array.
This can be used by drivers using multiple GEM contexts to implement a
single GL context.
Signed-off-by: Lionel Landwerlin
Link: https://gitlab.freedesktop.org/mesa/mes
We want to enable performance monitoring on multiple contexts to cover
the Iris use case of using 2 GEM contexts (3D & compute).
So start by breaking the OA configuration BO which contains global &
per context register writes.
NOA muxes & OA configurations are global, while FLEXEU register
config
Chris doesn't like that.
v2: Don't forget to configure the kernel so that periodic reports are
written appropriately (Lionel)
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 153 +
drivers/gpu/drm/i915/i915_perf_types.h | 10 +-
2 files
Hi all,
Just adding Mesa MR links to the patches.
Cheers,
Lionel Landwerlin (4):
drm/i915/perf: break OA config buffer object in 2
drm/i915/perf: stop using the kernel context
drm/i915/perf: prepare driver to receive multiple ctx handles
drm/i915/perf: enable filtering on multiple contex
Hi Dave and Daniel,
Here goes drm-intel-fixes-2020-04-30:
- Fix selftest refcnt leak (Xiyu)
- Fix gem vma lock (Chris)
- Fix gt's i915_request.timeline acquire by checking if cacheline is valid
(Chris)
- Fix IRQ postinistall fault masks (Matt)
Thanks,
Rodrigo.
The following changes since commi
On Wed, Apr 29, 2020 at 11:19:07AM +, k...@kl.wtf wrote:
> April 28, 2020 5:14 PM, "Daniel Vetter" wrote:
>
> > On Fri, Apr 24, 2020 at 06:26:15PM +0200, Kenny Levinsen wrote:
> >
> >> Some processes, such as systemd, are only polling for EPOLLERR|EPOLLHUP.
> >> As drm_file uses unkeyed wake
== Series Details ==
Series: drm/i915/perf: Add support for multi context perf queries (rev4)
URL : https://patchwork.freedesktop.org/series/76588/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a350ade77f42 drm/i915/perf: break OA config buffer object in 2
5845f5921ffd drm/i915
== Series Details ==
Series: series starting with [01/25] perf/core: Only copy-to-user after
completely unlocking all locks, v3.
URL : https://patchwork.freedesktop.org/series/76724/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8391_full -> Patchwork_17513_full
=
Hi
On 28.04.2020 16:27, Tvrtko Ursulin wrote:
>
> On 28/04/2020 14:19, Marek Szyprowski wrote:
>> The Documentation/DMA-API-HOWTO.txt states that dma_map_sg returns the
>> numer of the created entries in the DMA address space. However the
>> subsequent calls to dma_sync_sg_for_{device,cpu} and dma
== Series Details ==
Series: drm/i915/perf: Add support for multi context perf queries (rev4)
URL : https://patchwork.freedesktop.org/series/76588/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8401 -> Patchwork_17528
Summa
Quoting Lionel Landwerlin (2020-04-30 14:55:35)
> @@ -1382,6 +1446,12 @@ static void i915_oa_stream_destroy(struct
> i915_perf_stream *stream)
>
> BUG_ON(stream != perf->exclusive_stream);
>
> + err = intel_context_pin(stream->config_context);
> + if (err) {
> +
On 30/04/2020 17:55, Chris Wilson wrote:
Quoting Lionel Landwerlin (2020-04-30 14:55:35)
@@ -1382,6 +1446,12 @@ static void i915_oa_stream_destroy(struct
i915_perf_stream *stream)
BUG_ON(stream != perf->exclusive_stream);
+ err = intel_context_pin(stream->config_context);
== Series Details ==
Series: drm/i915/selftests: Add tiled blits selftest (rev2)
URL : https://patchwork.freedesktop.org/series/76746/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8399_full -> Patchwork_17525_full
Summary
Quoting Lionel Landwerlin (2020-04-30 14:55:33)
> We want to enable performance monitoring on multiple contexts to cover
> the Iris use case of using 2 GEM contexts (3D & compute).
>
> So start by breaking the OA configuration BO which contains global &
> per context register writes.
>
> NOA muxe
On Wed, Apr 29, 2020 at 4:57 AM Jani Nikula wrote:
>
> On Tue, 28 Apr 2020, Michal Orzel wrote:
> > As suggested by the TODO list for the kernel DRM subsystem, replace
> > the deprecated functions that take/drop modeset locks with new helpers.
> >
> > Signed-off-by: Michal Orzel
> > ---
> > dri
To ensure that we have global observation point wrt to
all data, flush amfs.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_
Flush TDL and L3.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b3ddb928d231..0bbce218157f 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.
Do a l3 fabric flush when emitting flush.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
b/drivers/gpu/drm/i915/
Treat media state as any other state and invalidate it.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 789efece1fc0..859c901c8935 100644
---
HDC pipeline flush is bit on the first dword of
the PIPE_CONTROL, not the second. Make it so.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_engine.h | 23 +++
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 3
Flush enable bit is a sync point which makes this
pipecontrol to wait that everything on a previous
pipe control are flushed. Enable it to make
sure that our invalidates doesn't overlap.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++
1 file changed, 2 insertions(+)
This reverts commit 62037229b7d94f1db5ef8d2e2ec819832ef3.
L3 ro cache invalidation is part of the dword0 of pipe
control. Also it is not relevant to this gen.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 -
drivers/gpu/drm/i915/gt/intel_lrc.c |
Request boundary is a global observation point for
all operations. Thus flush the LLC too.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 ++
2 files changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915
Aim for completeness for invalidating everything
and mark state pointers stale.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c
b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b47230583494..
== Series Details ==
Series: series starting with [1/9] Revert "drm/i915/tgl: Include ro parts of l3
to invalidate"
URL : https://patchwork.freedesktop.org/series/76777/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
53177bdb8662 Revert "drm/i915/tgl: Include ro parts of l3 to
== Series Details ==
Series: series starting with [1/9] Revert "drm/i915/tgl: Include ro parts of l3
to invalidate"
URL : https://patchwork.freedesktop.org/series/76777/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8401 -> Patchwork_17529
Quoting Patchwork (2020-04-30 17:25:55)
> == Series Details ==
>
> Series: series starting with [1/9] Revert "drm/i915/tgl: Include ro parts of
> l3 to invalidate"
> URL : https://patchwork.freedesktop.org/series/76777/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_
On 30/04/2020 12:18, Chris Wilson wrote:
Since the introduction of 'soft-rc6', we aim to park the device quickly
and that results in frequent idling of the whole device. Currently upon
idling we free the batch buffer pool, and so this renders the cache
ineffective for many workloads. If we want
If the PMU is active, it will be utilising the driver internals for its
sampling. Therefore we must not remove the driver while PMU is still
awake! Hence try to unload the module while the pmu is open.
Signed-off-by: Chris Wilson
---
tests/perf_pmu.c | 96
If the PMU is active, it will be utilising the driver internals for its
sampling. Therefore we must not remove the driver while PMU is still
awake! Hence try to unload the module while the pmu is open.
Signed-off-by: Chris Wilson
---
tests/perf_pmu.c | 96
On Thu, Apr 30, 2020 at 5:38 PM Sean Paul wrote:
>
> On Wed, Apr 29, 2020 at 4:57 AM Jani Nikula
> wrote:
> >
> > On Tue, 28 Apr 2020, Michal Orzel wrote:
> > > As suggested by the TODO list for the kernel DRM subsystem, replace
> > > the deprecated functions that take/drop modeset locks with n
Quoting Chris Wilson (2020-04-30 19:28:59)
> +static void test_unload(void)
> +{
> + igt_fork(child, 1) {
...
> + igt_debug("Read %d events from perf and trial unload\n",
> count);
> + pmu_read_multi(fd, count, buf);
> + igt_assert_eq(unload_i915(),
While a perf event is open, keep a reference to the module so we don't
remove the driver internals mid-sampling.
Testcase: igt/perf_pmu/module-unload
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: sta...@vger.kernel.org
---
drivers/gpu/drm/i915/i915_pmu.c | 5 -
1 file changed, 4 insert
Future platforms require per-crtc SAGV evaluation
and serializing global state when those are changed
from different commits.
v2: - Add has_sagv check to intel_crtc_can_enable_sagv
so that it sets bit in reject mask.
- Use bw_state in intel_pre/post_plane_enable_sagv
instead of ato
We need to calculate SAGV mask also in a non-modeset
commit, however currently active_pipes are only calculated
for modesets in global atomic state, thus now we will be
tracking those also in bw_state in order to be able to
properly access global data.
v2: - Removed pre/post plane SAGV updates fro
== Series Details ==
Series: drm/i915/pmu: Keep a reference to module while active
URL : https://patchwork.freedesktop.org/series/76779/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8402 -> Patchwork_17530
Summary
---
gdb uses ptrace() to peek and poke bytes of the target's address space.
The driver must implement an vm_ops->access() handler or else gdb will
be unable to inspect the pointer and report it as out-of-bounds.
Worse than useless as it causes immediate suspicion of the valid GTT
pointer, distracting t
gdb uses ptrace() to peek and poke bytes of the target's address space.
The kernel must implement an vm_ops->access() handler or else gdb will
be unable to inspect the pointer and report it as out-of-bounds. Worse
than useless as it causes immediate suspicion of the valid GTT pointer.
Signed-off-b
gdb uses ptrace() to peek and poke bytes of the target's address space.
The kernel must implement an vm_ops->access() handler or else gdb will
be unable to inspect the pointer and report it as out-of-bounds. Worse
than useless as it causes immediate suspicion of the valid GPU pointer.
Signed-off-b
We need to calculate SAGV mask also in a non-modeset
commit, however currently active_pipes are only calculated
for modesets in global atomic state, thus now we will be
tracking those also in bw_state in order to be able to
properly access global data.
v2: - Removed pre/post plane SAGV updates fro
Introduce platform dependent SAGV checking in
combination with bandwidth state pipe SAGV mask.
v2, v3, v4, v5, v6: Fix rebase conflict
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 30 --
1 file changed, 28 insertions(+), 2 deletions(-)
di
Starting from TGL we need to have a separate wm0
values for SAGV and non-SAGV which affects
how calculations are done.
v2: Remove long lines
v3: Removed COLOR_PLANE enum references
v4, v5, v6: Fixed rebase conflict
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_displa
== Series Details ==
Series: series starting with [1/9] drm/i915/gt: Stop holding onto the
pinned_default_state
URL : https://patchwork.freedesktop.org/series/76771/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8401_full -> Patchwork_17526_full
==
gdb uses ptrace() to peek and poke bytes of the target's address space.
The driver must implement an vm_ops->access() handler or else gdb will
be unable to inspect the pointer and report it as out-of-bounds.
Worse than useless as it causes immediate suspicion of the valid GTT
pointer, distracting t
gdb uses ptrace() to peek and poke bytes of the target's address space.
The driver must implement an vm_ops->access() handler or else gdb will
be unable to inspect the pointer and report it as out-of-bounds.
Worse than useless as it causes immediate suspicion of the valid GTT
pointer, distracting t
== Series Details ==
Series: series starting with [1/2] drm/i915: Fix glk watermark calculations
URL : https://patchwork.freedesktop.org/series/76774/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8401_full -> Patchwork_17527_full
==
Hi!
Here's this week drm-misc-fixes PR
Thanks!
Maxime
drm-misc-fixes-2020-04-30:
A few resources-related fixes for qxl, some doc build warnings and ioctl
fixes for dma-buf, an off-by-one fix in edid, and a return code fix in
DP-MST
The following changes since commit 9da67433f64eb89e5a7b479775078
== Series Details ==
Series: SAGV support for Gen12+ (rev32)
URL : https://patchwork.freedesktop.org/series/75129/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8403 -> Patchwork_17531
Summary
---
**SUCCESS**
No r
== Series Details ==
Series: drm/i915/perf: Add support for multi context perf queries (rev4)
URL : https://patchwork.freedesktop.org/series/76588/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8401_full -> Patchwork_17528_full
=
== Series Details ==
Series: drm/i915: Implement vm_ops->access for gdb access into mmaps (rev3)
URL : https://patchwork.freedesktop.org/series/76783/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8403 -> Patchwork_17532
Su
== Series Details ==
Series: drm/i915: Implement vm_ops->access for gdb access into mmaps (rev3)
URL : https://patchwork.freedesktop.org/series/76783/
State : warning
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
CHK include/generated/compile.h
From: Maarten Lankhorst
v2:
* Manual Rebase (Manasi)
Signed-off-by: Maarten Lankhorst
Signed-off-by: Manasi Navare
---
drivers/gpu/drm/i915/display/intel_display.c | 61 ---
.../drm/i915/display/intel_display_types.h| 11 ++-
drivers/gpu/drm/i915/intel_pm.c | 76
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