On Fri, 17 Apr 2020, Kai Vehmanen wrote:
> Hi Jani,
>
> On Fri, 17 Apr 2020, Jani Nikula wrote:
>
>> We have some module unload/reload tests hitting an issue with i915
>> unbinding the component interface before the audio driver has properly
>> put the power. Log an error about it for ease of debu
Quoting Sultan Alsawaf (2020-04-20 08:24:19)
> Chris,
>
> Could you please look at this in earnest? This is a real bug that crashes my
> laptop without any kind of provocation. It is undeniably a bug in i915, and
> I've
> clearly described it in my patch. If you dont like the patch, I'm open to a
Import the kernel's i915_pciids.h, up to:
commit 8717c6b7414ffb890672276dccc284c23078ac0e
Author: Lee Shawn C
Date: Tue Dec 10 23:04:15 2019 +0800
drm/i915/cml: Separate U series pci id from origianl list.
Signed-off-by: Liwei Song
---
V2 -> V3:
Add 4 new info blocks and add sound sup
== Series Details ==
Series: drm/i915: store HW tagging information into tracepoints (rev2)
URL : https://patchwork.freedesktop.org/series/75849/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8324_full -> Patchwork_17373_full
===
Future platforms require per-crtc SAGV evaluation
and serializing global state when those are changed
from different commits.
v2: - Add has_sagv check to intel_crtc_can_enable_sagv
so that it sets bit in reject mask.
- Use bw_state in intel_pre/post_plane_enable_sagv
instead of ato
Introduce platform dependent SAGV checking in
combination with bandwidth state pipe SAGV mask.
v2, v3, v4: Fix rebase conflict
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 38 -
1 file changed, 28 insertions(+), 10 deletions(-)
diff -
Starting from TGL we need to have a separate wm0
values for SAGV and non-SAGV which affects
how calculations are done.
v2: Remove long lines
v3: Removed COLOR_PLANE enum references
v4: Fixed rebase conflict
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_display.c |
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
v2: Fixed wrong PCode reply mask, removed hardcoded
values.
v3: Forbid si
== Series Details ==
Series: Sync i915_pciids upto 8717c6b7414f (rev3)
URL : https://patchwork.freedesktop.org/series/76080/
State : failure
== Summary ==
Applying: Sync i915_pciids upto 8717c6b7414f
error: sha1 information is lacking or useless (src/intel_module.c).
error: could not build fak
== Series Details ==
Series: SAGV support for Gen12+ (rev25)
URL : https://patchwork.freedesktop.org/series/75129/
State : failure
== Summary ==
Applying: drm/i915: Introduce skl_plane_wm_level accessor.
Applying: drm/i915: Add intel_atomic_get_bw_*_state helpers
Using index info to reconstruc
Quoting Greg KH (2020-04-14 11:23:44)
> On Tue, Apr 14, 2020 at 09:15:07AM +0100, Chris Wilson wrote:
> > Quoting Greg KH (2020-04-11 12:39:57)
> > > On Fri, Apr 10, 2020 at 07:17:38AM -0700, Sultan Alsawaf wrote:
> > > > On Fri, Apr 10, 2020 at 11:08:38AM +0200, Greg KH wrote:
> > > > > On Tue, Ap
If we can not manipulate the frequency with RPS, then comparing min/max
power consumption is pointless / misleading. We will leave the warning
about not being able to control the frequency selection via RPS to other
tests so as not to confuse this more specialised check.
Signed-off-by: Chris Wilso
Check that the GPU does respond to our RPS frequency requests by setting
our desired frequency.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 1 +
drivers/gpu/drm/i915/gt/selftest_rps.c | 196 ---
drivers/gpu/drm/i915/gt/selftest_rps.h | 1
One of the core tenents of reclocking the GPU is that its throughput
scales with the clock frequency. We can observe this by incrementing a
loop counter on the GPU, and compare the different execution rates at
the notional RPS frequencies.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/
Split the frequency measurement into two modes, so that we can judge the
impact of the llc setup on top of the pure CS frequency scaling.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 3 +-
drivers/gpu/drm/i915/gt/selftest_rps.c | 157 ++-
dri
In Gpuvis [1] we added matching of the OA report tags against i915
tracepoints fields to figure what workload was submitted by what
process. It doesn't matter much whether HW tags get reused for a
single request, as it gets preempted for example. All we need is link
between the OA report and seqno/
Looks like I'l have to resend the series, because patches 2,3,4 were now
pushed and git am fails to reapply those as part of this series,
when I first sent those as in-reply.
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
__
Without async flip support in the kernel, fullscreen apps where game
resolution is equal to the screen resolution, must perform an extra blit
per frame prior to flipping.
Asynchronous page flips will also boost the FPS of Mesa benchmarks.
v2: Few patches have been squashed and patches have been s
Set the Async Address Update Enable bit in plane ctl
when async flip is requested.
v2: -Move the Async flip enablement to individual patch (Paulo)
Signed-off-by: Karthik B S
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files cha
Support added only for async flips on primary plane.
If flip is requested on any other plane, reject it.
Make sure there is no change in fbc, offset and framebuffer modifiers
when async flip is requested.
If any of these are modified, reject async flip.
v2: -Replace DRM_ERROR (Paulo)
-Add ch
Add enable/disable flip done functions and the flip done handler
function which handles the flip done interrupt.
Enable the flip done interrupt in IER.
Enable flip done function is called before writing the
surface address register as the write to this register triggers
the flip done interrupt
F
Enable asynchronous flips in i915 for gen9+ platforms.
v2: -Async flip enablement should be a stand alone patch (Paulo)
Signed-off-by: Karthik B S
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
Since the flip done event will be sent in the flip_done_handler,
no need to add the event to the list and delay it for later.
v2: -Moved the async check above vblank_get as it
was causing issues for PSR.
Signed-off-by: Karthik B S
---
drivers/gpu/drm/i915/display/intel_sprite.c | 2 +-
1 f
Make the commit call blocking in case of async flips
so that there is no delay in completing the flip.
v2: -Rebased
Signed-off-by: Karthik B S
---
drivers/gpu/drm/i915/display/intel_display.c | 15 ++-
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i9
== Series Details ==
Series: series starting with [1/4] drm/i915/selftests: Verify frequency scaling
with RPS
URL : https://patchwork.freedesktop.org/series/76184/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8327 -> Patchwork_17376
==
== Series Details ==
Series: drm/i915: store HW tagging information into tracepoints (rev3)
URL : https://patchwork.freedesktop.org/series/75849/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/genera
== Series Details ==
Series: Asynchronous flip implementation for i915 (rev2)
URL : https://patchwork.freedesktop.org/series/74386/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ae7aa012537f drm/i915: Add enable/disable flip done and flip done handler
3c944ffc2524 drm/i915: Add
On Mon, 13 Apr 2020, Lyude Paul wrote:
> Looks like I accidentally made it so you couldn't force DPCD backlight
> support on, whoops. Fix that.
Thanks, pushed.
BR,
Jani.
>
> Signed-off-by: Lyude Paul
> Fixes: 17f5d57915be ("drm/i915: Force DPCD backlight mode on X1 Extreme 2nd
> Gen 4K AMOL
== Series Details ==
Series: Asynchronous flip implementation for i915 (rev2)
URL : https://patchwork.freedesktop.org/series/74386/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8327 -> Patchwork_17378
Summary
---
**
In Gpuvis [1] we added matching of the OA report tags against i915
tracepoints fields to figure what workload was submitted by what
process. It doesn't matter much whether HW tags get reused for a
single request, as it gets preempted for example. All we need is link
between the OA report and seqno/
On 17-04-2020 22:58, Anshuman Gupta wrote:
Gen11 onwards PG3 contains functions for pipe B,
external displays, and VGA. Add missing ICL_DISP_PW_3
for ehl_power_wells.
Cc: Animesh Manna
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1737
Signed-off-by: Anshuman Gupta
Looks ok to
Chris Wilson writes:
> One of the core tenents of reclocking the GPU is that its throughput
> scales with the clock frequency. We can observe this by incrementing a
> loop counter on the GPU, and compare the different execution rates at
> the notional RPS frequencies.
>
> Signed-off-by: Chris Wil
Since we may lose the content of any buffer when we relinquish control
of the system (e.g. suspend/resume), we have to be careful not to rely
on regaining control. A good method to detect when we might be using
garbage is by always injecting that garbage prior to first use on
load/resume/etc.
v2:
Quoting Mika Kuoppala (2020-04-20 11:54:38)
> Chris Wilson writes:
>
> > One of the core tenents of reclocking the GPU is that its throughput
> > scales with the clock frequency. We can observe this by incrementing a
> > loop counter on the GPU, and compare the different execution rates at
> > th
Chris Wilson writes:
> If we can not manipulate the frequency with RPS, then comparing min/max
> power consumption is pointless / misleading. We will leave the warning
> about not being able to control the frequency selection via RPS to other
> tests so as not to confuse this more specialised che
== Series Details ==
Series: series starting with [1/4] drm/i915/selftests: Verify frequency scaling
with RPS
URL : https://patchwork.freedesktop.org/series/76184/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8327 -> Patchwork_17376
==
We need a new PCode request commands and reply codes
to be added as a prepartion patch for QGV points
restricting for new SAGV support.
v2: - Extracted those changes into separate patch
(Ville Syrjälä)
v3: - Moved new PCode masks to another place from
PCode commands(Ville)
Signed-off
Flip the switch and enable SAGV support
for Gen12 also.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e4aef90c7364..75991467a375 100644
--- a/dr
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
v2: Fixed wrong PCode reply mask, removed hardcoded
values.
v3: Forbid si
Starting from TGL we need to have a separate wm0
values for SAGV and non-SAGV which affects
how calculations are done.
v2: Remove long lines
v3: Removed COLOR_PLANE enum references
v4: Fixed rebase conflict
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_display.c |
For future Gen12 SAGV implementation we need to
seemlessly alter wm levels calculated, depending
on whether we are allowed to enable SAGV or not.
So this accessor will give additional flexibility
to do that.
Currently this accessor is still simply working
as "pass-through" function. This will be
Introduce platform dependent SAGV checking in
combination with bandwidth state pipe SAGV mask.
v2, v3, v4: Fix rebase conflict
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/intel_pm.c | 38 -
1 file changed, 28 insertions(+), 10 deletions(-)
diff -
Future platforms require per-crtc SAGV evaluation
and serializing global state when those are changed
from different commits.
v2: - Add has_sagv check to intel_crtc_can_enable_sagv
so that it sets bit in reject mask.
- Use bw_state in intel_pre/post_plane_enable_sagv
instead of ato
That is a preparation patch before next one where we
introduce old_bw_state and a bunch of other changes
as well.
In a review comment it was suggested to split out
at least that renaming into a separate patch, what
is done here.
v2: Removed spurious space
Reviewed-by: Ville Syrjälä
Signed-off-by
For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can
== Series Details ==
Series: drm/i915: store HW tagging information into tracepoints (rev4)
URL : https://patchwork.freedesktop.org/series/75849/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
88fa70a96d6c drm/i915: store HW tagging information into tracepoints
-:14: ERROR:GIT_C
== Series Details ==
Series: drm/i915: store HW tagging information into tracepoints (rev4)
URL : https://patchwork.freedesktop.org/series/75849/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8328 -> Patchwork_17379
Summary
== Series Details ==
Series: drm/i915/gt: Poison residual state [HWSP] across resume. (rev3)
URL : https://patchwork.freedesktop.org/series/76100/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8328 -> Patchwork_17380
Summar
Avoid flushing the submission queue (of others) under the client's
timeline lock, but instead move it to the end so that we may catch more.
References: https://gitlab.freedesktop.org/drm/intel/-/issues/1066
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gt_requests.c | 5 -
1
Since moving the obj->vma.list to a spin_lock, and the vm->bound_list to
its vm->mutex, along with tracking shrinkable status under its own
spinlock, we no long require the object to be locked by the caller.
This is fortunate as it appears we can be called with the lock along an
error path in flip
Chris Wilson writes:
> Quoting Mika Kuoppala (2020-04-20 11:54:38)
>> Chris Wilson writes:
>>
>> > One of the core tenents of reclocking the GPU is that its throughput
>> > scales with the clock frequency. We can observe this by incrementing a
>> > loop counter on the GPU, and compare the diffe
This patch fixes a kernel taint on non DSC DP monitors.
Fixes: 48b8b04c7 ("drm/i915/display: Enable DP Display Audio WA")
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1750
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/display/intel_audio.c | 5 +++--
1 file changed, 3 insertio
Quoting Mika Kuoppala (2020-04-20 13:54:21)
> Chris Wilson writes:
>
> > Quoting Mika Kuoppala (2020-04-20 11:54:38)
> >> Further, intel_runtime_pm_get is missing.
> >
> > For what? We acquire the wakeref via the request on the engine.
> >
> > We don't talk to intel_runtime_pm directly, everythin
Hi,
On 4/15/20 7:44 PM, Daniel Vetter wrote:
On Wed, Apr 15, 2020 at 05:03:55PM +0200, Hans de Goede wrote:
Hi,
On 4/15/20 9:39 AM, Daniel Vetter wrote:
Allows us to drop the cleanup code on the floor.
Sam noticed in his review:
With this change we avoid calling pci_disable_device()
twise i
The early check for compressed_bpp being zero is too early, as it is hit
also when DSC is not enabled. Move the checks down to where the values
are actually needed. This is a paranoid check for a situation that
should not happen, so we don't really care about handling it gracefully
apart from not o
> -Original Message-
> From: Jani Nikula
> Sent: Monday, April 20, 2020 6:47 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; Gupta, Anshuman
> ; Shankar, Uma
> Subject: [PATCH] drm/i915/audio: fix compressed_bpp check
>
> The early check for compressed_bpp being zero is
> -Original Message-
> From: Shankar, Uma
> Sent: Monday, April 20, 2020 7:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Vehmanen, Kai ; Gupta, Anshuman
> ; jani.nik...@linux.intel.com; chris-wilson.co.uk;
> Shankar, Uma
> Subject: [PATCH] drm/i915/display: Fixed kernel taint in au
Hi
Am 15.04.20 um 09:39 schrieb Daniel Vetter:
> Add a new macro helper to combine the usual init sequence in drivers,
> consisting of a kzalloc + devm_drm_dev_init + drmm_add_final_kfree
> triplet. This allows us to remove the rather unsightly
> drmm_add_final_kfree from all currently merged driv
== Series Details ==
Series: SAGV support for Gen12+ (rev26)
URL : https://patchwork.freedesktop.org/series/75129/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8328 -> Patchwork_17381
Summary
---
**SUCCESS**
No r
== Series Details ==
Series: series starting with [1/2] drm/i915/gem: Remove object_is_locked
assertion from unpin_from_display_plane
URL : https://patchwork.freedesktop.org/series/76194/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5b3ba577946c drm/i915/gem: Remove object_is
Unused, hiding from the compiler warnings behind the inline keyword.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 9c05
Remove a number of inlines from .c files, and let the compiler decide
what's best. There's more to do, but need to start somewhere, and need
to start setting the example.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/icl_dsi.c| 8 +++
drivers/gpu/drm/i915/display/intel
== Series Details ==
Series: series starting with [1/2] drm/i915/gem: Remove object_is_locked
assertion from unpin_from_display_plane
URL : https://patchwork.freedesktop.org/series/76194/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8328 -> Patchwork_17382
==
tree: git://anongit.freedesktop.org/drm-intel topic/core-for-CI
head: d0435a9b45070b945578c093dcd363b6b73a502c
commit: 198db0fc276cdf8e1bb66a4a03473dbea1400d18 [18/20] Revert "drm/i915:
Don't select BROKEN"
config: x86_64-allyesconfig (attached as .config)
compiler: gcc-7 (Ubuntu 7.5.0-6ubuntu
The PPS is supposed to reflect the DSC config instead of hard coding the
rc_model_size. Make it so.
Currently all users of drm_dsc_pps_payload_pack() hard code the size to
8192 also in the DSC config, so this change should have no impact, other
than allowing the drivers to use other sizes as neede
The rc_model_size is specified in the DSC config, and the hardware
programming should respect that instead of hard coding a value of 8192.
Regardless, the rc_model_size in DSC config is currently hard coded to
the same value, so this should have no impact, other than allowing the
use of other size
== Series Details ==
Series: series starting with [01/24] perf/core: Only copy-to-user after
completely unlocking all locks, v3.
URL : https://patchwork.freedesktop.org/series/76096/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8319_full -> Patchwork_17349_full
=
On Fri, 17 Apr 2020, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> No reason that I can see why we should enable TRANS_DDI_FUNC_CTL
> before we set up the watermarks of confogiure the mbus stuff.
> In fact reordering these seems to match the bspec sequence better,
> and cricually will allow us t
On Mon, 20 Apr 2020 at 13:54, Chris Wilson wrote:
>
> Since moving the obj->vma.list to a spin_lock, and the vm->bound_list to
> its vm->mutex, along with tracking shrinkable status under its own
> spinlock, we no long require the object to be locked by the caller.
>
> This is fortunate as it appe
== Series Details ==
Series: drm/i915/display: Fixed kernel taint in audio codec init
URL : https://patchwork.freedesktop.org/series/76195/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8329 -> Patchwork_17383
Summary
-
On Mon, 20 Apr 2020 at 13:54, Chris Wilson wrote:
>
> Avoid flushing the submission queue (of others) under the client's
> timeline lock, but instead move it to the end so that we may catch more.
>
> References: https://gitlab.freedesktop.org/drm/intel/-/issues/1066
> Signed-off-by: Chris Wilson
== Series Details ==
Series: Asynchronous flip implementation for i915 (rev2)
URL : https://patchwork.freedesktop.org/series/74386/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8327_full -> Patchwork_17378_full
Summary
---
== Series Details ==
Series: drm/i915/audio: fix compressed_bpp check
URL : https://patchwork.freedesktop.org/series/76196/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8329 -> Patchwork_17384
Summary
---
**SUCCESS*
== Series Details ==
Series: series starting with [1/4] drm/i915/selftests: Verify frequency scaling
with RPS
URL : https://patchwork.freedesktop.org/series/76184/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8327_full -> Patchwork_17376_full
On Mon, Apr 20, 2020 at 04:22:07PM +0800, Liwei Song wrote:
> Import the kernel's i915_pciids.h, up to:
>
> commit 8717c6b7414ffb890672276dccc284c23078ac0e
> Author: Lee Shawn C
> Date: Tue Dec 10 23:04:15 2019 +0800
>
> drm/i915/cml: Separate U series pci id from origianl list.
>
> Signe
If we encounter an error while scaling, read back the frequency tables
from the pcu.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_rps.c | 39 ++
1 file changed, 39 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c
b/drivers/gpu/drm/i9
Split the frequency measurement into two modes, so that we can judge the
impact of the llc setup on top of the pure CS frequency scaling.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 3 +-
drivers/gpu/drm/i915/gt/selftest_rps.c | 157 ++-
dri
If we can not manipulate the frequency with RPS, then comparing min/max
power consumption is pointless / misleading. We will leave the warning
about not being able to control the frequency selection via RPS to other
tests so as not to confuse this more specialised check.
Signed-off-by: Chris Wilso
One of the core tenents of reclocking the GPU is that its throughput
scales with the clock frequency. We can observe this by incrementing a
loop counter on the GPU, and compare the different execution rates at
the notional RPS frequencies.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
-
Check that the GPU does respond to our RPS frequency requests by setting
our desired frequency.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 1 +
drivers/gpu/drm/i915/gt/selftest_rps.c | 196 ---
drivers/gpu/drm/i915/gt/selftest_rps.h | 1
After having testing all the RPS controls individually, we need to take
a step back and check how our RPS worker integrates them to perform
dynamic GPU reclocking. So do that by submitting a spinner and wait and
see what happens.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_g
== Series Details ==
Series: drm/i915: store HW tagging information into tracepoints (rev4)
URL : https://patchwork.freedesktop.org/series/75849/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8328_full -> Patchwork_17379_full
===
Chris Wilson writes:
> Check that the GPU does respond to our RPS frequency requests by setting
> our desired frequency.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 1 +
> drivers/gpu/drm/i915/gt/selftest_rps.c | 196 ---
> drivers/
== Series Details ==
Series: drm/i915/gt: Poison residual state [HWSP] across resume. (rev3)
URL : https://patchwork.freedesktop.org/series/76100/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8328_full -> Patchwork_17380_full
==
Chris Wilson writes:
> Split the frequency measurement into two modes, so that we can judge the
> impact of the llc setup on top of the pure CS frequency scaling.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 3 +-
> drivers/gpu/drm/i915/gt/selftest_rps.c
From: Alexey Budankov
Introduce the CAP_PERFMON capability designed to secure system
performance monitoring and observability operations so that CAP_PERFMON
can assist CAP_SYS_ADMIN capability in its governing role for
performance monitoring and observability subsystems.
CAP_PERFMON hardens syst
From: Alexey Budankov
Open access to monitoring for CAP_PERFMON privileged process. Providing
the access under CAP_PERFMON capability singly, without the rest of
CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials
and makes operation more secure.
CAP_PERFMON implements the pri
From: Alexey Budankov
Update the kernel.rst documentation file with the information related to
usage of CAP_PERFMON capability to secure performance monitoring and
observability operations in system.
Signed-off-by: Alexey Budankov
Cc: Alexei Starovoitov
Cc: Andi Kleen
Cc: Igor Lubashev
Cc: J
From: Alexey Budankov
Extend error messages to mention CAP_PERFMON capability as an option to
substitute CAP_SYS_ADMIN capability for secure system performance
monitoring and observability operations. Make
perf_event_paranoid_check() and __cmd_ftrace() to be aware of
CAP_PERFMON capability.
CAP_
On Mon, Apr 20, 2020 at 11:21:42AM +0300, Joonas Lahtinen wrote:
> So it seems that the patch got pulled into v5.6 and has been backported
> to v5.5 but not v5.4.
You're right, that's my mistake.
> In doing that zeroing of ring->vaddr is removed so the test to do mdelay(1)
> and "ring->vaddr = NU
From: Alexey Budankov
Open access to monitoring for CAP_PERFMON privileged process. Providing
the access under CAP_PERFMON capability singly, without the rest of
CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials
and makes operation more secure.
CAP_PERFMON implements the pri
From: Alexey Budankov
Open access to monitoring of kernel code, CPUs, tracepoints and
namespaces data for a CAP_PERFMON privileged process. Providing the
access under CAP_PERFMON capability singly, without the rest of
CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials
and makes
From: Alexey Budankov
Open access to i915_perf monitoring for CAP_PERFMON privileged process.
Providing the access under CAP_PERFMON capability singly, without the
rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the
credentials and makes operation more secure.
CAP_PERFMON implement
From: Alexey Budankov
Open access to monitoring for CAP_PERFMON privileged process. Providing
the access under CAP_PERFMON capability singly, without the rest of
CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials
and makes operation more secure.
CAP_PERFMON implements the pri
Chris,
Could you please look at this in earnest? This is a real bug that crashes my
laptop without any kind of provocation. It is undeniably a bug in i915, and I've
clearly described it in my patch. If you dont like the patch, I'm open to any
suggestions you have for an alternative solution. My go
From: Alexey Budankov
Update perf-security.rst documentation file with the information
related to usage of CAP_PERFMON capability to secure performance
monitoring and observability operations in system.
Committer notes:
While testing 'perf top' under cap_perfmon I noticed that it needs
some mor
From: Alexey Budankov
Open access to bpf_trace monitoring for CAP_PERFMON privileged process.
Providing the access under CAP_PERFMON capability singly, without the
rest of CAP_SYS_ADMIN credentials, excludes chances to misuse the
credentials and makes operation more secure.
CAP_PERFMON implement
From: Alexey Budankov
Open access to monitoring via kprobes and uprobes and eBPF tracing for
CAP_PERFMON privileged process. Providing the access under CAP_PERFMON
capability singly, without the rest of CAP_SYS_ADMIN credentials,
excludes chances to misuse the credentials and makes operation more
On Mon, Apr 20, 2020 at 12:02:39PM +0300, Joonas Lahtinen wrote:
> I think the the patch should be dropped for now before the issue is
> properly addressed. Either by backporting the mainline fixes or if
> those are too big and there indeed is a smaller alternative patch
> that is properly reviewed
From: Alexey Budankov
Open access to monitoring for CAP_PERFMON privileged process. Providing
the access under CAP_PERFMON capability singly, without the rest of
CAP_SYS_ADMIN credentials, excludes chances to misuse the credentials
and makes operation more secure.
CAP_PERFMON implements the pri
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