Chris Wilson writes:
> Since the fence registers control HW detiling throught the GGTT
> aperture, make them a part of the intel_ggtt under gt/
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/Makefile | 2 +-
> drivers/gpu/drm/i915/gt/
Chris Wilson writes:
> Since we always reload the fence register state on runtime resume,
> having it explicitly in the S0ix resume code is redundant. Indeed, it
> is not even being used!
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 -
Hi ,
When I was going through the gitlab issues,I encountered an issue
https://gitlab.freedesktop.org/xorg/driver/xf86-video-intel/issues/186 for
which the patch is merged in 5.5 kernel and becomes the duplicate of
https://gitlab.freedesktop.org/drm/intel/issues/673 and can be CLOSED.
I didn't g
Chris Wilson writes:
> Since the number of fence regs can vary dramactically between platforms,
> allocate the array on demand so we don't waste as much space.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 6 --
> drivers/gpu/drm/i915/gt/intel_ggtt_
On Thu, 2020-03-05 at 18:53 +0100, Janusz Krzysztofik wrote:
> The test already tried to use a working mapping by first trying legacy
> WC, then GTT. Use gem_mmap__device_coherent() helper instead of
> approaching its implementation locally.
>
> Signed-off-by: Janusz Krzysztofik
Please ignore t
On Tue, Mar 10, 2020 at 06:01:06PM +0200, Ville Syrjälä wrote:
> On Tue, Feb 25, 2020 at 12:35:41PM +0530, Pankaj Bharadiya wrote:
> > Introduce new scaling filter property to allow userspace to select
> > the driver's default scaling filter or Nearest-neighbor(NN) filter
> > for upscaling operatio
Extend initial check for support of MMAP_GTT mapping to userptr with
equivalent checks for each MMAP_OFFSET mapping type supported by i915
driver. Based on that, extend coverage of process-exit-gtt* subtests
over non-GTT mapping types. In case of dmabuf-* subtests, use first
supported mapping typ
On Wed, Mar 11, 2020 at 10:07:13AM +0100, Thomas Zimmermann wrote:
> Hi Daniel
>
> Am 02.03.20 um 23:25 schrieb Daniel Vetter:
> > We have lots of these. And the cleanup code tends to be of dubious
> > quality. The biggest wrong pattern is that developers use devm_, which
> > ties the release acti
Together with recently submitted patches, this series concludes
MMAP_OFFSET related changes required for gem_userptr_blits.
Thanks,
Janusz
Janusz Krzysztofik (2):
tests/gem_userptr_blits: Refresh readonly-mmap-unsync exercise
tests/gem_userptr_blits: Refresh other now MMAP_GTT dependent subte
Upgrade the subtest to use MMAP_GTT API v4 (aka MMAP_OFFSET),
dynamically examine each mapping type supported by i915 driver.
Signed-off-by: Janusz Krzysztofik
---
tests/i915/gem_userptr_blits.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/tests/i915
On Wed, Mar 11, 2020 at 10:14:03AM +0100, Thomas Zimmermann wrote:
>
>
> Am 02.03.20 um 23:25 schrieb Daniel Vetter:
> <...>
> > +
> > +int __drmm_add_action(struct drm_device *dev,
> > + drmres_release_t action,
> > + void *data, const char *name)
> > +{
> > + s
On Wed, Mar 11, 2020 at 10:39:13AM +0100, Thomas Zimmermann wrote:
> Hi
>
> Am 02.03.20 um 23:26 schrieb Daniel Vetter:
> > Well for the simple stuff at least, vblank, gem and minor cleanup I
> > want to further split up as a demonstration.
> >
> > v2: We need to clear drm_device->dev otherwise t
On Wed, Mar 11, 2020 at 10:59:10AM +0100, Thomas Zimmermann wrote:
> Hi
>
> Am 02.03.20 um 23:26 schrieb Daniel Vetter:
> > The cleanup here is somewhat tricky, since we can't tell apart the
> > allocated minor index from 0. So register a cleanup action first, and
> > if the index allocation fails
On 14/03/2020 10:33, Lionel Landwerlin wrote:
On Gen11 powergating half the execution units is a functional
requirement when using the VME samplers. Not fullfilling this
requirement can lead to hangs.
This unfortunately plays fairly poorly with the NOA requirements. NOA
requires a stable power
On 13/03/2020 14:34, Lionel Landwerlin wrote:
On Gen11 powergating half the execution units is a functional
requirement when using the VME samplers. Not fullfilling this
requirement can lead to hangs.
This unfortunately plays fairly poorly with the NOA requirements. NOA
requires a stable power
On 16/03/2020 11:16, Tvrtko Ursulin wrote:
On 13/03/2020 14:34, Lionel Landwerlin wrote:
On Gen11 powergating half the execution units is a functional
requirement when using the VME samplers. Not fullfilling this
requirement can lead to hangs.
This unfortunately plays fairly poorly with the NO
Am 16.03.20 um 09:56 schrieb Christoph Hellwig:
On Fri, Mar 13, 2020 at 09:17:42AM -0300, Jason Gunthorpe wrote:
On Fri, Mar 13, 2020 at 04:21:39AM -0700, Christoph Hellwig wrote:
On Thu, Mar 12, 2020 at 11:19:28AM -0300, Jason Gunthorpe wrote:
The non-page scatterlist is also a big concern fo
On Fri, Mar 06, 2020 at 02:56:06AM -0800, Joe Perches wrote:
> On Fri, 2020-03-06 at 11:39 +0100, Daniel Vetter wrote:
> > On Wed, Mar 04, 2020 at 01:08:32PM +0100, Christian König wrote:
> > > Am 04.03.20 um 13:07 schrieb Lukas Bulwahn:
> > > > Commit 52791eeec1d9 ("dma-buf: rename reservation_obj
On Mon, Mar 16, 2020 at 10:50:07AM +0100, Daniel Vetter wrote:
> On Fri, Mar 06, 2020 at 02:56:06AM -0800, Joe Perches wrote:
> > On Fri, 2020-03-06 at 11:39 +0100, Daniel Vetter wrote:
> > > On Wed, Mar 04, 2020 at 01:08:32PM +0100, Christian König wrote:
> > > > Am 04.03.20 um 13:07 schrieb Lukas
On Mon, Mar 09, 2020 at 12:01:51PM +, Chris Wilson wrote:
> [ 1715.899800] BUG: KCSAN: data-race in drm_gem_handle_create_tail /
> drm_gem_object_handle_put_unlocked
> [ 1715.899838]
> [ 1715.899861] write to 0x8881830f3604 of 4 bytes by task 7834 on cpu 1:
> [ 1715.899896] drm_gem_handle
On Mon, Mar 09, 2020 at 12:15:29PM +, Chris Wilson wrote:
> Mark up the potential racy read in drm_mm_initialized(), as we want a
> cheap and cheerful check:
>
> [ 121.098731] BUG: KCSAN: data-race in _i915_gem_object_create_stolen [i915]
> / rm_hole
> [ 121.098766]
> [ 121.098789] write (
Quoting Mika Kuoppala (2020-03-16 07:29:36)
> Chris Wilson writes:
>
> > Since the number of fence regs can vary dramactically between platforms,
> > allocate the array on demand so we don't waste as much space.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/gt/intel_ggtt.
During phy compliance auto test mode source need to read
requested test pattern from sink through DPCD. After processing
the request source need to set the pattern. So set/get method
added in drm layer as it is DP protocol.
v2: As per review feedback from Manasi on RFC version,
- added dp revision
[Why]:
Aligh with DP spec wanted to follow same naming convention.
[How]:
Changed the macro name of the dpcd address used for getting requested
test-pattern.
Cc: Harry Wentland
Cc: Alex Deucher
Reviewed-by: Harry Wentland
Reviewed-by: Manasi Navare
Signed-off-by: Animesh Manna
---
drivers/g
These debugfs entry will help testapp to understand the test request
during dp phy compliance mode.
Reviewed-by: Manasi Navare
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/d
vswing/pre-emphasis adjustment calculation is needed in processing
of auto phy compliance request other than link training, so have
made non-static function.
No functional change.
v1: initial patch.
v2:
- used "intel_dp" prefix in function name. (Jani)
- used array notation instead pointer for li
DP_COMP_CTL and DP_COMP_PAT register used to program DP
compliance pattern.
v1: Initial patch.
v2: used pipe instead of port in macro definition. [Manasi]
Reviewed-by: Manasi Navare
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_reg.h | 20
1 file changed, 20 i
This patch process phy compliance request by programming requested
vswing, pre-emphasis and test pattern.
v1: Initial patch.
v2: Fixes added during testing with test-scope. (Khaled/Clint/Manasi)
- pipe used as argument during registers programming instead of port.
- TRANS_CONF must be disable/enab
During DP phy compliance auto test mode, sink will request
combination of different test pattern with differnt level of
vswing, pre-emphasis. Function added to prepare for it.
Reviewed-by: Manasi Navare
Signed-off-by: Animesh Manna
---
.../drm/i915/display/intel_display_types.h| 1 +
drive
Driver changes mainly to process the request coming from Test equipment
as short pulse hpd interrupt to change link-pattern/v-swing/pre-emphasis
Complete auto test suite takes much lesser time than manual run.
Overall design:
--
Automate test request will come to source device as HDP s
To turn off preemption, we now require per-engine resets.
Signed-off-by: Chris Wilson
---
tests/i915/sysfs_heartbeat_interval.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/i915/sysfs_heartbeat_interval.c
b/tests/i915/sysfs_heartbeat_interval.c
index 0ba19b263..ef13
To exclude yynamic tests just use their group name?
Signed-off-by: Chris Wilson
Cc: Petri Latvala
---
tests/intel-ci/blacklist.txt | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tests/intel-ci/blacklist.txt b/tests/intel-ci/blacklist.txt
index 948b47569..184c23c37 10
Chris Wilson writes:
> Since the number of fence regs can vary dramactically between platforms,
> allocate the array on demand so we don't waste as much space.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 6 --
> drive
Since the fence registers control HW detiling through the GGTT
aperture, make them a part of the intel_ggtt under gt/
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/Makefile | 2 +-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
.../inte
Since the number of fence regs can vary dramactically between platforms,
allocate the array on demand so we don't waste as much space.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 6 --
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.
Since we always reload the fence register state on runtime resume,
having it explicitly in the S0ix resume code is redundant. Indeed, it
is not even being used!
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
1 file changed, 1 deletion(-)
diff
Make the GT responsible for restoring its fence when it wakes up from
suspend.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 ++
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 1 +
drivers/gpu/drm/i915/i915_drv.c | 4
driver
We need to calculate cdclk after watermarks/ddb has been calculated
as with recent hw CDCLK needs to be adjusted accordingly to DBuf
requirements, which is not possible with current code organization.
Setting CDCLK according to DBuf BW requirements and not just rejecting
if it doesn't satisfy BW r
No need to bump up CDCLK now, as it is now correctly
calculated, accounting for DBuf BW as BSpec says.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 12
1 file changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/
According to BSpec max BW per slice is calculated using formula
Max BW = CDCLK * 64. Currently when calculating min CDCLK we
account only per plane requirements, however in order to avoid
FIFO underruns we need to estimate accumulated BW consumed by
all planes(ddb entries basically) residing on tha
We need to calculate cdclk after watermarks/ddb has been calculated
as with recent hw CDCLK needs to be adjusted accordingly to DBuf
requirements, which is not possible with current code organization.
Setting CDCLK according to DBuf BW requirements and not just rejecting
if it doesn't satisfy BW r
It is illegal to wait on an another vma while holding the vm->mutex, as
that easily leads to ABBA deadlocks (we wait on a second vma that waits
on us to release the vm->mutex). So while the vm->mutex exists, move the
waiting outside of the lock into the async binding pipeline.
Signed-off-by: Chris
Allocate a few dma fence context id that we can use to associate async work
[for the CPU] launched on behalf of this context. For extra fun, we allow
a configurable concurrency width.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 4
drivers/gpu/drm/i915
If the caller allows and we do not have to wait for any signals,
immediately execute the work within the caller's process.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 2 +-
drivers/gpu/drm/i915/i915_sw_fence_work.c | 6 +-
drivers/gpu/drm/i915/i915_s
Only GPU activity via the GGTT fence is asynchronous, we know that we
control the CPU access directly, so we only need to wait for the GPU to
stop using the fence before we relinquish it.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 12
drivers/gpu/
We cached the number of vma bound to the object in order to speed up
shrinker decisions. This has been superseded by being more proactive in
removing objects we cannot shrink from the shrinker lists, and so we can
drop the clumsy attempt at atomically counting the bind count and
comparing it to the
Make a copy of the object tiling parameters at the point of grabbing the
fence.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 93 +++-
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h | 4 +
2 files changed, 37 insertions(+), 60 deletions(-)
diff --
Sometimes we have to be very careful not to allocate underneath a mutex
(or spinlock) and yet still want to track activity. Enter
i915_active_acquire_for_context(). This raises the activity counter on
i915_active prior to use and ensures that the fence-tree contains a slot
for the context.
Signed-
If we must revoke the fence because the VMA is no longer present, or
because the fence no longer applies, ensure that we do and convert it
into an error if we try but cannot.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c | 21 +++-
drivers/gpu/drm/i
It is reasonably common for userspace (even modern drivers like iris) to
reuse an active address for a new buffer. This would cause the
application to stall under its mutex (originally struct_mutex) until the
old batches were idle and it could synchronously remove the stale PTE.
However, we can que
In preparation for making eb_vma bigger and heavy to run inn parallel,
we need to stop apply an in-place swap() to reorder around ww_mutex
deadlocks. Keep the array intact and reorder the locks using a dedicated
list.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/gem/i915_gem_execbuffer.c
Since the fence registers control HW detiling through the GGTT
aperture, make them a part of the intel_ggtt under gt/
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/Makefile | 2 +-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +-
.../inte
Use a separate array allocation for the execbuf vma, so that we can
track their lifetime independently from the copy of the user arguments.
With luck, this has a secondary benefit of splitting the malloc size to
within reason and avoid vmalloc.
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/ge
Since the number of fence regs can vary dramactically between platforms,
allocate the array on demand so we don't waste as much space.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 6 --
drivers/gpu/drm/i915/gt/intel_ggtt_fencing.
Since we always reload the fence register state on runtime resume,
having it explicitly in the S0ix resume code is redundant. Indeed, it
is not even being used!
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.h | 1 -
1 file changed, 1 deletion(-)
diff
Make the GT responsible for restoring its fence when it wakes up from
suspend.
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 ++
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 1 +
drivers/gpu/drm/i915/i915_drv.c | 4
driver
On Mon, Mar 16, 2020 at 10:54:26AM +, Chris Wilson wrote:
> To exclude yynamic tests just use their group name?
Yes, the igt_subtest_with_dynamic("somename") macro creates a subtest
entry point just like igt_subtest, for the purposes of testlists and
blacklists.
>
> Signed-off-by: Chris Wi
On Thu, 27 Feb 2020, Jani Nikula wrote:
> Hi all -
>
> The following commits have been marked as Cc: stable or fixing something
> in v5.6-rc3 or earlier, but failed to cherry-pick to
> drm-intel-fixes. Please see if they are worth backporting, and please do
> so if they are.
New ones for -rc6:
0
This patch gives us the active pending request count which is yet
to be submitted to the GPU.
V2:
* Change 64-bit to atomic for request count. (Tvrtko Ursulin)
V3:
* Remove mutex for request count.
* Rebase.
* Fixes hitting underflow for predictive request. (Tvrtko Ursulin)
V4:
* Rebase.
V
Load classification is used for predictive governor to control
eu/slice/subslice based on workloads.
sysfs is provided to enable/disable the feature
V2:
* Fix code style.
* Move predictive_load_timer into a drm_i915_private
structure.
* Make generic function to set optimum config. (Tvrtko U
This patch sets improves GPU power consumption on Linux kernel based OS such as
Chromium OS, Ubuntu, etc. Following are the power savings.
Power savings on GLK-GT1 Bobba platform running on Chrome OS.
---|
App /KPI| % Power Benefit (mW) |
This patch will select optimum eu/slice/sub-slice configuration based on
type of load (low, medium, high) as input.
Based on our readings and experiments we have predefined set of optimum
configuration for each platform(CHT, KBL).
i915_gem_context_set_load_type will select optimum configuration fro
This patch gives us the active pending request count which is yet
to be submitted to the GPU.
V2:
* Change 64-bit to atomic for request count. (Tvrtko Ursulin)
V3:
* Remove mutex for request count.
* Rebase.
* Fixes hitting underflow for predictive request. (Tvrtko Ursulin)
V4:
* Rebase.
V
Load classification is used for predictive governor to control
eu/slice/subslice based on workloads.
sysfs is provided to enable/disable the feature
V2:
* Fix code style.
* Move predictive_load_timer into a drm_i915_private
structure.
* Make generic function to set optimum config. (Tvrtko U
drm/i915: Context aware user agnostic EU/Slice/Sub-slice control within kernel
This patch sets improves GPU power consumption on Linux kernel based OS such as
Chromium OS, Ubuntu, etc. Following are the power savings.
Power savings on GLK-GT1 Bobba platform running on Chrome OS.
-
This patch will select optimum eu/slice/sub-slice configuration based on
type of load (low, medium, high) as input.
Based on our readings and experiments we have predefined set of optimum
configuration for each platform(CHT, KBL).
i915_gem_context_set_load_type will select optimum configuration fro
Quoting Ankit Navik (2020-03-16 13:29:49)
> This patch gives us the active pending request count which is yet
> to be submitted to the GPU.
>
> V2:
> * Change 64-bit to atomic for request count. (Tvrtko Ursulin)
>
> V3:
> * Remove mutex for request count.
> * Rebase.
> * Fixes hitting underfl
On Wed, 2020-03-11, Lyude Paul wrote:
>On Tue, 2020-01-07 at 01:41 +0800, Lee Shawn C wrote:
>> Driver report physcial bandwidth for max dot clock rate.
>> It would caused compatibility issue sometimes when physical bandwidth
>> exceed MST hub output ability.
>>
>> For example, here is a MST hu
On Fri, Mar 13, 2020 at 09:17:42AM -0300, Jason Gunthorpe wrote:
> On Fri, Mar 13, 2020 at 04:21:39AM -0700, Christoph Hellwig wrote:
> > On Thu, Mar 12, 2020 at 11:19:28AM -0300, Jason Gunthorpe wrote:
> > > The non-page scatterlist is also a big concern for RDMA as we have
> > > drivers that want
On Mon, Mar 16, 2020 at 10:41:42AM +0100, Christian König wrote:
> Well I would prefer if the drivers can somehow express their requirements
> and get IOVA structures already in the form they need.
>
> Converting the IOVA data from one form to another is sometimes quite costly.
> Especially when i
On Thu, Mar 12, 2020 at 11:19:28AM -0300, Jason Gunthorpe wrote:
> The non-page scatterlist is also a big concern for RDMA as we have
> drivers that want the page list, so even if we did as this series
> contemplates I'd have still have to split the drivers and create the
> notion of a dma-only SGL
== Series Details ==
Series: drm/i915: Port sync for skl+
URL : https://patchwork.freedesktop.org/series/74691/
State : failure
== Summary ==
Applying: drm/i915/mst: Use .compute_config_late() to compute master transcoder
Applying: drm/i915: Move TRANS_DDI_FUNC_CTL2 programming where it belong
== Series Details ==
Series: drm/edid: DisplayID parser fixes
URL : https://patchwork.freedesktop.org/series/74689/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8137 -> Patchwork_16968
Summary
---
**SUCCESS**
No
If the current node/entry location is occupied, and the object is not
pinned, try assigning it some free space. We cannot wait here, so if in
doubt, we unreserve and try to grab all at once.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 13 +++--
1 file
== Series Details ==
Series: drm/i915/edp: Ignore short pulse when panel powered off (rev2)
URL : https://patchwork.freedesktop.org/series/74265/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8137 -> Patchwork_16970
Summary
On Mon, Mar 16, 2020 at 09:31:32AM +0100, Daniel Vetter wrote:
> On Tue, Mar 10, 2020 at 06:01:06PM +0200, Ville Syrjälä wrote:
> > On Tue, Feb 25, 2020 at 12:35:41PM +0530, Pankaj Bharadiya wrote:
> > > Introduce new scaling filter property to allow userspace to select
> > > the driver's default s
== Series Details ==
Series: series starting with [v6,1/3] drm/i915/perf: remove generated code
URL : https://patchwork.freedesktop.org/series/74702/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e31b72062fe2 drm/i915/perf: remove generated code
-:24: WARNING:UNKNOWN_COMMIT_ID:
== Series Details ==
Series: series starting with [v6,1/3] drm/i915/perf: remove generated code
URL : https://patchwork.freedesktop.org/series/74702/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8137 -> Patchwork_16971
Sum
== Series Details ==
Series: series starting with [1/7] drm/i915: Move GGTT fence registers under gt/
URL : https://patchwork.freedesktop.org/series/74703/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
cfd159dc30dd drm/i915: Move GGTT fence registers under gt/
-:6: WARNING:TYPO
== Series Details ==
Series: series starting with [1/7] drm/i915: Move GGTT fence registers under gt/
URL : https://patchwork.freedesktop.org/series/74703/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fence_r
Beware that the context may already be closed as we try to lookup an
engine.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1389
Fixes: 130a95e9098e ("drm/i915/gem: Consolidate ctx->engines[] release")
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
---
drivers/gpu/dr
== Series Details ==
Series: drm/i915/gt: convert to struct drm_device based logging macros.
URL : https://patchwork.freedesktop.org/series/74707/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6cfa7991dd93 drm/i915/ggtt: convert to drm_device based logging macros.
-:84: WARNING
== Series Details ==
Series: series starting with [1/7] drm/i915: Move GGTT fence registers under gt/
URL : https://patchwork.freedesktop.org/series/74703/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8137 -> Patchwork_16972
===
== Series Details ==
Series: drm/i915/gt: convert to struct drm_device based logging macros.
URL : https://patchwork.freedesktop.org/series/74707/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8137 -> Patchwork_16973
Summar
Hey Ville and others,
On Fri, 13 Mar 2020, Kai Vehmanen wrote:
> On Fri, 13 Mar 2020, Ville Syrjälä wrote:
> Now thinking of another possibility, is it possible to hook code to
> power-up of power domains? E.g. can I hook custom code which is executed
[...]
> If we could reprogram AUD_FREQ_CNTRL
== Series Details ==
Series: drm/i915/dp: Add dpcd link_rate quirk for Apple 15" MBP 2017 (rev3)
URL : https://patchwork.freedesktop.org/series/74100/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3d21f79cfaf6 drm/i915/dp: Add dpcd link_rate quirk for Apple 15" MBP 2017 (v3)
-:
== Series Details ==
Series: drm/i915/dp: Add dpcd link_rate quirk for Apple 15" MBP 2017 (rev3)
URL : https://patchwork.freedesktop.org/series/74100/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8137 -> Patchwork_16974
Su
Looks good. Thanks for cleaning this up.
With s/mutex_lock/mutex_unlock/ below:
Reviewed-by: Umesh Nerlige Ramappa
Thanks,
Umesh
On Sat, Mar 14, 2020 at 12:33:29PM +0200, Lionel Landwerlin wrote:
A little bit of history :
Back when i915-perf was introduced (4.13), there was no way to
dy
== Series Details ==
Series: tests/gem_userptr_blits: Refresh other now MMAP_GTT dependent subtests
URL : https://patchwork.freedesktop.org/series/74730/
State : failure
== Summary ==
Applying: tests/gem_userptr_blits: Refresh readonly-mmap-unsync exercise
error: sha1 information is lacking or
On Thu, 12 Mar 2020 16:04:59 -0700, Umesh Nerlige Ramappa wrote:
>
> From: Lionel Landwerlin
>
> We're about to introduce an options to open the perf stream, giving
> the user ability to configure how often it wants the kernel to poll
> the OA registers for available data.
>
> Right now the workar
== Series Details ==
Series: DP Phy compliance auto test (rev7)
URL : https://patchwork.freedesktop.org/series/71121/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8137 -> Patchwork_16976
Summary
---
**SUCCESS**
N
== Series Details ==
Series: series starting with [CI,1/4] drm/i915: Move GGTT fence registers under
gt/
URL : https://patchwork.freedesktop.org/series/74738/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
24d226d21d96 drm/i915: Move GGTT fence registers under gt/
-:47: WARNING
== Series Details ==
Series: series starting with [CI,1/4] drm/i915: Move GGTT fence registers under
gt/
URL : https://patchwork.freedesktop.org/series/74738/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
Error: Cannot open file ./drivers/gpu/drm/i915/i915_gem_fen
== Series Details ==
Series: series starting with [CI,1/4] drm/i915: Move GGTT fence registers under
gt/
URL : https://patchwork.freedesktop.org/series/74738/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8137 -> Patchwork_16977
===
== Series Details ==
Series: Consider DBuf bandwidth when calculating CDCLK
URL : https://patchwork.freedesktop.org/series/74739/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
70a984e1e806 drm/i915: Decouple cdclk calculation from modeset checks
01a1b24738fd drm/i915: Adjust CD
On Thu, 12 Mar 2020 16:05:00 -0700, Umesh Nerlige Ramappa wrote:
>
> From: Lionel Landwerlin
>
> This isn't really gen specific stuff, so just move it to the common
> code.
It seems pollin is not the only member which is not gen specific but is
initialized in gen specific code. Anyway any other s
== Series Details ==
Series: series starting with [01/15] drm/i915: Move GGTT fence registers under
gt/
URL : https://patchwork.freedesktop.org/series/74740/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2bf8a0072a07 drm/i915: Move GGTT fence registers under gt/
-:47: WARNING:
== Series Details ==
Series: Consider DBuf bandwidth when calculating CDCLK
URL : https://patchwork.freedesktop.org/series/74739/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8137 -> Patchwork_16978
Summary
---
**FA
Francisco Jerez writes:
> Tvrtko Ursulin writes:
>[...]
>> Some time ago we entertained the idea of GPU "load average", where that
>> was defined as a count of runnable requests (so batch buffers). How
>> that, more generic metric, would behave here if used as an input signal
>> really intrig
Apparently we do try and attach a fence to an invalid vma (during
execbuf) so we cannot simply assert it never happens and report EINVAL
instead.
Fixes: dec9cf9ee8cb ("drm/i915/gt: Pull restoration of GGTT fences underneath
the GT")
Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
---
dr
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