On Mon, 28 Oct 2019, Matt Roper wrote:
> VBT revision 229 adds a new "Generic DTD" block 58 and deprecates the
> old LFP panel mode data in block 42. Let's start parsing this block to
> fill in the panel fixed mode on devices with a >=229 VBT.
>
> v2:
> * Update according to the recent updates:
Use this in all the places where we try to acquire planes after the planes
atomic_check().
In case of intel_modeset_all_pipes() this is not yet done after atomic_check,
but seems like it will be in the future. To add some paranoia, add all planes
rather than active planes, because of bigjoiner and
We are still looking at drm_crtc_state in a few places, convert those
to use intel_crtc_state instead.
Changes since v1:
- Move to before uapi/hw split.
- Add hunks for intel_pm.c as well.
Changes since v2:
- Incorporate Ville's feedback.
Signed-off-by: Maarten Lankhorst
Reviewed-by: Matt Roper
Prepare to split up hw and uapi machinally, by adding a uapi and
hw alias. We will remove the base in a bit. This is a split from the
original uapi/hw patch, which did it all in one go.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c | 8 --
drivers/gpu/dr
Split up crtc_state->base to hw where appropriate. This is done using the
following patch:
@@
struct intel_crtc_state *T;
identifier x =~
"^(active|enable|degamma_lut|gamma_lut|ctm|mode|adjusted_mode)$";
@@
-T->base.x
+T->hw.x
@@
struct drm_crtc_state *T;
identifier x =~
"^(active|enable|degam
Now that we separated everything into uapi and hw, it's
time to make the split definitive. Remove the union and
make a copy of the hw state on modeset and fastset.
Color blobs are copied in crtc atomic_check(), right
before color management is checked.
Changes since v1:
- Copy all blobs immediate
Split up plane_state->base to hw. This is done using the following patch:
@@
struct intel_plane_state *T;
identifier x =~
"^(crtc|fb|alpha|pixel_blend_mode|rotation|color_encoding|color_range)$";
@@
-T->base.x
+T->hw.x
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_ato
Split up plane_state->base to uapi. This is done using the following patch,
ran after the previous commit that splits out any hw references:
@@
struct intel_plane_state *T;
identifier x;
@@
-T->base.x
+T->uapi.x
@@
struct intel_plane_state *T;
@@
-T->base
+T->uapi
Signed-off-by: Maarten Lankhors
Prepare to split up hw and uapi machinally, by adding a uapi and
hw alias. We will remove the base in a bit. This is a split from the
original uapi/hw patch, which did it all in one go.
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/display/intel_atomic_plane.c| 16
.
intel_get_load_detect_pipe() needs to set uapi active,
uapi enable is set by the call to drm_atomic_set_mode_for_crtc(),
so we can remove it.
intel_pipe_config_compare() needs to look at hw state, but I didn't
change spatch to look at it. It's easy enough to do manually.
intel_atomic_check() defi
get_crtc_from_states() is called before plane_state is copied to uapi,
so use the uapi state there.
intel_legacy_cursor_update() could probably get away with looking at
the hw state, but for clarity look at the uapi state always
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/
Splitting plane state is easier than splitting crtc_state,
before plane check we copy the drm properties to hw so we can
do the same in bigjoiner later on.
We copy the state after we did all the modeset handling, but fortunately
i915 seems to be split correctly and nothing during modeset looks
at
On 10/23/2019 9:07 PM, Jason Wang wrote:
This patch implements basic support for mdev driver that supports
virtio transport for kernel virtio driver.
Signed-off-by: Jason Wang
---
drivers/vfio/mdev/mdev_core.c| 20
drivers/vfio/mdev/mdev_private.h | 2 +
include/linux/mdev.h
On Tue, 29 Oct 2019 08:31:22 +0800
Changbin Du wrote:
> Here python is different from C. Both empty string and None are False in
> python.
> Note such condition is common in python.
Treating both as a False value is reasonably common. Treating them
elsewhere in the same code block as separate
commit 'a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS)'
introduced new PCI ID that CML support. But some PCI
IDs were removed from CML IDs in BSpec.
v2: remove some inaccurate descriptions.
v3: fix typo.
v4: add missing version number.
v5: no update.
v6: update patch comment.
Cc: Rodrigo Vivi
Cc:
U series device need different DDI buffer setup for eDP
and DP. If driver did not recognize ULT id proerply.
The setting for H and S series would be used.
v2: add missing comma in subplatform_ult_ids[].
v3: no update.
v4: no update.
v5: no update.
v6: no update.
Cc: Rodrigo Vivi
Cc: Jani Nikula
== Series Details ==
Series: series starting with [CI,01/12] drm/i915: Introduce
intel_atomic_get_plane_state_after_check(), v2.
URL : https://patchwork.freedesktop.org/series/68694/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
874fbe7ef3ea drm/i915: Introduce intel_atomic_ge
Quoting Jani Nikula (2019-10-28 12:38:20)
> Mostly for improved documentation, convert the debug category macros
> into an enum. Drop unused DRM_UT_NONE. Document previously undocumented
> categories.
>
> Signed-off-by: Jani Nikula
> +enum drm_debug_category {
> + /**
> +* @DRM_U
== Series Details ==
Series: series starting with [CI,01/12] drm/i915: Introduce
intel_atomic_get_plane_state_after_check(), v2.
URL : https://patchwork.freedesktop.org/series/68694/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7208 -> Patchwork_15042
===
>-Original Message-
>From: Intel-gfx On Behalf Of Ville
>Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 1/9] drm/i915: Expose 10:10:10 XRGB formats on SNB-
>BDW sprites
>
>From: Ville Syrjälä
>
>SNB-BDW support 10:10:10
== Series Details ==
Series: drm/i915: Avoid HPD poll detect triggering a new detect cycle
URL : https://patchwork.freedesktop.org/series/68644/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7201_full -> Patchwork_15019_full
Execlists uses a scheduling quantum (a timeslice) to alternate execution
between ready-to-run contexts of equal priority. This ensures that all
users (though only if they of equal importance) have the opportunity to
run and prevents livelocks where contexts may have implicit ordering due
to userspa
On Mon, Oct 28, 2019 at 11:24:22AM +0200, Jani Nikula wrote:
> On Fri, 25 Oct 2019, Changbin Du wrote:
> > On Fri, Oct 25, 2019 at 09:57:48AM +0300, Jani Nikula wrote:
> >> On Thu, 24 Oct 2019, Jonathan Corbet wrote:
> >> > On Sun, 20 Oct 2019 21:17:17 +0800
> >> > Changbin Du wrote:
> >> >
> >>
On Mon, 28 Oct 2019 at 14:16, Imre Deak wrote:
>
> For the HPD interrupt functionality the HW depends on power wells in the
> display core domain to be on. Accordingly when enabling these power
> wells the HPD polling logic will force an HPD detection cycle to account
> for hotplug events that may
On Wed, 07 Aug 2019, Daniele Ceraolo Spurio
wrote:
> I've been trying to identify MMIO ranges to clearly define what belongs
> to display_uncore to do a check on access, but there are lots of
> exceptions and differences across gens (with a few more coming with TGL),
> so I don't think that's a v
On Tue, 29 Oct 2019, Joonas Lahtinen wrote:
> Quoting Jani Nikula (2019-10-28 12:38:20)
>> Mostly for improved documentation, convert the debug category macros
>> into an enum. Drop unused DRM_UT_NONE. Document previously undocumented
>> categories.
>>
>> Signed-off-by: Jani Nikula
>
>
>
>> +en
== Series Details ==
Series: series starting with [v6,1/2] drm/i915/cml: Remove unsupport PCI ID
URL : https://patchwork.freedesktop.org/series/68698/
State : failure
== Summary ==
Applying: drm/i915/cml: Remove unsupport PCI ID
Applying: drm/i915/cml: Separate U series pci id from origianl li
== Series Details ==
Series: drm/i915/gt: Make timeslice duration configurable
URL : https://patchwork.freedesktop.org/series/68701/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7208 -> Patchwork_15044
Summary
---
*
From: Michal Wajdeczko
HWS placement restrictions can't just rely on HAS_LLC flag.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Auld
Cc: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/
Since we have no way access it from the CPU. For such cases just
fallback to internal objects.
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/gt/intel_ring.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring.c
b/drivers/gpu/drm/i915/
From: Daniele Ceraolo Spurio
If the aperture is not available in HW we can't use a ggtt slot and wc
copy, so fall back to regular kmap.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 19
dr
From: Daniele Ceraolo Spurio
Skip both setup and cleanup of the aperture mapping if the HW doesn't
have an aperture bar.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 31 ++---
1 file changed, 19 insertions(
From: Daniele Ceraolo Spurio
The following patches in the series will use it to avoid certain
operations when the mappable aperture is not available in HW.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.h | 5 +
1 file changed, 5 in
From: Daniele Ceraolo Spurio
We can't fence anything without aperture.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drive
We may be missing support for the mappable aperture on some platforms.
Signed-off-by: Matthew Auld
Cc: Daniele Ceraolo Spurio
---
.../drm/i915/gem/selftests/i915_gem_coherency.c| 5 -
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 6 ++
drivers/gpu/drm/i915/gt/selftest_hangc
>-Original Message-
>From: Intel-gfx On Behalf Of Ville
>Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 2/9] drm/i915: Expose alpha formats on VLV/CHV
>primary
>planes
>
>From: Ville Syrjälä
>
>Currently we expose VLV/
Quoting Matthew Auld (2019-10-29 09:58:50)
> From: Daniele Ceraolo Spurio
>
> The following patches in the series will use it to avoid certain
> operations when the mappable aperture is not available in HW.
>
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Matthew Auld
Reviewed-by: Ch
Quoting Matthew Auld (2019-10-29 09:58:51)
> From: Daniele Ceraolo Spurio
>
> Skip both setup and cleanup of the aperture mapping if the HW doesn't
> have an aperture bar.
>
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Matthew Auld
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 31
On Mon, Oct 28, 2019 at 06:10:14PM -0700, José Roberto de Souza wrote:
> Non-TC ports always have tc_mode == TC_PORT_TBT_ALT so it was
> switching aux to TC mode for all combo-phy ports, happily this did
> not caused any issue but is better follow BSpec.
> Also this is reserved bit before ICL.
>
>
Quoting Matthew Auld (2019-10-29 09:58:52)
> From: Daniele Ceraolo Spurio
>
> We can't fence anything without aperture.
>
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Stuart Summers
> Signed-off-by: Matthew Auld
Neat.
Reviewed-by: Chris Wilson
-Chris
Quoting Matthew Auld (2019-10-29 09:58:53)
> From: Daniele Ceraolo Spurio
>
> If the aperture is not available in HW we can't use a ggtt slot and wc
> copy, so fall back to regular kmap.
>
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Abdiel Janulgue
> Signed-off-by: Matthew Auld
>
Quoting Matthew Auld (2019-10-29 09:58:54)
> From: Michal Wajdeczko
>
> HWS placement restrictions can't just rely on HAS_LLC flag.
>
> Signed-off-by: Michal Wajdeczko
> Signed-off-by: Matthew Auld
> Cc: Daniele Ceraolo Spurio
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
> 1 fil
Quoting Matthew Auld (2019-10-29 09:58:55)
> Since we have no way access it from the CPU. For such cases just
> fallback to internal objects.
>
> Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilson
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.fr
Quoting Matthew Auld (2019-10-29 09:58:56)
> We may be missing support for the mappable aperture on some platforms.
>
> Signed-off-by: Matthew Auld
> Cc: Daniele Ceraolo Spurio
> ---
> .../drm/i915/gem/selftests/i915_gem_coherency.c| 5 -
> drivers/gpu/drm/i915/gem/selftests/i915_gem_m
== Series Details ==
Series: series starting with [1/6] drm/i915: Fix i845/i865 cursor width
URL : https://patchwork.freedesktop.org/series/68646/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7201_full -> Patchwork_15021_full
==
== Series Details ==
Series: series starting with [1/7] drm/i915: define i915_ggtt_has_aperture
URL : https://patchwork.freedesktop.org/series/68705/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6d8f88fa8405 drm/i915: define i915_ggtt_has_aperture
d802efde66e4 drm/i915: do not
== Series Details ==
Series: drm/i915/selftests: Check a few more fixed locations within the context
image (rev2)
URL : https://patchwork.freedesktop.org/series/68611/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7201_full -> Patchwork_15022_full
Name of the i915 module parameter providing fault injection function is
changing for consistency with a new convention of naming i915 driver
internal functions called from the driver PCI .probe entry point. Adjust
the test to use the new name.
Suggested-by: Joonas Lahtinen
Signed-off-by: Janusz
Name of the i915 module parameter providing fault injection function is
changing for consistency with a new convention of naming i915 driver
internal functions called from the driver PCI .probe entry point. Adjust
the test to use the new name.
v2: * add R-b (thanks Chris),
* add cover letter
== Series Details ==
Series: series starting with [1/7] drm/i915: define i915_ggtt_has_aperture
URL : https://patchwork.freedesktop.org/series/68705/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: define i915_ggtt_has_aperture
Okay!
Commit:
Commit f2db53f14d3d ("drm/i915: Replace "_load" with "_probe"
consequently") deliberately left the name of the module parameter
unchanged as that would require a corresponding change on IGT size.
Now as the IGT side change has been submitted, complete the switch to
the "probe" nomenclature.
Sugges
Commit 50d84418f586 ("drm/i915: Add i915 to i915_inject_probe_failure")
introduced new functions unfortunately named incompatibly with rules
established by commit f2db53f14d3d ("drm/i915: Replace "_load" with
"_probe" consequently"). Fix it for consistency.
Suggested-by: Michał Wajdeczko
Signed-
Test-with: <20191029101751.5848-2-janusz.krzyszto...@linux.intel.com>
The purpose is:
* to fix incompatible names of new functions introduced meanwhile,
* to complete postponed rename of module parameter.
v2: * drop unnecessary statement about custom user applications from
commit message of
== Series Details ==
Series: drm/i915: Avoid HPD poll detect triggering a new detect cycle (rev2)
URL : https://patchwork.freedesktop.org/series/68644/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7205 -> Patchwork_15031
S
We may be missing support for the mappable aperture on some platforms.
Signed-off-by: Matthew Auld
Cc: Daniele Ceraolo Spurio
Reviewed-by: Chris Wilson
---
.../drm/i915/gem/selftests/i915_gem_coherency.c| 7 ++-
drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c | 6 ++
drivers/g
From: Daniele Ceraolo Spurio
The following patches in the series will use it to avoid certain
operations when the mappable aperture is not available in HW.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.h | 5
Since we have no way access it from the CPU. For such cases just
fallback to internal objects.
Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_ring.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring
From: Daniele Ceraolo Spurio
Skip both setup and cleanup of the aperture mapping if the HW doesn't
have an aperture bar.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 31 ++---
1 f
From: Daniele Ceraolo Spurio
If the aperture is not available in HW we can't use a ggtt slot and wc
copy, so fall back to regular kmap.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_ge
From: Michal Wajdeczko
HWS placement restrictions can't just rely on HAS_LLC flag.
Signed-off-by: Michal Wajdeczko
Signed-off-by: Matthew Auld
Cc: Daniele Ceraolo Spurio
Acked-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-
From: Daniele Ceraolo Spurio
We can't fence anything without aperture.
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Stuart Summers
Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_fence_reg.c | 6 --
1 file changed, 4 insertions(+), 2 delet
>-Original Message-
>From: Intel-gfx On Behalf Of Ville
>Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 4/9] drm/i915: Expose C8 on VLV/CHV sprite planes
>
>From: Ville Syrjälä
>
>VLV/CHV sprite planes also support the
== Series Details ==
Series: series starting with [1/7] drm/i915: define i915_ggtt_has_aperture
URL : https://patchwork.freedesktop.org/series/68705/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7208 -> Patchwork_15045
Sum
The intel_dp_link_training.h include has no need or place in
intel_display.h. Include it in intel_display.c instead.
Cc:
Cc: Manasi Navare
Fixes: eadf6f9170d5 ("drm/i915/display/icl: Enable master-slaves in trans port
sync")
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_di
On 2019/10/29 下午3:42, Zhu Lingshan wrote:
>>
>> + void (*set_status)(struct mdev_device *mdev, u8 status);
>
> Hi Jason
>
> Is it possible to make set_status() return an u8 or bool, because this
> may fail in real hardware. Without a returned code, I am not sure
> whether it is a good idea to
Not for merging, for demo only.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_audio.c | 113 +++--
1 file changed, 59 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c
b/drivers/gpu/drm/i915/display/intel_audio.c
index 85
Add convenience helpers for the most common uncore operations with
struct drm_i915_private * as context rather than struct intel_uncore *.
The goal is to replace all instances of I915_READ(),
I915_POSTING_READ(), and I915_WRITE() in display/ with these, to finally
be able to get rid of the implici
On Tue, 29 Oct 2019, Jani Nikula wrote:
> The intel_dp_link_training.h include has no need or place in
> intel_display.h. Include it in intel_display.c instead.
>
> Cc:
Whoops, obviously to be removed before merging.
BR,
Jani.
>
> Cc: Manasi Navare
> Fixes: eadf6f9170d5 ("drm/i915/display/icl:
== Series Details ==
Series: drm/i915: Conclude load -> probe naming convention switch (rev2)
URL : https://patchwork.freedesktop.org/series/67454/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2fff720f7c40 drm/i915: Fix i915_inject_load_error() name to read *_probe_*
-:11: ERR
>-Original Message-
>From: Intel-gfx On Behalf Of Ville
>Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 3/9] drm/i915: Add missing 10bpc formats for pipe B
>sprites on CHV
>
>From: Ville Syrjälä
>
>CHV pipe B sprites ga
>-Original Message-
>From: Intel-gfx On Behalf Of Ville
>Syrjala
>Sent: Wednesday, October 9, 2019 4:14 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH v2 5/9] drm/i915: Add 10bpc formats with alpha for
>icl+
>
>From: Ville Syrjälä
>
>ICL+ again supports alpha ble
>-Original Message-
>From: Intel-gfx On Behalf Of Ville
>Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 6/9] drm/i915: Sort format arrays consistently
>
>From: Ville Syrjälä
>
>Let's try to keep the pixel format arrays
== Series Details ==
Series: series starting with [v2,1/7] drm/i915: define i915_ggtt_has_aperture
URL : https://patchwork.freedesktop.org/series/68710/
State : failure
== Summary ==
Applying: drm/i915: define i915_ggtt_has_aperture
Using index info to reconstruct a base tree...
M driver
On Mon, 28 Oct 2019 22:25:27 +0100, wrote:
From: Don Hiatt
On some platforms (e.g. KBL) that do not support GuC submission, but
the user enabled the GuC communication (e.g for HuC authentication)
calling the GuC EXIT_S_STATE action results in lose of ability to
enter RC6. We can remove the Gu
Quoting Janusz Krzysztofik (2019-10-29 10:17:51)
> Name of the i915 module parameter providing fault injection function is
> changing for consistency with a new convention of naming i915 driver
> internal functions called from the driver PCI .probe entry point. Adjust
> the test to use the new nam
== Series Details ==
Series: drm/i915/display: only include intel_dp_link_training.h where needed
URL : https://patchwork.freedesktop.org/series/68711/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1b222834c572 drm/i915/display: only include intel_dp_link_training.h where
need
From: Janusz Krzysztofik
Name of the i915 module parameter providing fault injection function is
changing for consistency with a new convention of naming i915 driver
internal functions called from the driver PCI .probe entry point. Adjust
the test to use the new name.
[ickle: keep the old param
== Series Details ==
Series: drm/i915: Avoid HPD poll detect triggering a new detect cycle (rev2)
URL : https://patchwork.freedesktop.org/series/68644/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7205 -> Patchwork_15031
S
>-Original Message-
>From: Intel-gfx On Behalf Of Ville
>Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
>
>From: Ville Syrjälä
>
>According to the spec color keying is not support
== Series Details ==
Series: drm/i915/execlists: Simply walk back along request timeline on reset
(rev6)
URL : https://patchwork.freedesktop.org/series/68601/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7203_full -> Patchwork_15023_full
=
== Series Details ==
Series: series starting with [1/2] drm/i915/selftests: Initialise ret
URL : https://patchwork.freedesktop.org/series/68662/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7203_full -> Patchwork_15025_full
On 10/25/2019 8:52 PM, Animesh Manna wrote:
On 10/17/2019 9:28 PM, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
It sounds like the hardware only needs the DSB object to be in global
GTT
and not in the mappable region.
Currently tested and working without any regression, waiting for
confi
>-Original Message-
>From: Intel-gfx On Behalf Of Ville
>Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 8/9] drm/i915: Do not enable HDR mode when color
>keying is active
>
>From: Ville Syrjälä
>
>The spec says that col
From: Ville Syrjälä
We always pass mode==NULL to intel_get_load_detect_pipe(). Remove
the pointless function argument.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_crt.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 7 ++-
drivers/gpu/drm/i915/display/in
On Tue, Oct 29, 2019 at 08:22:21AM +0100, Maarten Lankhorst wrote:
> intel_get_load_detect_pipe() needs to set uapi active,
> uapi enable is set by the call to drm_atomic_set_mode_for_crtc(),
> so we can remove it.
>
> intel_pipe_config_compare() needs to look at hw state, but I didn't
> change sp
>-Original Message-
>From: Intel-gfx On Behalf Of Ville
>Syrjala
>Sent: Tuesday, October 8, 2019 9:45 PM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH 9/9] drm/i915: Eliminate redundancy in
>intel_primary_plane_create()
>
>From: Ville Syrjälä
>
>Lots of redundant as
On Tue, 29 Oct 2019, Thierry Reding wrote:
> From: Thierry Reding
>
> The current link status contains bytes 0x202 through 0x207, but we also
> want to make sure to include the DP_ADJUST_REQUEST_POST_CURSOR2 (0x20c)
> so that the post-cursor adjustment can be queried during link training.
We don
Hi Chris,
On Tuesday, October 29, 2019 1:49:26 PM CET Chris Wilson wrote:
> From: Janusz Krzysztofik
>
> Name of the i915 module parameter providing fault injection function is
> changing for consistency with a new convention of naming i915 driver
> internal functions called from the driver PCI
>-Original Message-
>From: Shankar, Uma
>Sent: Tuesday, October 29, 2019 6:38 PM
>To: Ville Syrjala ;
>intel-gfx@lists.freedesktop.org
>Subject: RE: [Intel-gfx] [PATCH 7/9] drm/i915: Reject ckey+fp16 on skl+
>
>
>
>>-Original Message-
>>From: Intel-gfx On Behalf Of
>>Ville Syrja
Quoting Janusz Krzysztofik (2019-10-29 13:35:48)
> > diff --git a/tests/i915/i915_module_load.c b/tests/i915/i915_module_load.c
> > index f42083f53..7d9a5cfd2 100644
> > --- a/tests/i915/i915_module_load.c
> > +++ b/tests/i915/i915_module_load.c
> > @@ -350,11 +350,17 @@ igt_main
> > }
> >
== Series Details ==
Series: drm/print: cleanup and new drm_device based logging (rev3)
URL : https://patchwork.freedesktop.org/series/67795/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7204_full -> Patchwork_15026_full
S
From: Thierry Reding
The current link status contains bytes 0x202 through 0x207, but we also
want to make sure to include the DP_ADJUST_REQUEST_POST_CURSOR2 (0x20c)
so that the post-cursor adjustment can be queried during link training.
Reported-by: coverity-bot
Addresses-Coverity-ID: 1487366 (
== Series Details ==
Series: series starting with [v2,1/5] drm/dsi: clean up DSI data type
definitions
URL : https://patchwork.freedesktop.org/series/68664/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7204_full -> Patchwork_15027_full
===
On Tue, Oct 29, 2019 at 03:32:41PM +0200, Jani Nikula wrote:
> On Tue, 29 Oct 2019, Thierry Reding wrote:
> > From: Thierry Reding
> >
> > The current link status contains bytes 0x202 through 0x207, but we also
> > want to make sure to include the DP_ADJUST_REQUEST_POST_CURSOR2 (0x20c)
> > so tha
== Series Details ==
Series: drm/i915/execlists: Use vfunc to check engine submission mode (rev2)
URL : https://patchwork.freedesktop.org/series/68654/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7204_full -> Patchwork_15029_full
=
== Series Details ==
Series: drm/i915/tgl: add support to one DP-MST stream
URL : https://patchwork.freedesktop.org/series/68671/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7204_full -> Patchwork_15030_full
Summary
-
== Series Details ==
Series: drm/i915: Conclude load -> probe naming convention switch (rev2)
URL : https://patchwork.freedesktop.org/series/67454/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7209 -> Patchwork_15046
Summa
== Series Details ==
Series: series starting with [RFC,1/2] drm/i915: add display uncore helpers
URL : https://patchwork.freedesktop.org/series/68713/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
dfb3731d13b1 drm/i915: add display uncore helpers
-:28: WARNING:FILE_PATH_CHANGES
Gen12 only support a single report format :
I915_OA_FORMAT_A32u40_A4u32_B8_C8
Signed-off-by: Lionel Landwerlin
Fixes: 00a7f0d7155c ("drm/i915/tgl: Add perf support on TGL")
---
drivers/gpu/drm/i915/selftests/i915_perf.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/driver
On Tue, Oct 29, 2019 at 08:22:24AM +0100, Maarten Lankhorst wrote:
> Now that we separated everything into uapi and hw, it's
> time to make the split definitive. Remove the union and
> make a copy of the hw state on modeset and fastset.
>
> Color blobs are copied in crtc atomic_check(), right
> be
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