On Thu, 24 Oct 2019, Chris Wilson wrote:
> We would like some freedom to break the user API/ABI for future HW but
> yet still expose the driver for upstream development on that HW.
> Currently, we have the i915.force_probe module parameter to avoid binding
> to HW while the driver is under develop
commit 'a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS)'
introduced new PCI ID that CML support. But some sku
is not support yet so remove them avoid unexpected issue.
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Lucas De Marchi
Cc: Anusha Srivatsa
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
incl
U series device need different DDI buffer setup for eDP
and DP. If driver did not recognize ULT id proerply.
The setting for H and S series would be used.
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Lucas De Marchi
Cc: Anusha Srivatsa
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
drivers/gpu/drm
On Fri, 25 Oct 2019, Lee Shawn C wrote:
> commit 'a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS)'
> introduced new PCI ID that CML support. But some sku
> is not support yet so remove them avoid unexpected issue.
Please elaborate.
BR,
Jani.
>
> Cc: Rodrigo Vivi
> Cc: Jani Nikula
> Cc: Lucas D
On Fri, 25 Oct 2019, Lee Shawn C wrote:
> U series device need different DDI buffer setup for eDP
> and DP. If driver did not recognize ULT id proerply.
> The setting for H and S series would be used.
>
> Cc: Rodrigo Vivi
> Cc: Jani Nikula
> Cc: Lucas De Marchi
> Cc: Anusha Srivatsa
> Cc: Coop
Op 24-10-2019 om 17:21 schreef Ville Syrjälä:
> On Thu, Oct 24, 2019 at 02:47:59PM +0200, Maarten Lankhorst wrote:
>> Now that we separated everything into uapi and hw, it's
>> time to make the split definitive. Remove the union and
>> make a copy of the hw state on modeset and fastset.
>>
>> Color
== Series Details ==
Series: series starting with [1/2] drm/i915/cml: Remove unsupport PCI ID
URL : https://patchwork.freedesktop.org/series/68547/
State : failure
== Summary ==
Applying: drm/i915/cml: Remove unsupport PCI ID
Applying: drm/i915/cml: Separate U sereis pci id from origianl list.
From: Tvrtko Ursulin
Intel_lrc.c is the only caller and so to avoid some header file ordering
issues in future patches move these two over there.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine.h | 55 --
drivers/gpu/drm/i915/gt/intel_lrc.c| 5
Quoting Chris Wilson (2019-10-24 14:40:18)
> Our existing behaviour is to allow contexts and their GPU requests to
> persist past the point of closure until the requests are complete. This
> allows clients to operate in a 'fire-and-forget' manner where they can
> setup a rendering pipeline and hand
Quoting Tvrtko Ursulin (2019-10-25 10:09:52)
> From: Tvrtko Ursulin
>
> Intel_lrc.c is the only caller and so to avoid some header file ordering
> issues in future patches move these two over there.
How much pain would you feel if we did intel_lrc.c +
intel_execlists_submission.c earlier rather
BAT is growing a little fat and CI is under pressure and needs to trim
off some redundant runtime. An easy option to reduce the selftest
runtimes, so try halving our default subtest timeout. While this reduces
the number of iterations used, for the majority of tests that are
passing, repeat runs (w
On Fri, 25 Oct 2019 at 10:27, Chris Wilson wrote:
>
> BAT is growing a little fat and CI is under pressure and needs to trim
> off some redundant runtime. An easy option to reduce the selftest
> runtimes, so try halving our default subtest timeout. While this reduces
> the number of iterations use
For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can
Currently intel_can_enable_sagv function contains
a mix of workarounds for different platforms
some of them are not valid for gens >= 11 already,
so lets split it into separate functions.
v2:
- Rework watermark calculation algorithm to
attempt to calculate Level 0 watermark
with ad
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
v2: Fixed wrong PCode reply mask, removed hardcoded
values.
v3: Forbid si
== Series Details ==
Series: drm/i915: Move intel_engine_context_in/out into intel_lrc.c
URL : https://patchwork.freedesktop.org/series/68553/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7181 -> Patchwork_14977
Summary
--
On Fri, Oct 25, 2019 at 11:00:06AM +0200, Maarten Lankhorst wrote:
> Op 24-10-2019 om 17:21 schreef Ville Syrjälä:
> > On Thu, Oct 24, 2019 at 02:47:59PM +0200, Maarten Lankhorst wrote:
> >> Now that we separated everything into uapi and hw, it's
> >> time to make the split definitive. Remove the u
On Fri, Oct 25, 2019 at 12:53:51PM +0300, Stanislav Lisovskiy wrote:
> Currently intel_can_enable_sagv function contains
> a mix of workarounds for different platforms
> some of them are not valid for gens >= 11 already,
> so lets split it into separate functions.
>
> v2:
> - Rework watermark
On Fri, 2019-10-25 at 13:24 +0300, Ville Syrjälä wrote:
> On Fri, Oct 25, 2019 at 12:53:51PM +0300, Stanislav Lisovskiy wrote:
> > Currently intel_can_enable_sagv function contains
> > a mix of workarounds for different platforms
> > some of them are not valid for gens >= 11 already,
> > so lets sp
Drop the forcewake before libigt tries to wait on it.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 47 +++
1 file changed, 25 insertions(+), 22 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index 87
== Series Details ==
Series: drm/i915/selftests: Tweak the default subtest runtime
URL : https://patchwork.freedesktop.org/series/68554/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7182 -> Patchwork_14978
Summary
---
On Fri, 2019-10-25 at 10:44 +, Lisovskiy, Stanislav wrote:
> On Fri, 2019-10-25 at 13:24 +0300, Ville Syrjälä wrote:
> > On Fri, Oct 25, 2019 at 12:53:51PM +0300, Stanislav Lisovskiy
> > wrote:
> > > Currently intel_can_enable_sagv function contains
> > > a mix of workarounds for different plat
We can be more aggressive in our testing by launching a number of
kthreads, where each is submitting its own copy or fill batches on a set
of random sized objects. Also since the underlying fill and copy batches
can be pre-empted mid-batch(for particularly large objects), throw in a
random mixture
On Thu, Oct 24, 2019 at 01:45:16PM -0700, Rajat Jain wrote:
> Hi,
>
> Thanks for your review and comments. Please see inline below.
>
> On Thu, Oct 24, 2019 at 4:20 AM Thierry Reding
> wrote:
> >
> > On Tue, Oct 22, 2019 at 05:12:06PM -0700, Rajat Jain wrote:
> > > Certain laptops now come with
Quoting Matthew Auld (2019-10-25 12:24:42)
> We can be more aggressive in our testing by launching a number of
> kthreads, where each is submitting its own copy or fill batches on a set
> of random sized objects. Also since the underlying fill and copy batches
> can be pre-empted mid-batch(for part
== Series Details ==
Series: drm/i915/bios: add compression parameter block definition (rev2)
URL : https://patchwork.freedesktop.org/series/68396/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7169_full -> Patchwork_14961_full
=
On Fri, 25 Oct 2019, Jani Nikula wrote:
>On Fri, 25 Oct 2019, Lee Shawn C wrote:
>> commit 'a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS)'
>> introduced new PCI ID that CML support. But some sku is not support
>> yet so remove them avoid unexpected issue.
>
>Please elaborate.
>
>BR,
>Jani.
>
So
TGL introduced a feature in which we map the main surface to the
auxilliary surface. If we screw up the page tables, the HW has a
register to tell us which engine encounters a fault in the page table
walk.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_gpu_error.c | 8
d
On Thu, Oct 24, 2019 at 09:24:18PM +0300, Gwan-gyeong Mun wrote:
> It calls intel_dp_vsc_enable() and intel_dp_hdr_metadata_enable() on pipe
> updates to make sure that we enable sending of VSC SDP and HDR Metadata
> Infoframe SDP packet (when applicable) on fastsets.
I think we first need to move
Quoting Lionel Landwerlin (2019-10-25 13:17:18)
> TGL introduced a feature in which we map the main surface to the
> auxilliary surface. If we screw up the page tables, the HW has a
> register to tell us which engine encounters a fault in the page table
> walk.
Platform specific, or for likely all
v2: remove some inaccurate descriptions.
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Lucas De Marchi
Cc: Anusha Srivatsa
Cc: Cooper Chiou
Signed-off-by: Lee Shawn C
---
include/drm/i915_pciids.h | 4
1 file changed, 4 deletions(-)
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pci
U series device need different DDI buffer setup for eDP
and DP. If driver did not recognize ULT id proerply.
The setting for H and S series would be used.
v2 : add missing comma in subplatform_ult_ids[].
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Lucas De Marchi
Cc: Anusha Srivatsa
Cc: Cooper Chiou
On 25/10/2019 15:22, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-10-25 13:17:18)
TGL introduced a feature in which we map the main surface to the
auxilliary surface. If we screw up the page tables, the HW has a
register to tell us which engine encounters a fault in the page table
walk.
commit 'a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS)'
introduced new PCI ID that CML support. But some sku
is not support yet so remove them.
v2: remove some inaccurate descriptions.
v3: fix typo.
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Lucas De Marchi
Cc: Anusha Srivatsa
Cc: Cooper Chiou
Sign
commit 'a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS)'
introduced new PCI ID that CML support. But some sku
is not support yet so remove them.
v2: remove some inaccurate descriptions.
v3: fix typo.
v4: add missing version number.
Cc: Rodrigo Vivi
Cc: Jani Nikula
Cc: Lucas De Marchi
Cc: Anusha
On 25/10/2019 11:59, Chris Wilson wrote:
Drop the forcewake before libigt tries to wait on it.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
benchmarks/gem_wsim.c | 47 +++
1 file changed, 25 insertions(+), 22 deletions(-)
diff --git a/benchmar
On 25/10/2019 10:13, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-10-25 10:09:52)
From: Tvrtko Ursulin
Intel_lrc.c is the only caller and so to avoid some header file ordering
issues in future patches move these two over there.
How much pain would you feel if we did intel_lrc.c +
intel_
== Series Details ==
Series: drm/i915: Convert PAT setup to uncore mmio
URL : https://patchwork.freedesktop.org/series/68503/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7169_full -> Patchwork_14962_full
Summary
---
Because DP ports don't use intel_hdmi_infoframes_enabled() machanism,
DP ports requires a way to check a specific infoframe (aka. Video DIP )
is enabled or not.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 21 +
drivers/gpu/drm/i915/display/i
It calls intel_dp_vsc_enable() and intel_dp_hdr_metadata_enable() on pipe
updates to make sure that we enable sending of VSC SDP and HDR Metadata
Infoframe SDP packet (when applicable) on fastsets.
In order to set an enabled state of VSC SDP and HDR Metadata Infoframe SDP,
It adds intel_enable_info
Because DP ports don't use set_infoframes() / intel_write_infoframe()
machanisms, DP ports requires a handling of enabling/disabling of each
Video DIP when a changing usage of video DIP for SDP transmission such as
whether or not to use HDR.
For now it only adds enable_infoframe() callback for hsw
It prevents sending VSC SDP Packet to a receiver when VSC SDP is not
needed. Because VSC SDP is used for PSR, YCbCr 420, HDR BT.2020 and etc,
it checks PSR is enabled or not.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 10 +-
1 file changed, 9 insertions(
It prevents sending HDR Metadata Infoframe SDP packet to a receiver when
HDR Metadata Infoframe SDP is not needed.
v2: Minor style fix
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drive
Call intel_dp_vsc_enable() and intel_dp_hdr_metadata_enable() on pipe
updates to make sure that we enable sending of VSC SDP and HDR Metadata
Infoframe SDP packet (when applicable) on fastsets.
These functions check pipe state and when the features does not need,
they disable the features.
Signed
This reverts commit 900554dc6bfc996ad07b9e187bbfd3864cd5bed0 to make
sure that Fi.CI.DOCS complains :-)
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h
b/drivers/gpu/drm/i915/display/intel_dpll
Avoid angering clang and smatch by using a constant value in a '&&' test,
by forcing that constant value into a boolean.
E.g.,
drivers/gpu/drm/i915/gt/intel_engine_heartbeat.c:159:13: warning: use of
logical '&&' with constant operand [-Wconstant-logical-operand]
if (!delay && CONFIG_DRM_
drivers/gpu/drm/i915//gt/selftest_engine_heartbeat.c:255 live_heartbeat_fast()
error: uninitialized symbol 'err'.
drivers/gpu/drm/i915//gt/selftest_engine_heartbeat.c:320 live_heartbeat_off()
error: uninitialized symbol 'err'.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/selftest_en
Hi Arek,
can you please:
1. use the format:
commit 900554dc6bfc ("drm/i915: Describe structure member in
documentation")
when referring to a commit that has been applied.
chekcpatch.pl should have complained.
2. Sign off the commit
3. because this is a fix, please add the tag.
== Series Details ==
Series: Refactor Gen11+ SAGV support (rev4)
URL : https://patchwork.freedesktop.org/series/68028/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.h
AR dri
From: Tvrtko Ursulin
It was quite some time since I last posted this RFC, but recently there has been
some new interest, this time from OpenCL and related customers, so I decided to
give it a quick respin and test the waters.
This time round it has been really hastily rebased since the upstream
From: Tvrtko Ursulin
Expose a list of clients with open file handles in sysfs.
This will be a basis for a top-like utility showing per-client and per-
engine GPU load.
Currently we only expose each client's pid and name under opaque numbered
directories in /sys/class/drm/card0/clients/.
For in
From: Tvrtko Ursulin
Some clients have the DRM fd passed to them over a socket by the X server.
Grab the real client and pid when they create their first context and
update the exposed data for more useful enumeration.
Signed-off-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_contex
From: Tvrtko Ursulin
Expose per-client and per-engine busyness under the previously added sysfs
client root.
The new files are one per-engine instance and located under the 'busy'
directory. Each contains a monotonically increasing nano-second resolution
times each client's jobs were executing o
From: Tvrtko Ursulin
Some customers want to know how much of the GPU time are their clients
using in order to make dynamic load balancing decisions.
With the hooks already in place which track the overall engine busyness,
we can extend that slightly to split that time between contexts.
v2: Fix
From: Tvrtko Ursulin
By default we are not collecting any per-engine and per-context
statistcs.
Add a new sysfs toggle to enable this facility:
$ echo 1 >/sys/class/drm/card0/clients/enable_stats
v2: Rebase.
v3: sysfs_attr_init.
v4: Scheduler caps.
Signed-off-by: Tvrtko Ursulin
---
drivers/
From: Tvrtko Ursulin
intel_gpu_top counterpart for the equally named i915 series. For reference only
at this stage.
Tvrtko Ursulin (1):
intel-gpu-top: Support for client stats
tools/intel_gpu_top.c | 590 +-
1 file changed, 584 insertions(+), 6 deletio
From: Tvrtko Ursulin
Adds support for per-client engine busyness stats i915 exports in sysfs
and produces output like the below:
==
intel-gpu-top - 935/ 935 MHz;0% RC6; 14.73 Watts; 1097 irqs/s
IMC reads:
Provide the iterator name as an explicit macro parameter so that it is
known to the caller, and allows for them to properly nest loops over all
engines.
Fixes:
../tests/i915/gem_exec_schedule.c: In function ‘semaphore_noskip’:
../lib/igt_gt.h:84:44: warning: declaration of ‘e__’ shadows a previous
== Series Details ==
Series: series starting with [CI,1/7] drm/i915: support creating LMEM objects
(rev2)
URL : https://patchwork.freedesktop.org/series/68502/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b3c03a1e2a25 drm/i915: support creating LMEM objects
-:36: WARNING:FILE
== Series Details ==
Series: series starting with [CI,1/7] drm/i915: support creating LMEM objects
(rev2)
URL : https://patchwork.freedesktop.org/series/68502/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: support creating LMEM objects
Okay
Quoting Tvrtko Ursulin (2019-10-25 15:21:28)
> int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file)
> {
> + int ret = -ENOMEM;
> struct drm_i915_file_private *file_priv;
> - int ret;
>
> DRM_DEBUG("\n");
>
> file_priv = kzalloc(sizeof(*fi
Quoting Tvrtko Ursulin (2019-10-25 15:21:29)
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index 55f1f93c0925..c7f6684eb366 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
Quoting Tvrtko Ursulin (2019-10-25 15:21:30)
> +static int busy_add(int id, void *p, void *data)
> +{
> + struct busy_ctx *bc = data;
> + struct i915_gem_context *ctx = p;
> + unsigned int engine_class = bc->engine_class;
> + struct i915_gem_engines_iter it;
> + struct
== Series Details ==
Series: series starting with [CI,1/7] drm/i915: support creating LMEM objects
(rev2)
URL : https://patchwork.freedesktop.org/series/68502/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7186 -> Patchwork_14980
==
Quoting Tvrtko Ursulin (2019-10-25 15:21:31)
> + ret = i915_mutex_lock_interruptible(&i915->drm);
> + if (ret)
> + return ret;
> +
> + if (val && !i915->clients.stats.enabled)
> + enable = true;
> + else if (!val && i915->clients.stats.enabled)
>
Quoting Tvrtko Ursulin (2019-10-25 15:24:10)
> From: Tvrtko Ursulin
>
> Adds support for per-client engine busyness stats i915 exports in sysfs
> and produces output like the below:
>
> ==
> intel-gpu-top - 935/ 935 MHz;
On 10/17/2019 9:28 PM, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
It sounds like the hardware only needs the DSB object to be in global GTT
and not in the mappable region.
Currently tested and working without any regression, waiting for
confirmation from h/w team, will update soon.
Regard
Provide the iterator name as an explicit macro parameter so that it is
known to the caller, and allows for them to properly nest loops over all
engines.
Fixes:
../tests/i915/gem_exec_schedule.c: In function ‘semaphore_noskip’:
../lib/igt_gt.h:84:44: warning: declaration of ‘e__’ shadows a previous
From: Matthew Auld
We currently define LMEM, or local memory, as just another memory
region, like system memory or stolen, which we can expose to userspace
and can be mapped to the CPU via some BAR.
Signed-off-by: Matthew Auld
Cc: Joonas Lahtinen
Cc: Abdiel Janulgue
Reviewed-by: Chris Wilson
From: Matthew Auld
Add LMEM objects to list of backends we test for huge-GTT-pages.
Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilson
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 123 +-
1 file changed, 122 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/
From: Matthew Auld
Now that for all the relevant backends we do randomised testing, we need
to make sure we still sanity check the obvious cases that might blow up,
such that introducing a temporary regression is less likely. Also
rather than do this for every backend, just limit to our two memo
From: Matthew Auld
Simple test writing to dwords across an object, using various engines in
a randomized order, checking that our writes land from the cpu.
Signed-off-by: Matthew Auld
Reviewed-by: Chris Wilson
---
.../drm/i915/selftests/intel_memory_region.c | 166 ++
1 file
From: Matthew Auld
Ditch the dubious static list of sizes to enumerate, in favour of
choosing a random size within the limits of each backing store. With
repeated CI runs this should give us a wider range of object sizes, and
in turn more page-size combinations, while using less machine time.
Si
From: Abdiel Janulgue
Create an io-mapping to describe the CPU aperture for lmem.
Signed-off-by: Abdiel Janulgue
Cc: Matthew Auld
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_region_lmem.c | 28 ++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git
From: Abdiel Janulgue
We can create LMEM objects, but we also need to support mapping them
into kernel space for internal use.
Signed-off-by: Abdiel Janulgue
Signed-off-by: Matthew Auld
Signed-off-by: Steve Hampson
Cc: Joonas Lahtinen
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/
On 25/10/2019 16:13, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-10-25 15:24:10)
From: Tvrtko Ursulin
Adds support for per-client engine busyness stats i915 exports in sysfs
and produces output like the below:
==
in
== Series Details ==
Series: drm/i915/selftests/blt: add some kthreads into the mix
URL : https://patchwork.freedesktop.org/series/68563/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f43a0146b3fc drm/i915/selftests/blt: add some kthreads into the mix
-:159: CHECK:BRACES: Blank
Provide the iterator name as an explicit macro parameter so that it is
known to the caller, and allows for them to properly nest loops over all
engines.
Fixes:
../tests/i915/gem_exec_schedule.c: In function ‘semaphore_noskip’:
../lib/igt_gt.h:84:44: warning: declaration of ‘e__’ shadows a previous
== Series Details ==
Series: drm/i915/selftests/blt: add some kthreads into the mix
URL : https://patchwork.freedesktop.org/series/68563/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7186 -> Patchwork_14981
Summary
---
As the GT may be running in parallel with the module initialisation
code, we may enter i915_pmu_gt_parked() as we are executing
i915_pmu_register(). We have to init the spinlock before we mark
pmu.event_init so that it is available for use by i915_pmu_gt_parked()
(which may run as soon as event_ini
On 10/24/19 12:51 PM, Lucas De Marchi wrote:
On dgfx there's no LLC and eDRAM control table. Since now this
also means the device has global MOCS, just return early on the
initialization function.
L3 settings still apply and still need to be tweaked.
Bspec: 45101
Cc: Daniele Ceraolo Spurio
== Series Details ==
Series: drm/i915: capture aux page table error register
URL : https://patchwork.freedesktop.org/series/68565/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
71955d0b2b64 drm/i915: capture aux page table error register
-:7: WARNING:TYPO_SPELLING: 'auxilliary'
On Sat, Oct 26, 2019 at 04:32:25AM +0800, Lee Shawn C wrote:
> commit 'a7b4deeb02b9 ("drm/i915/cml: Add CML PCI IDS)'
> introduced new PCI ID that CML support. But some sku
> is not support yet so remove them.
A better description would be that some PCI IDs were removed from the
CML IDs in BSpec.
On Fri, Oct 25, 2019 at 09:57:48AM +0300, Jani Nikula wrote:
> On Thu, 24 Oct 2019, Jonathan Corbet wrote:
> > On Sun, 20 Oct 2019 21:17:17 +0800
> > Changbin Du wrote:
> >
> >> The 'functions' directive is not only for functions, but also works for
> >> structs/unions. So the name is misleading.
== Series Details ==
Series: series starting with [v4] drm/i915/cml: Remove unsupport PCI ID (rev5)
URL : https://patchwork.freedesktop.org/series/68547/
State : failure
== Summary ==
Applying: drm/i915/cml: Remove unsupport PCI ID
Applying: drm/i915/cml: Separate U sereis pci id from origianl
== Series Details ==
Series: drm/i915: capture aux page table error register
URL : https://patchwork.freedesktop.org/series/68565/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7186 -> Patchwork_14982
Summary
---
**F
On Wed, Oct 23, 2019 at 03:44:50PM +0300, Imre Deak wrote:
> On Tue, Oct 22, 2019 at 09:56:43PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The change to skip the PCH reference initialization during fastboot
> > did end up breaking FDI. To fix that let's try to do the PCH referenc
We can be more aggressive in our testing by launching a number of
kthreads, where each is submitting its own copy or fill batches on a set
of random sized objects. Also since the underlying fill and copy batches
can be pre-empted mid-batch(for particularly large objects), throw in a
random mixture
Quoting Lionel Landwerlin (2019-10-25 13:29:46)
> On 25/10/2019 15:22, Chris Wilson wrote:
> > Quoting Lionel Landwerlin (2019-10-25 13:17:18)
> >> TGL introduced a feature in which we map the main surface to the
> >> auxilliary surface. If we screw up the page tables, the HW has a
> >> register to
On Fri, 25 Oct 2019 at 17:55, Chris Wilson wrote:
>
> As the GT may be running in parallel with the module initialisation
> code, we may enter i915_pmu_gt_parked() as we are executing
> i915_pmu_register(). We have to init the spinlock before we mark
> pmu.event_init so that it is available for us
== Series Details ==
Series: Update VSC SDP / HDR Metadata SDP states on pipe updates. (rev2)
URL : https://patchwork.freedesktop.org/series/68531/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7186 -> Patchwork_14984
Summa
== Series Details ==
Series: CI: Test revert some of the documentation fixes
URL : https://patchwork.freedesktop.org/series/68567/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
919d7fcfb94e CI: Test revert some of the documentation fixes
-:24: ERROR:MISSING_SIGN_OFF: Missing Si
== Series Details ==
Series: CI: Test revert some of the documentation fixes
URL : https://patchwork.freedesktop.org/series/68567/
State : warning
== Summary ==
$ make htmldocs 2>&1 | grep i915 | grep -v "reading sources" | grep -v "writing
output"
./drivers/gpu/drm/i915/display/intel_dpll_mg
On Thu, Oct 24, 2019 at 6:40 AM Chris Wilson
wrote:
> Our existing behaviour is to allow contexts and their GPU requests to
> persist past the point of closure until the requests are complete. This
> allows clients to operate in a 'fire-and-forget' manner where they can
> setup a rendering pipeli
== Series Details ==
Series: CI: Test revert some of the documentation fixes
URL : https://patchwork.freedesktop.org/series/68567/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7187 -> Patchwork_14985
Summary
---
**F
== Series Details ==
Series: series starting with [1/2] drm/i915: Encapsulate kconfig constant
values inside boolean predicates
URL : https://patchwork.freedesktop.org/series/68569/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
96cf8a97600c drm/i915: Encapsulate kconfig consta
On Fri, Oct 25, 2019 at 12:53:52PM +0300, Stanislav Lisovskiy wrote:
> According to BSpec 53998, we should try to
> restrict qgv points, which can't provide
> enough bandwidth for desired display configuration.
>
> Currently we are just comparing against all of
> those and take minimum(worst case)
On Fri, Oct 25, 2019 at 1:36 PM Thierry Reding wrote:
>
> On Thu, Oct 24, 2019 at 01:45:16PM -0700, Rajat Jain wrote:
> > Hi,
> >
> > Thanks for your review and comments. Please see inline below.
> >
> > On Thu, Oct 24, 2019 at 4:20 AM Thierry Reding
> > wrote:
> > >
> > > On Tue, Oct 22, 2019 a
Chris Wilson writes:
> Exercise the first level of suspend, S0. This is basically the same as
> our runtime-suspend, we need to put the device to sleep but otherwise
> it is left powered up.
>
> Ideally, we would measure the energy consumption in this state.
This and the others.
Reviewed-by: Mi
On Mon, Oct 21, 2019 at 06:28:18AM +, Lin, Wayne wrote:
>
>
> > -Original Message-
> > From: Ville Syrjälä
> > Sent: Monday, October 14, 2019 10:42 PM
> > To: Lin, Wayne
> > Cc: dri-de...@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> > Subject: Re: [PATCH 4/4] drm/edid: P
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