[Intel-gfx] [CI 3/9] drm/i915/perf: allow for CS OA configs to be created lazily

2019-10-11 Thread Chris Wilson
From: Lionel Landwerlin Here we introduce a mechanism by which the execbuf part of the i915 driver will be able to request that a batch buffer containing the programming for a particular OA config be created. We'll execute these OA configuration buffers right before executing a set of userspace

[Intel-gfx] [CI 6/9] drm/i915/perf: execute OA configuration from command stream

2019-10-11 Thread Chris Wilson
From: Lionel Landwerlin We haven't run into issues with programming the global OA/NOA registers configuration from CPU so far, but HW engineers actually recommend doing this from the command streamer. On TGL in particular one of the clock domain in which some of that programming goes might not be

[Intel-gfx] [CI 5/9] drm/i915/perf: implement active wait for noa configurations

2019-10-11 Thread Chris Wilson
From: Lionel Landwerlin NOA configuration take some amount of time to apply. That amount of time depends on the size of the GT. There is no documented time for this. For example, past experimentations with powergating configuration changes seem to indicate a 60~70us delay. We go with 500us as def

[Intel-gfx] [CI 8/9] drm/i915/perf: allow holding preemption on filtered ctx

2019-10-11 Thread Chris Wilson
From: Lionel Landwerlin We would like to make use of perf in Vulkan. The Vulkan API is much lower level than OpenGL, with applications directly exposed to the concept of command buffers (pretty much equivalent to our batch buffers). In Vulkan, queries are always limited in scope to a command buff

[Intel-gfx] [CI 9/9] drm/i915/execlists: Prevent merging requests with conflicting flags

2019-10-11 Thread Chris Wilson
We set out-of-bound parameters inside the i915_requests.flags field, such as disabling preemption or marking the end-of-context. We should not coalesce consecutive requests if they have differing instructions as we only inspect the last active request in a context. Thus if we allow a later request

[Intel-gfx] [CI 7/9] drm/i915/perf: Allow dynamic reconfiguration of the OA stream

2019-10-11 Thread Chris Wilson
Introduce a new perf_ioctl command to change the OA configuration of the active stream. This allows the OA stream to be reconfigured between batch buffers, giving greater flexibility in sampling. We inject a request into the OA context to reconfigure the stream asynchronously on the GPU in between

[Intel-gfx] [CI 4/9] drm/i915: add support for perf configuration queries

2019-10-11 Thread Chris Wilson
From: Lionel Landwerlin Listing configurations at the moment is supported only through sysfs. This might cause issues for applications wanting to list configurations from a container where sysfs isn't available. This change adds a way to query the number of configurations and their content throu

[Intel-gfx] [CI 1/9] drm/i915/perf: Replace global wakeref tracking with engine-pm

2019-10-11 Thread Chris Wilson
As we now have a specific engine to use OA on, exchange the top-level runtime-pm wakeref with the engine-pm. This still results in the same top-level runtime-pm, but with more nuances to keep the engine and its gt awake. Signed-off-by: Chris Wilson Reviewed-by: Lionel Landwerlin --- drivers/gpu

[Intel-gfx] [CI 2/9] drm/i915/perf: introduce a versioning of the i915-perf uapi

2019-10-11 Thread Chris Wilson
From: Lionel Landwerlin Reporting this version will help application figure out what level of the support the running kernel provides. v2: Add i915_perf_ioctl_version() (Chris) Signed-off-by: Lionel Landwerlin Reviewed-by: Chris Wilson Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i9

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/4] drm/i915/display: Handle fused off display correctly

2019-10-11 Thread Souza, Jose
On Fri, 2019-10-11 at 10:16 +0300, Martin Peres wrote: > On 10/10/2019 23:18, Patchwork wrote: > > == Series Details == > > > > Series: series starting with [1/4] drm/i915/display: Handle fused > > off display correctly > > URL : https://patchwork.freedesktop.org/series/67872/ > > State : failur

Re: [Intel-gfx] Does the i915 VBT tell us if a panel is an OLED panel?

2019-10-11 Thread Sean Paul
On Thu, Oct 10, 2019 at 04:35:56PM +0300, Jani Nikula wrote: > On Thu, 10 Oct 2019, Hans de Goede wrote: > > Hi Jani, > > > > During plumbers I had some discussions with Daniel about supporting > > OLED screens. Userspace may need to know that a panel is OLED for 2 > > reasons: > > > > 1) To avoid

[Intel-gfx] [PATCH] drm/i915/selftests: Serialise write to scratch with its vma binding

2019-10-11 Thread Chris Wilson
Add the missing serialisation on the request for a write into a vma to wait until that vma is bound before being executed by the GPU. Signed-off-by: Chris Wilson Cc: Matthew Auld --- drivers/gpu/drm/i915/gt/selftest_workarounds.c | 8 1 file changed, 8 insertions(+) diff --git a/drive

Re: [Intel-gfx] [PATCH] drm/i915/selftests: Serialise write to scratch with its vma binding

2019-10-11 Thread Matthew Auld
On Fri, 11 Oct 2019 at 20:36, Chris Wilson wrote: > > Add the missing serialisation on the request for a write into a vma to > wait until that vma is bound before being executed by the GPU. > > Signed-off-by: Chris Wilson > Cc: Matthew Auld Reviewed-by: Matthew Auld

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: coffeelake supports hdcp2.2

2019-10-11 Thread Patchwork
== Series Details == Series: drm/i915: coffeelake supports hdcp2.2 URL : https://patchwork.freedesktop.org/series/67925/ State : success == Summary == CI Bug Log - changes from CI_DRM_7067 -> Patchwork_14771 Summary --- **SUCCESS**

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/9] drm/i915/perf: Replace global wakeref tracking with engine-pm

2019-10-11 Thread Patchwork
== Series Details == Series: series starting with [CI,1/9] drm/i915/perf: Replace global wakeref tracking with engine-pm URL : https://patchwork.freedesktop.org/series/67927/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9446e81d2ad5 drm/i915/perf: Replace global wakeref track

[Intel-gfx] [PATCH 2/8] drm/i915: Nuke 'realloc_pipes'

2019-10-11 Thread Ville Syrjala
From: Ville Syrjälä The 'realloc_pipes' bitmask is pointless. It is either: a) the set of pipes which are already part of the state, in which case adding them again is entirely redundant b) the set of all pipes which we then add to the state Also the fact that 'realloc_pipes' uses the crtc in

[Intel-gfx] [PATCH 3/8] drm/i915: Make dirty_pipes refer to pipes

2019-10-11 Thread Ville Syrjala
From: Ville Syrjälä Despite the its name dirty_pipes refers to crtc indexes. Let's change its behaviout to match the name. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 9 +++-- drivers/gpu/drm/i915/intel_pm.c | 13 ++--- 2 files chan

[Intel-gfx] [PATCH 4/8] drm/i915: Don't set undefined bits in dirty_pipes

2019-10-11 Thread Ville Syrjala
From: Ville Syrjälä skl_commit_modeset_enables() straight up compares dirty_pipes with a bitmask of already committed pipes. If we set bits in dirty_pipes for non-existent pipes that comparison will never work right. So let's limit ourselves to bits that exist. And we'll do the same for the acti

[Intel-gfx] [PATCH 1/8] drm/i915: Nuke the useless changed param from skl_ddb_add_affected_pipes()

2019-10-11 Thread Ville Syrjala
From: Ville Syrjälä changed==true just means we have some crtcs in the state. All the stuff following this only operates on crtcs in the state anyway so there is no point in having this bool. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_pm.c | 30 --

[Intel-gfx] [PATCH 8/8] drm/i915: Nuke skl wm.dirty_pipes bitmask

2019-10-11 Thread Ville Syrjala
From: Ville Syrjälä The dirty_pipes bitmask is now unused. Get rid of it. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_drv.h | 1 - drivers/gpu/drm/i915/intel_pm.c | 35 + 2 files changed, 1 insertion(+), 35 deletions(-) diff --git a/drivers/gpu/

[Intel-gfx] [PATCH 5/8] drm/i915: Streamline skl_commit_modeset_enables()

2019-10-11 Thread Ville Syrjala
From: Ville Syrjälä skl_commit_modeset_enables() is a bit of mess. Let's streamline it by simply tracking which pipes still need to be updated. As a bonus we get rid of the state->wm_results.dirty_pipes usage. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 39 +

[Intel-gfx] [PATCH 0/8] drm/i915: Some cleanup near the SKL wm/ddb area

2019-10-11 Thread Ville Syrjala
From: Ville Syrjälä Made the mistake of looking at some skl+ wm/ddb stuff, and then proceeded to throw out a bunch of useless things. I stopped when I saw struct skl_ddb_allocation and decided that maybe that starts to cut a bit too close to the dbuf slice stuff. Ville Syrjälä (8): drm/i915:

[Intel-gfx] [PATCH 7/8] drm/i915: Move linetime wms into the crtc state

2019-10-11 Thread Ville Syrjala
From: Ville Syrjälä The linetime watermarks really have very little in common with the plane watermarks. It looks to be cleaner to simply track them in the crtc_state and program them from the normal modeset/fastset paths. The only dark cloud comes from the fact that the register is still suppos

[Intel-gfx] [PATCH 6/8] drm/i915: Polish WM_LINETIME register stuff

2019-10-11 Thread Ville Syrjala
From: Ville Syrjälä Let's store the normal and IPS linetime watermarks individually, and while at it we'll pimp the register definitions as well. Signed-off-by: Ville Syrjälä --- .../drm/i915/display/intel_display_types.h| 3 +- drivers/gpu/drm/i915/i915_reg.h | 14 ++-- dri

[Intel-gfx] [PATCH] drm/i915: Favor last VBT child device with conflicting AUX ch/DDC pin

2019-10-11 Thread Ville Syrjala
From: Ville Syrjälä The first come first served apporoach to handling the VBT child device AUX ch conflicts has backfired. We have machines in the wild where the VBT specifies both port A eDP and port E DP (in that order) with port E being the real one. So let's try to flip the preference around

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/9] drm/i915/perf: Replace global wakeref tracking with engine-pm

2019-10-11 Thread Patchwork
== Series Details == Series: series starting with [CI,1/9] drm/i915/perf: Replace global wakeref tracking with engine-pm URL : https://patchwork.freedesktop.org/series/67927/ State : success == Summary == CI Bug Log - changes from CI_DRM_7067 -> Patchwork_14772 ===

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Serialise write to scratch with its vma binding

2019-10-11 Thread Patchwork
== Series Details == Series: drm/i915/selftests: Serialise write to scratch with its vma binding URL : https://patchwork.freedesktop.org/series/67928/ State : success == Summary == CI Bug Log - changes from CI_DRM_7067 -> Patchwork_14773 Su

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Some cleanup near the SKL wm/ddb area

2019-10-11 Thread Patchwork
== Series Details == Series: drm/i915: Some cleanup near the SKL wm/ddb area URL : https://patchwork.freedesktop.org/series/67930/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Favor last VBT child device with conflicting AUX ch/DDC pin

2019-10-11 Thread Patchwork
== Series Details == Series: drm/i915: Favor last VBT child device with conflicting AUX ch/DDC pin URL : https://patchwork.freedesktop.org/series/67931/ State : success == Summary == CI Bug Log - changes from CI_DRM_7067 -> Patchwork_14775

Re: [Intel-gfx] Kernel crash on 4.19.77-1-lts (Arch Linux / ThinkPad T470p)

2019-10-11 Thread John Maguire
> Just use Cc. We want all replies to go to the list(s) as well. Sorry, I wasn't sure and wanted to err on the side of not spamming the wrong people. > Oct 10 12:53:30 scorpion kernel: RIP: 0010:dma_fence_signal_locked+0x30/0xe0 > > Looks like it could be > https://bugs.freedesktop.org/show_bug.c

Re: [Intel-gfx] [PATCH v3] drm/i915: Restrict qgv points which don't have enough bandwidth.

2019-10-11 Thread James Ausmus
On Wed, Sep 25, 2019 at 03:17:37PM +0300, Stanislav Lisovskiy wrote: > According to BSpec 53998, we should try to > restrict qgv points, which can't provide > enough bandwidth for desired display configuration. > > Currently we are just comparing against all of > those and take minimum(worst case)

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Add an rcu_barrier option to i915_drop_caches

2019-10-11 Thread Patchwork
== Series Details == Series: drm/i915: Add an rcu_barrier option to i915_drop_caches URL : https://patchwork.freedesktop.org/series/67922/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7065_full -> Patchwork_14770_full Summ

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: coffeelake supports hdcp2.2

2019-10-11 Thread Patchwork
== Series Details == Series: drm/i915: coffeelake supports hdcp2.2 URL : https://patchwork.freedesktop.org/series/67925/ State : success == Summary == CI Bug Log - changes from CI_DRM_7067_full -> Patchwork_14771_full Summary --- **S

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [CI,1/9] drm/i915/perf: Replace global wakeref tracking with engine-pm

2019-10-11 Thread Patchwork
== Series Details == Series: series starting with [CI,1/9] drm/i915/perf: Replace global wakeref tracking with engine-pm URL : https://patchwork.freedesktop.org/series/67927/ State : success == Summary == CI Bug Log - changes from CI_DRM_7067_full -> Patchwork_14772_full =

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