Quoting Ruhl, Michael J (2019-09-16 20:45:14)
> >-Original Message-
> >From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf
> >Of Chris Wilson
> >Sent: Sunday, September 15, 2019 2:46 PM
> >@@ -424,9 +424,9 @@ int drm_mm_reserve_node(struct drm_mm *mm,
> >struct drm_mm
== Series Details ==
Series: series starting with [1/6] drm/i915: Polish possible_clones setup
URL : https://patchwork.freedesktop.org/series/67504/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6992_full -> Patchwork_14637_full
Quoting Tvrtko Ursulin (2019-09-26 14:57:24)
>
> On 25/09/2019 11:01, Chris Wilson wrote:
> > void i915_gem_context_release(struct kref *ref)
> > {
> > struct i915_gem_context *ctx = container_of(ref, typeof(*ctx), ref);
> > - struct drm_i915_private *i915 = ctx->i915;
> > + stru
== Series Details ==
Series: drm/i915/selftests: Exercise potential false lite-restore (rev9)
URL : https://patchwork.freedesktop.org/series/67438/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6992_full -> Patchwork_14638_full
=
Hello Ville,
On 9/25/2019 7:24 PM, Ville Syrjala wrote:
From: Ville Syrjälä
We're going to need two cea mode tables (on for VICs < 128,
another one for VICs >= 193). To that end replace the direct
edid_cea_modes[] lookups with a function call. And we'll rename
the array to edid_cea_modes_0[] t
Resending this series to test with DC3CO IGT series.
https://patchwork.freedesktop.org/series/66648/
Test-with: <1570088709-3605-2-git-send-email-jeeva...@intel.com>
Anshuman Gupta (6):
drm/i915/tgl: Add DC3CO required register and bits
drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
DC3CO enable bit will be used by driver to make DC3CO
ready for DMC f/w and status bit will be used as DC3CO
entry status.
2. Transcoder EXITLINE register and its bit fields and mask.
Transcode
Enable dc3co state in enable_dc module param and add dc3co
enable mask to allowed_dc_mask and gen9_dc_mask.
v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6
independently. [Animesh]
v2: Using a switch statement for cleaner code. [Animesh]
Cc: Jani Nikula
Cc: Imre Deak
Cc: A
On 9/25/2019 7:25 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Add a second table to the cea modes with VIC >= 193.
Cc: Hans Verkuil
Cc: Shashank Sharma
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 151 -
1 file changed, 149 insertion
DC3CO is useful power state, when DMC detects PSR2 idle frame
while an active video playback, playing 30fps video on 60hz panel
is the classic example of this use case.
B.Specs:49196 has a restriction to enable DC3CO only for Video Playback.
It will be worthy to enable DC3CO after completion of ea
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
v1: comment modification for DMC_DBUG3.
using GEN >= 12 check instead of IS_TIGERLAK
DC3CO enabling B.Specs sequence requires to enable end configure
exit scanlines to TRANS_EXITLINE register, programming this register
has to be part of modeset sequence as this can't be change when
transcoder or port is enabled.
When system boots with only eDP panel there may not be real
modeset as
Add target_dc_state and used by set_target_dc_state API
in order to enable DC3CO state with existing DC states.
target_dc_state will enable/disable the desired DC state in
DC_STATE_EN reg when "DC Off" power well gets disable/enable.
v2: commit log improvement.
v3: Used intel_wait_for_register to
On 9/25/2019 7:25 PM, Ville Syrjala wrote:
From: Ville Syrjälä
Now that the cea mode handling is not 100% tied to the single
array the dummy VIC 0 mode is pretty much pointles. Throw it
out.
Cc: Hans Verkuil
Cc: Shashank Sharma
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c
On Wed, 02 Oct 2019, Ville Syrjälä wrote:
> On Wed, Oct 02, 2019 at 05:54:04PM +0300, Jani Nikula wrote:
>> Unify on current common usage to allow repurposing drm_err() later. Fix
>> newlines while at it.
>>
>> Signed-off-by: Jani Nikula
>
> Series is
> Reviewed-by: Ville Syrjälä
Thanks, pushe
The CDCLK>=2*BCLK constraint applies to all generations since gen10.
Extend the constraint logic in audio get/put_power().
Signed-off-by: Kai Vehmanen
---
drivers/gpu/drm/i915/display/intel_audio.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/displ
On platfroms with gen10+ display, driver must set the enable bit of
AUDIO_PIN_BUF_CTL register before transactions with the HDA controller
can proceed. Add setting this bit to the audio power up sequence.
Failing to do this resulted in errors during display audio codec probe,
and failures during r
== Series Details ==
Series: drm/i915/vbt: Child device size remains unchanged through VBT 229
URL : https://patchwork.freedesktop.org/series/67510/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6992_full -> Patchwork_14639_full
Nothing inside the idle worker now requires struct_mutex, so we can
remove the indirection of using our own worker.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c| 28 ++-
.../drm/i915/gem/selftests/i915_gem_mman.c|
The premise here is to simply avoiding having to acquire the vm->mutex
inside vma create/destroy to update the vm->unbound_lists, to avoid some
nasty lock recursions later.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 2 +-
drivers/g
We don't need to hold struct_mutex now for retiring requests, so drop it
from i915_retire_requests() and i915_gem_wait_for_idle(), finally
removing I915_WAIT_LOCKED for good.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../gpu/drm/i915/gem/i915_gem_client_blt.c| 7 +-
driv
wait_for_timelines is essentially the same loop as retiring requests
(with an extra timeout), so merge the two into one routine.
v2: i915_retire_requests_timeout and keep VT'd w/a as !interruptible
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_mm
As our global unpark/park keep track of the number of active users, we
can simply move the accounting from the GEM layer to the base GT layer.
It was placed originally inside GEM to benefit from the 100ms extra
delay on idleness, but that has been eliminated and now there is no
substantive differen
We no longer need to placate lockdep by holding struct_mutex for our
initialisation, so don't.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 2 --
drivers/gpu/drm/i915/i915_gem.c | 9 -
drivers/gpu/drm/i91
Requests are run from the gt and are tided into the gt runtime power
management, so pull the runtime request management under gt/
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gem/i915_gem_mman.c |
We no longer need struct_mutex to serialise request emission, so remove
it from the gt selftests.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
.../gpu/drm/i915/gem/selftests/huge_pages.c | 15 +-
.../drm/i915/gem/selftests/i915_gem_context.c | 4 -
.../drm/i915/gem/selftests
As we need to use a mutex to serialise i915_active activation
(because we want to allow the callback to sleep), we need to push the
i915_active.retire into a worker callback in case we get need to retire
from an atomic context.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
.../gpu/d
Since we cannot allocate underneath the vm->mutex (it is used in the
direct-reclaim paths), we need to shift the allocations off into a
mutexless worker with fence recursion prevention. To know when we need
this protection, we mark up the address spaces that do allocate before
insertion. In the fut
Make dma_fence_enable_sw_signaling() behave like its
dma_fence_add_callback() and dma_fence_default_wait() counterparts and
perform the test to enable signaling under the fence->lock, along with
the action to do so. This ensure that should an implementation be trying
to flush the cb_list (by signal
The ulterior motive to switching the booleans over to bitops is to
allow use of the allocated flag as a bitlock.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/drm_mm.c | 36 +++
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 6 ++--
drivers/gpu/drm/i915/g
Forgo the struct_mutex serialisation for i915_active, and interpose its
own mutex handling for active/retire.
This is a multi-layered sleight-of-hand. First, we had to ensure that no
active/retire callbacks accidentally inverted the mutex ordering rules,
nor assumed that they were themselves seria
It protects nothing being accessed for the intel_framebuffer, so it's
own locking had better be sufficient.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.
struct_mutex provides no serialisation of the registers and data
structures being saved and restored across suspend/resume. It is
completely superfluous here.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_suspend.c | 8
1 file changed, 8 deletion
Having a struct_mutex around the read of a BIOS blob serves no purpose.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers
The overlay uses the modeset mutex to control itself and only required
the struct_mutex for requests, which is now obsolete.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/display/intel_display.c | 7 +--
drivers/gpu/drm/i915/display/intel_overlay.c | 13 -
Now that we can retire without taking struct_mutex, we can do so to
handle shrinking the mmap-offset space after an allocation failure.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Matthew Auld
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 17 +--
Keep track of the GEM contexts underneath i915->gem.contexts and assign
them their own lock for the purposes of list management.
v2: Focus on lock tracking; ctx->vm is protected by ctx->mutex
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 170
Now that we now longer need to guarantee that the active callback is
under the struct_mutex, we can lift it out of the i915_gem_park() and
into the engine parking itself.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c| 19 -
Tvrtko wanted all the pain in one hit, so here it is.
-Chris
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
With the introduction of ctx->engines[] we allow multiple logical
contexts to be used on the same engine (e.g. with virtual engines).
According to bspec, aach logical context requires a unique tag in order
for context-switching to occur correctly between them. [Simple
experiments show that it is no
Hi,
On Wed, 2 Oct 2019, Kai Vehmanen wrote:
> I have one failing case left on ICL where v1 patchset does not seem
> sufficient. The test case involves a loop of doing S3 suspend, resume,
> unload driver, load driver, play audio via HDMI and repeat. I get
> systematically better results with thi
From: Tvrtko Ursulin
We do not have to use atomic bitops when already under the spinlock.
Saves on a handful of lock instruction prefixes, on x86 at least.
Signed-off-by: Tvrtko Ursulin
Cc: dri-de...@lists.freedesktop.org
Cc: Chris Wilson
---
drivers/dma-buf/dma-fence.c | 14 +++---
== Series Details ==
Series: drm/i915/dp: remove static variable for aux last status (rev2)
URL : https://patchwork.freedesktop.org/series/67499/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6996 -> Patchwork_14641
Summary
== Series Details ==
Series: DC3CO Support for TGL test with DC3CO IGT
URL : https://patchwork.freedesktop.org/series/67525/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6996 -> Patchwork_14642
Summary
---
**SUCCESS
== Series Details ==
Series: series starting with [1/4] drm/i915/vga: rename intel_vga_msr_write()
to intel_vga_reset_io_mem() (rev2)
URL : https://patchwork.freedesktop.org/series/67493/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6bc8182b67d0 drm/i915/vga: rename intel_vga
On Thu, 03 Oct 2019, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/dp: remove static variable for aux last status (rev2)
> URL : https://patchwork.freedesktop.org/series/67499/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6996 -> Patchwork_14641
> =
== Series Details ==
Series: series starting with [1/4] drm/i915/vga: rename intel_vga_msr_write()
to intel_vga_reset_io_mem() (rev2)
URL : https://patchwork.freedesktop.org/series/67493/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6996 -> Patchwork_14643
==
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Fix audio power up sequence for
gen10+ display
URL : https://patchwork.freedesktop.org/series/67528/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6996 -> Patchwork_14644
== Series Details ==
Series: series starting with [01/22] dma-fence: Serialise signal enabling
(dma_fence_enable_sw_signaling)
URL : https://patchwork.freedesktop.org/series/67529/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
965a4b96c26d dma-fence: Serialise signal enabling
== Series Details ==
Series: series starting with [01/22] dma-fence: Serialise signal enabling
(dma_fence_enable_sw_signaling)
URL : https://patchwork.freedesktop.org/series/67529/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6996 -> Patchwork_14645
=
Keep track of the GEM contexts underneath i915->gem.contexts and assign
them their own lock for the purposes of list management.
v2: Focus on lock tracking; ctx->vm is protected by ctx->mutex
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
Annotate the ctx->vm assignment on creation
---
dri
Keep track of the GEM contexts underneath i915->gem.contexts and assign
them their own lock for the purposes of list management.
v2: Focus on lock tracking; ctx->vm is protected by ctx->mutex
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 173
On Wed, Oct 02, 2019 at 03:32:41PM -0700, Matt Roper wrote:
> On Mon, Sep 23, 2019 at 03:29:30AM -0700, Dhinakaran Pandiyan wrote:
> > Gen-12 display decompression operates on Y-tiled compressed main surface.
> > The CCS is linear
>
> I'd mention in the commit message that we opt to to treat the
>
Keep track of the GEM contexts underneath i915->gem.contexts and assign
them their own lock for the purposes of list management.
v2: Focus on lock tracking; ctx->vm is protected by ctx->mutex
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
Removed the last rcu_dereference_protected(true) hac
== Series Details ==
Series: dma-fence: Use non-atomic bitops while under the lock
URL : https://patchwork.freedesktop.org/series/67532/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6996 -> Patchwork_14646
Summary
---
On Thu, Oct 03, 2019 at 12:43:41AM +, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/tgl: Add the Thunderbolt PLL divider values (rev2)
> URL : https://patchwork.freedesktop.org/series/67498/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6993 -> Pat
On 03/10/2019 11:12, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
We do not have to use atomic bitops when already under the spinlock.
Saves on a handful of lock instruction prefixes, on x86 at least.
Signed-off-by: Tvrtko Ursulin
Cc: dri-de...@lists.freedesktop.org
Cc: Chris Wilson
---
dr
== Series Details ==
Series: drm/i915/dp: remove static variable for aux last status (rev3)
URL : https://patchwork.freedesktop.org/series/67499/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6996 -> Patchwork_14647
Summary
== Series Details ==
Series: series starting with [01/22] dma-fence: Serialise signal enabling
(dma_fence_enable_sw_signaling) (rev4)
URL : https://patchwork.freedesktop.org/series/67529/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
dc6317e4794e dma-fence: Serialise signal en
== Series Details ==
Series: series starting with [01/22] dma-fence: Serialise signal enabling
(dma_fence_enable_sw_signaling) (rev4)
URL : https://patchwork.freedesktop.org/series/67529/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6996 -> Patchwork_14648
==
Quoting Chris Wilson (2019-10-03 10:36:18)
> Make dma_fence_enable_sw_signaling() behave like its
> dma_fence_add_callback() and dma_fence_default_wait() counterparts and
> perform the test to enable signaling under the fence->lock, along with
> the action to do so. This ensure that should an imple
If we unwind the active requests, and on resubmission discover that we
intend to preempt the active context with itself, simply skip the ELSP
submission.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 17 -
1 file changed, 16 insertions(+), 1 deletion(-)
d
On 15/09/2019 19:45, Chris Wilson wrote:
Make dma_fence_enable_sw_signaling() behave like its
dma_fence_add_callback() and dma_fence_default_wait() counterparts and
perform the test to enable signaling under the fence->lock, along with
the action to do so. This ensure that should an implementati
On 03/10/2019 14:09, Chris Wilson wrote:
Quoting Chris Wilson (2019-10-03 10:36:18)
Make dma_fence_enable_sw_signaling() behave like its
dma_fence_add_callback() and dma_fence_default_wait() counterparts and
perform the test to enable signaling under the fence->lock, along with
the action to do
Make dma_fence_enable_sw_signaling() behave like its
dma_fence_add_callback() and dma_fence_default_wait() counterparts and
perform the test to enable signaling under the fence->lock, along with
the action to do so. This ensure that should an implementation be trying
to flush the cb_list (by signal
Quoting Chris Wilson (2019-10-03 14:19:46)
> Make dma_fence_enable_sw_signaling() behave like its
> dma_fence_add_callback() and dma_fence_default_wait() counterparts and
> perform the test to enable signaling under the fence->lock, along with
> the action to do so. This ensure that should an imple
Make dma_fence_enable_sw_signaling() behave like its
dma_fence_add_callback() and dma_fence_default_wait() counterparts and
perform the test to enable signaling under the fence->lock, along with
the action to do so. This ensure that should an implementation be trying
to flush the cb_list (by signal
Keep track of the GEM contexts underneath i915->gem.contexts and assign
them their own lock for the purposes of list management.
v2: Focus on lock tracking; ctx->vm is protected by ctx->mutex
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
Another missed ctx->mutex around __assign_ppgtt.
---
On 15/09/2019 19:45, Chris Wilson wrote:
The ulterior motive to switching the booleans over to bitops is to
allow use of the allocated flag as a bitlock.
Locked bit usage applies only to DRM_MM_NODE_ALLOCATED_BIT?
Any value in extracting the conversion to calling drm_mm_node_allocated
ahead
On Wed, Oct 02, 2019 at 11:00:45AM -0700, Lucas De Marchi wrote:
> On Wed, Oct 2, 2019 at 9:25 AM Ville Syrjala
> wrote:
> >
> > From: Ville Syrjälä
> >
> > Rename the encoder->crtc_mask to encoder->pipe_mask to better
> > reflect what it actually contains.
> >
> > Signed-off-by: Ville Syrjälä
>
On Thu, Oct 03, 2019 at 01:46:16PM +0530, Sharma, Shashank wrote:
> Hello Ville,
>
> On 9/25/2019 7:24 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > We're going to need two cea mode tables (on for VICs < 128,
> > another one for VICs >= 193). To that end replace the direct
> > edid_cea
>-Original Message-
>From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf
>Of Chris Wilson
>Sent: Thursday, October 3, 2019 3:08 AM
>To: Ruhl, Michael J ; dri-
>de...@lists.freedesktop.org
>Cc: intel-gfx@lists.freedesktop.org
>Subject: RE: [PATCH 2/2] drm/mm: Pack allo
From: Ville Syrjälä
The current "disable C3+" workaround for the delayed vblank
irqs on i945gm no longer works. I'm not sure what changed, but
now I need to also disable C2. I also got my hands on a i915gm
machine that suffers from the same issue.
After some furious poking of registers I managed
Keep track of the GEM contexts underneath i915->gem.contexts and assign
them their own lock for the purposes of list management.
v2: Focus on lock tracking; ctx->vm is protected by ctx->mutex
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
Avoid kernel_context_close() underneath timeline->mu
Quoting Ville Syrjala (2019-10-03 15:02:31)
> From: Ville Syrjälä
>
> The current "disable C3+" workaround for the delayed vblank
> irqs on i945gm no longer works. I'm not sure what changed, but
> now I need to also disable C2. I also got my hands on a i915gm
> machine that suffers from the same
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Chris Wilson
>Sent: Thursday, October 3, 2019 9:24 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: dri-de...@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH v3] dma-fence: Serialise signal en
On Thu, Oct 03, 2019 at 01:52:58PM +0530, Sharma, Shashank wrote:
>
> On 9/25/2019 7:25 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Add a second table to the cea modes with VIC >= 193.
> >
> > Cc: Hans Verkuil
> > Cc: Shashank Sharma
> > Signed-off-by: Ville Syrjälä
> > ---
> >
On Thu, Oct 03, 2019 at 01:59:42PM +0530, Sharma, Shashank wrote:
>
> On 9/25/2019 7:25 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Now that the cea mode handling is not 100% tied to the single
> > array the dummy VIC 0 mode is pretty much pointles. Throw it
> > out.
> >
> > Cc: Hans
On Thu, Oct 03, 2019 at 03:12:11PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2019-10-03 15:02:31)
> > From: Ville Syrjälä
> >
> > The current "disable C3+" workaround for the delayed vblank
> > irqs on i945gm no longer works. I'm not sure what changed, but
> > now I need to also disable
Quoting Ruhl, Michael J (2019-10-03 15:12:38)
> >-Original Message-
> >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> >Chris Wilson
> >Sent: Thursday, October 3, 2019 9:24 AM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: dri-de...@lists.freedesktop.org
> >Su
Keep track of the GEM contexts underneath i915->gem.contexts and assign
them their own lock for the purposes of list management.
v2: Focus on lock tracking; ctx->vm is protected by ctx->mutex
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
Another missed __assign_ppgtt inside the mock.
---
== Series Details ==
Series: drm/i915/tgl: Add the Thunderbolt PLL divider values (rev3)
URL : https://patchwork.freedesktop.org/series/67498/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2a79d1c605b4 drm/i915/tgl: Add the Thunderbolt PLL divider values
-:33: CHECK:CAMELCASE:
>-Original Message-
>From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
>Sent: Thursday, October 3, 2019 10:19 AM
>To: Ruhl, Michael J ; intel-
>g...@lists.freedesktop.org
>Cc: dri-de...@lists.freedesktop.org
>Subject: RE: [Intel-gfx] [PATCH v3] dma-fence: Serialise signal enabling
>(dma_
On 03/10/2019 15:18, Chris Wilson wrote:
Quoting Ruhl, Michael J (2019-10-03 15:12:38)
-Original Message-
From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
Chris Wilson
Sent: Thursday, October 3, 2019 9:24 AM
To: intel-gfx@lists.freedesktop.org
Cc: dri-de...@
== Series Details ==
Series: drm/i915/tgl: Add the Thunderbolt PLL divider values (rev3)
URL : https://patchwork.freedesktop.org/series/67498/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6997 -> Patchwork_14649
Summary
--
On Mon, Sep 30, 2019 at 05:55:36PM -0700, José Roberto de Souza wrote:
> This is required for legacy/static TC ports as IOM is not aware of
> the connection and will not trigger the TC cold exit.
>
> BSpec: 21750
> BSpsc: 49294
> Cc: Imre Deak
> Cc: Lucas De Marchi
> Signed-off-by: José Roberto
Driver changes mainly to process the request coming from Test equipment
as short pulse hpd interrupt to change link-pattern/v-swing/pre-emphasis
Complete auto test suite takes much lesser time than manual run.
Overall design:
--
Automate test request will come to source device as HDP s
This patch process phy compliance request by programming requested
vswing, pre-emphasis and test pattern.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 62 +
1 file changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.
DP_COMP_CTL and DP_COMP_PAT register used to program DP
compliance pattern.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_reg.h | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index eefd789b9
set pattern in DP_COMP_CTL.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 55 +
1 file changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index a19141fc672e..93b1ce80c174
During phy complaince auto test mode source need to read
requested test pattern from sink through DPCD. After processing
the request source need to set the pattern. So set/get method
added in drm layer as it is DP protocol.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/drm_dp_helper.c | 77 ++
vswing/pre-emphasis adjustment calculation is needed in processing
of auto phy compliance request other than link training, so moved
the same function in intel_dp.c.
No functional change.
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dp.c | 32 +++
dr
During DP phy compliance auto test mode, sink will request
combination of different test pattern with differnt level of
vswing, pre-emphasis. Function added to prepare for it.
Signed-off-by: Animesh Manna
---
.../drm/i915/display/intel_display_types.h| 1 +
drivers/gpu/drm/i915/display/inte
For fast preempt-resets, error capture is skipped, so disable
preempt-resets before checking the error state. While thinking ahead, be
prepared for when the modparams are not accessible.
Signed-off-by: Chris Wilson
---
lib/igt_gt.c | 7 ---
tests/i915/i915_hangman.c | 7 ---
== Series Details ==
Series: drm/i915/execlists: Skip redundant resubmission
URL : https://patchwork.freedesktop.org/series/67537/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6997 -> Patchwork_14650
Summary
---
**S
On Wed, Oct 02, 2019 at 07:25:05PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> To avoid accidentally breaking things in the future add a
> comment explaining why we misconfigure the pipe_mask.
>
> Also toss in a TODO for investigating a single encoder
> approach as opposed to the encod
== Series Details ==
Series: DC3CO Support for TGL test with DC3CO IGT
URL : https://patchwork.freedesktop.org/series/67525/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6996_full -> Patchwork_14642_full
Summary
---
== Series Details ==
Series: series starting with [v3] dma-fence: Serialise signal enabling
(dma_fence_enable_sw_signaling) (rev9)
URL : https://patchwork.freedesktop.org/series/67529/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d8ea554e76ab dma-fence: Serialise signal enabl
== Series Details ==
Series: drm/i915: Implement a better i945gm vblank irq vs. C-states workaround
URL : https://patchwork.freedesktop.org/series/67541/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6998 -> Patchwork_14651
== Series Details ==
Series: series starting with [v3] dma-fence: Serialise signal enabling
(dma_fence_enable_sw_signaling) (rev9)
URL : https://patchwork.freedesktop.org/series/67529/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6998 -> Patchwork_14652
=
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