Re: [Intel-gfx] [PATCH -next] treewide: remove unused argument in lock_release()

On Thu, Sep 19, 2019 at 12:09:40PM -0400, Qian Cai wrote: > Since the commit b4adfe8e05f1 ("locking/lockdep: Remove unused argument > in __lock_release"), @nested is no longer used in lock_release(), so > remove it from all lock_release() calls and friends. Right; I never did this cleanup for not

Re: [Intel-gfx] [PATCH] drm/i915/tgl: Magic udelay to relieve the random lockups with multiple engines

Quoting Andi Shyti (2019-09-29 21:25:54) > Hi Chris, > > > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c > > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c > > @@ -1186,6 +1186,21 @@ static void execlists_submit_ports(struct > > intel_engine_cs *engine) > > /* we need to manually load the submit que

[Intel-gfx] [PATCH v2] drm/i915/tgl: Magic interrupt shadow to relieve some random lockups

My current theory is that this masks interrupt delivery to the local CPU during a critical phase. Purely papering over the symptoms with a delay plucked out of thin air from testing on tgl1-gem, refined slightly by just waiting for the next ack (though technically the next CS event may not be the c

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Magic udelay to relieve the random lockups with multiple engines (rev2)

== Series Details == Series: drm/i915/tgl: Magic udelay to relieve the random lockups with multiple engines (rev2) URL : https://patchwork.freedesktop.org/series/67365/ State : warning == Summary == $ dim checkpatch origin/drm-tip ffe0e0f4ce51 drm/i915/tgl: Magic interrupt shadow to relieve s

Re: [Intel-gfx] [PATCH 10/22] drm/i915/selftests: add write-dword test for LMEM

On 27/09/2019 21:42, Chris Wilson wrote: Quoting Matthew Auld (2019-09-27 18:33:57) + i = 0; + engines = i915_gem_context_lock_engines(ctx); + do { + u32 rng = prandom_u32_state(&prng); + u32 dword = offset_in_page(rng) / 4; + + ce = en

Re: [Intel-gfx] [PATCH] drm/i915: Initialise breadcrumb lists on the virtual engine

On 29/09/2019 09:33, Chris Wilson wrote: With deferring the breadcrumb signalling to the virtual engine (thanks preempt-to-busy) we need to make sure the lists and irq-worker are ready to send a signal. Fixes: cb2377a919bb ("drm/i915: Fixup preempt-to-busy vs reset of a virtual request") Signe

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Magic udelay to relieve the random lockups with multiple engines (rev2)

== Series Details == Series: drm/i915/tgl: Magic udelay to relieve the random lockups with multiple engines (rev2) URL : https://patchwork.freedesktop.org/series/67365/ State : success == Summary == CI Bug Log - changes from CI_DRM_6973 -> Patchwork_14581 =

Re: [Intel-gfx] [PATCH v2] drm/i915/userptr: Never allow userptr into the mappable GGTT

On 28/09/2019 09:25, Chris Wilson wrote: Daniel Vetter uncovered a nasty cycle in using the mmu-notifiers to invalidate userptr objects which also happen to be pulled into GGTT mmaps. That is when we unbind the userptr object (on mmu invalidation), we revoke all CPU mmaps, which may then recurse

[Intel-gfx] [PATCH i-g-t] i915/gem_mmap_gtt: Reduce RSS for fault-concurrent

The intent of exercising parallel page fault is not necessarily to exercise parallel swap-in (we can safely rely on that being well tested and is orthogonal to page faulting), but to make sure that our object and GGTT locking is exercised. We can safely reduce our RSS without loss of coverage. Furt

Re: [Intel-gfx] [PATCH i-g-t v2] i915/gem_ctx_isolation: Check nonpriv values are kept across switch

On Fri, Sep 27, 2019 at 02:28:34PM +0100, Chris Wilson wrote: > Verify that the values we store in our nonpriv context image registers > are restored after a switch. > > v2: Use explicit ordering to ensure we force the context switch back and > forth in between the register writes and their read.

Re: [Intel-gfx] [PATCH 10/22] drm/i915/selftests: add write-dword test for LMEM

Quoting Matthew Auld (2019-09-30 10:58:15) > On 27/09/2019 21:42, Chris Wilson wrote: > > Quoting Matthew Auld (2019-09-27 18:33:57) > >> + i = 0; > >> + engines = i915_gem_context_lock_engines(ctx); > >> + do { > >> + u32 rng = prandom_u32_state(&prng); > >> +

[Intel-gfx] [PATCH] drm/i915/selftests: Exercise context switching in parallell

We currently test context switching on each engine as a basic stress test (just verifying that nothing explodes if we execute 2 requests from different contexts sequentially). What we have not tested is what happens if we try and do so on all available engines simultaneously, putting our SW and the

Re: [Intel-gfx] [PATCH v2] drm/i915/userptr: Never allow userptr into the mappable GGTT

Quoting Tvrtko Ursulin (2019-09-30 11:33:22) > > On 28/09/2019 09:25, Chris Wilson wrote: > > Daniel Vetter uncovered a nasty cycle in using the mmu-notifiers to > > invalidate userptr objects which also happen to be pulled into GGTT > > mmaps. That is when we unbind the userptr object (on mmu inv

[Intel-gfx] [PATCH v2] drm/i915/selftests: Exercise context switching in parallel

We currently test context switching on each engine as a basic stress test (just verifying that nothing explodes if we execute 2 requests from different contexts sequentially). What we have not tested is what happens if we try and do so on all available engines simultaneously, putting our SW and the

Re: [Intel-gfx] [PATCH v9 7/7] drm/i915/tgl: Add DC3CO counter in i915_dmc_info

On Fri, Sep 27, 2019 at 10:27:44PM +0530, Anshuman Gupta wrote: > On 2019-09-27 at 19:38:49 +0300, Imre Deak wrote: > > On Thu, Sep 26, 2019 at 08:26:21PM +0530, Anshuman Gupta wrote: > > > Adding DC3CO counter in i915_dmc_info debugfs will be > > > useful for DC3CO validation. > > > DMC firmware u

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Exercise context switching in parallell (rev2)

== Series Details == Series: drm/i915/selftests: Exercise context switching in parallell (rev2) URL : https://patchwork.freedesktop.org/series/67395/ State : warning == Summary == $ dim checkpatch origin/drm-tip b214c64b2862 drm/i915/selftests: Exercise context switching in parallel -:32: WARN

Re: [Intel-gfx] [PATCH v2] drm/i915/tgl: Magic interrupt shadow to relieve some random lockups

Chris Wilson writes: > My current theory is that this masks interrupt delivery to the local CPU > during a critical phase. Purely papering over the symptoms with a delay > plucked out of thin air from testing on tgl1-gem, refined slightly by > just waiting for the next ack (though technically the

Re: [Intel-gfx] [PATCH v2] drm/i915/tgl: Magic interrupt shadow to relieve some random lockups

Quoting Mika Kuoppala (2019-09-30 13:02:49) > Chris Wilson writes: > > > My current theory is that this masks interrupt delivery to the local CPU > > during a critical phase. Purely papering over the symptoms with a delay > > plucked out of thin air from testing on tgl1-gem, refined slightly by >

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/tgl: Magic udelay to relieve the random lockups with multiple engines (rev2)

== Series Details == Series: drm/i915/tgl: Magic udelay to relieve the random lockups with multiple engines (rev2) URL : https://patchwork.freedesktop.org/series/67365/ State : success == Summary == CI Bug Log - changes from CI_DRM_6973_full -> Patchwork_14581_full ===

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Exercise context switching in parallell (rev2)

== Series Details == Series: drm/i915/selftests: Exercise context switching in parallell (rev2) URL : https://patchwork.freedesktop.org/series/67395/ State : success == Summary == CI Bug Log - changes from CI_DRM_6973 -> Patchwork_14582 Sum

[Intel-gfx] [CI] RFT drm/i915/tgl: Re-enable rps

--- drivers/gpu/drm/i915/i915_pci.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index ea53dfe2fba0..cd1fbd71dc31 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -807,7 +807,6 @@ static co

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for RFT drm/i915/tgl: Re-enable rps

== Series Details == Series: RFT drm/i915/tgl: Re-enable rps URL : https://patchwork.freedesktop.org/series/67398/ State : warning == Summary == $ dim checkpatch origin/drm-tip ac469e3ebe6f RFT drm/i915/tgl: Re-enable rps -:8: WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropr

[Intel-gfx] ✓ Fi.CI.BAT: success for RFT drm/i915/tgl: Re-enable rps

== Series Details == Series: RFT drm/i915/tgl: Re-enable rps URL : https://patchwork.freedesktop.org/series/67398/ State : success == Summary == CI Bug Log - changes from CI_DRM_6973 -> Patchwork_14583 Summary --- **SUCCESS** No r

[Intel-gfx] [PATCH i-g-t v2] i915/gem_mmap_gtt: Reduce RSS for fault-concurrent

The intent of exercising parallel page fault is not necessarily to exercise parallel swap-in (we can safely rely on that being well tested and is orthogonal to page faulting), but to make sure that our object and GGTT locking is exercised. We can safely reduce our RSS without loss of coverage. Furt

[Intel-gfx] [PATCH 1/4] drm/rect: Add drm_rect_translate_to()

From: Ville Syrjälä Add a helper to translate a rectangle to an absolute position. Signed-off-by: Ville Syrjälä --- include/drm/drm_rect.h | 14 ++ 1 file changed, 14 insertions(+) diff --git a/include/drm/drm_rect.h b/include/drm/drm_rect.h index 6195820aa5c5..fc7c14627ee2 100644

[Intel-gfx] [PATCH 3/4] drm/i915: Use drm_rect_translate_to()

From: Ville Syrjälä Use the newly introduced drm_rect_translate_to() instead of hand rolling it. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 10 -- 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_displ

[Intel-gfx] [PATCH 4/4] drm/i915: Use drm_rect_init()

From: Ville Syrjälä Use the new drm_rect_init() helper where appropriate. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 10 ++ drivers/gpu/drm/i915/display/intel_sprite.c | 6 ++ 2 files changed, 4 insertions(+), 12 deletions(-) diff --git a/dri

[Intel-gfx] [PATCH 2/4] drm/rect: Add drm_rect_init()

From: Ville Syrjälä Add a helper to initialize a rectangle from x/y/w/h information. Signed-off-by: Ville Syrjälä --- include/drm/drm_rect.h | 17 + 1 file changed, 17 insertions(+) diff --git a/include/drm/drm_rect.h b/include/drm/drm_rect.h index fc7c14627ee2..cd0106135b6a 1

Re: [Intel-gfx] [PATCH v2] drm/i915/selftests: Exercise context switching in parallel

On 30/09/2019 12:31, Chris Wilson wrote: We currently test context switching on each engine as a basic stress test (just verifying that nothing explodes if we execute 2 requests from different contexts sequentially). What we have not tested is what happens if we try and do so on all available en

Re: [Intel-gfx] [PATCH v2] drm/i915/selftests: Exercise context switching in parallel

Quoting Tvrtko Ursulin (2019-09-30 14:47:26) > > On 30/09/2019 12:31, Chris Wilson wrote: > > +static int live_parallel_switch(void *arg) > > +{ > > + struct drm_i915_private *i915 = arg; > > + static int (* const func[])(void *arg) = { > > + __live_parallel_switch1, > > +

Re: [Intel-gfx] [PATCH 11/23] drm/i915: Try to make bigjoiner work in atomic check.

Op 26-09-2019 om 05:48 schreef Matt Roper: > On Fri, Sep 20, 2019 at 01:42:23PM +0200, Maarten Lankhorst wrote: >> When the clock is higher than the dotclock, try with 2 pipes enabled. >> If we can enable 2, then we will go into big joiner mode, and steal >> the adjacent crtc. >> >> This only links

Re: [Intel-gfx] [PATCH v3 1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync

On Sun, Sep 22, 2019 at 10:08:02AM -0700, Manasi Navare wrote: > In case of tiled displays when the two tiles are sent across two CRTCs > over two separate DP SST connectors, we need a mechanism to synchronize > the two CRTCs and their corresponding transcoders. > So use the master-slave mode where

[Intel-gfx] [PATCH v3] drm/i915/selftests: Exercise context switching in parallel

We currently test context switching on each engine as a basic stress test (just verifying that nothing explodes if we execute 2 requests from different contexts sequentially). What we have not tested is what happens if we try and do so on all available engines simultaneously, putting our SW and the

[PATCH v2] lib/string-choice: add yesno(), onoff(), enableddisabled(), plural() helpers

The kernel has plenty of ternary operators to choose between constant strings, such as condition ? "yes" : "no", as well as value == 1 ? "" : "s": $ git grep '? "yes" : "no"' | wc -l 258 $ git grep '? "on" : "off"' | wc -l 204 $ git grep '? "enabled" : "disabled"' | wc -l 196 $ git grep '? "" : "s

Re: [Intel-gfx] [PATCH v3] drm/i915/selftests: Exercise context switching in parallel

Quoting Chris Wilson (2019-09-30 15:15:22) > We currently test context switching on each engine as a basic stress > test (just verifying that nothing explodes if we execute 2 requests from > different contexts sequentially). What we have not tested is what > happens if we try and do so on all avail

Re: [Intel-gfx] [PATCH v3 2/6] drm/i915/display/icl: Enable TRANSCODER PORT SYNC for tiled displays across separate ports

On Sun, Sep 22, 2019 at 10:08:03AM -0700, Manasi Navare wrote: > In case of tiled displays where different tiles are displayed across > different ports, we need to synchronize the transcoders involved. > This patch implements the transcoder port sync feature for > synchronizing one master transcode

Re: [Intel-gfx] [PATCH v5 3/6] drm/i915/display/icl: HW state readout for transcoder port sync config

On Thu, Sep 26, 2019 at 05:11:10PM -0700, Manasi Navare wrote: > After the state is committed, we readout the HW registers and compare > the HW state with the SW state that we just committed. > For Transcdoer port sync, we add master_transcoder and the > salves bitmask to the crtc_state, hence we n

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Exercise context switching in parallell (rev3)

== Series Details == Series: drm/i915/selftests: Exercise context switching in parallell (rev3) URL : https://patchwork.freedesktop.org/series/67395/ State : warning == Summary == $ dim checkpatch origin/drm-tip b6e359fa23f7 drm/i915/selftests: Exercise context switching in parallel -:36: WARN

Re: [Intel-gfx] [CI] RFT drm/i915/tgl: Re-enable rps

Quoting Chris Wilson (2019-09-30 13:39:29) > --- > drivers/gpu/drm/i915/i915_pci.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c > index ea53dfe2fba0..cd1fbd71dc31 100644 > --- a/drivers/gpu/drm/i915/i915_pci.c > +++ b/dr

Re: [PATCH v2] lib/string-choice: add yesno(), onoff(), enableddisabled(), plural() helpers

On 30/09/2019 16.18, Jani Nikula wrote: > The kernel has plenty of ternary operators to choose between constant > strings, such as condition ? "yes" : "no", as well as value == 1 ? "" : > "s": > > > --- > > v2: add string-choice.[ch] to not clutter kernel.h and to actually save > space on string

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/4] drm/rect: Add drm_rect_translate_to()

== Series Details == Series: series starting with [1/4] drm/rect: Add drm_rect_translate_to() URL : https://patchwork.freedesktop.org/series/67402/ State : success == Summary == CI Bug Log - changes from CI_DRM_6973 -> Patchwork_14584 Summa

[Intel-gfx] [PATCH v4] drm/i915/selftests: Exercise context switching in parallel

We currently test context switching on each engine as a basic stress test (just verifying that nothing explodes if we execute 2 requests from different contexts sequentially). What we have not tested is what happens if we try and do so on all available engines simultaneously, putting our SW and the

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for lib/string-choice: add yesno(), onoff(), enableddisabled(), plural() helpers

== Series Details == Series: lib/string-choice: add yesno(), onoff(), enableddisabled(), plural() helpers URL : https://patchwork.freedesktop.org/series/67405/ State : warning == Summary == $ dim checkpatch origin/drm-tip 776ae2f2dd01 lib/string-choice: add yesno(), onoff(), enableddisabled()

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Exercise context switching in parallell (rev3)

== Series Details == Series: drm/i915/selftests: Exercise context switching in parallell (rev3) URL : https://patchwork.freedesktop.org/series/67395/ State : success == Summary == CI Bug Log - changes from CI_DRM_6973 -> Patchwork_14585 Sum

[Intel-gfx] ✓ Fi.CI.BAT: success for lib/string-choice: add yesno(), onoff(), enableddisabled(), plural() helpers

== Series Details == Series: lib/string-choice: add yesno(), onoff(), enableddisabled(), plural() helpers URL : https://patchwork.freedesktop.org/series/67405/ State : success == Summary == CI Bug Log - changes from CI_DRM_6973 -> Patchwork_14586 ==

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/selftests: Exercise context switching in parallell (rev4)

== Series Details == Series: drm/i915/selftests: Exercise context switching in parallell (rev4) URL : https://patchwork.freedesktop.org/series/67395/ State : warning == Summary == $ dim checkpatch origin/drm-tip d759ff077352 drm/i915/selftests: Exercise context switching in parallel -:36: WARN

Re: [Intel-gfx] [PATCH v3 4/6] drm/i915/display/icl: Enable master-slaves in trans port sync

On Sun, Sep 22, 2019 at 10:08:05AM -0700, Manasi Navare wrote: > As per the display enable sequence, we need to follow the enable sequence > for slaves first with DP_TP_CTL set to Idle and configure the transcoder > port sync register to select the corersponding master, then follow the > enable seq

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Exercise context switching in parallell (rev2)

== Series Details == Series: drm/i915/selftests: Exercise context switching in parallell (rev2) URL : https://patchwork.freedesktop.org/series/67395/ State : success == Summary == CI Bug Log - changes from CI_DRM_6973_full -> Patchwork_14582_full ===

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/selftests: Exercise context switching in parallell (rev4)

== Series Details == Series: drm/i915/selftests: Exercise context switching in parallell (rev4) URL : https://patchwork.freedesktop.org/series/67395/ State : success == Summary == CI Bug Log - changes from CI_DRM_6973 -> Patchwork_14587 Sum

Re: [Intel-gfx] [PATCH v4] drm/i915/selftests: Exercise context switching in parallel

On 30/09/2019 15:49, Chris Wilson wrote: We currently test context switching on each engine as a basic stress test (just verifying that nothing explodes if we execute 2 requests from different contexts sequentially). What we have not tested is what happens if we try and do so on all available en

[Intel-gfx] ✓ Fi.CI.IGT: success for RFT drm/i915/tgl: Re-enable rps

== Series Details == Series: RFT drm/i915/tgl: Re-enable rps URL : https://patchwork.freedesktop.org/series/67398/ State : success == Summary == CI Bug Log - changes from CI_DRM_6973_full -> Patchwork_14583_full Summary --- **SUCCESS

[Intel-gfx] [PATCH v10 0/6] DC3CO Support for TGL

This v10 revision has most of the chages related to dc3co series code refactoring and fixes for few review comment provided by imre. Anshuman Gupta (6): drm/i915/tgl: Add DC3CO required register and bits drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask drm/i915/tgl: Enable D

[Intel-gfx] [PATCH v10 1/6] drm/i915/tgl: Add DC3CO required register and bits

Adding following definition to i915_reg.h 1. DC_STATE_EN register DC3CO bit fields and masks. DC3CO enable bit will be used by driver to make DC3CO ready for DMC f/w and status bit will be used as DC3CO entry status. 2. Transcoder EXITLINE register and its bit fields and mask. Transcode

[Intel-gfx] [PATCH v10 5/6] drm/i915/tgl: Switch between dc3co and dc5 based on display idleness

DC3CO is useful power state, when DMC detects PSR2 idle frame while an active video playback, playing 30fps video on 60hz panel is the classic example of this use case. B.Specs:49196 has a restriction to enable DC3CO only for Video Playback. It will be worthy to enable DC3CO after completion of ea

[Intel-gfx] [PATCH v10 3/6] drm/i915/tgl: Enable DC3CO state in "DC Off" power well

Add target_dc_state and used by set_target_dc_state API in order to enable DC3CO state with existing DC states. target_dc_state will enable/disable the desired DC state in DC_STATE_EN reg when "DC Off" power well gets disable/enable. v2: commit log improvement. v3: Used intel_wait_for_register to

[Intel-gfx] [PATCH v10 4/6] drm/i915/tgl: Do modeset to enable and configure DC3CO exitline

DC3CO enabling B.Specs sequence requires to enable end configure exit scanlines to TRANS_EXITLINE register, programming this register has to be part of modeset sequence as this can't be change when transcoder or port is enabled. When system boots with only eDP panel there may not be real modeset as

[Intel-gfx] [PATCH v10 2/6] drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask

Enable dc3co state in enable_dc module param and add dc3co enable mask to allowed_dc_mask and gen9_dc_mask. v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6 independently. [Animesh] v2: Using a switch statement for cleaner code. [Animesh] Cc: Jani Nikula Cc: Imre Deak Cc: A

[Intel-gfx] [PATCH v10 6/6] drm/i915/tgl: Add DC3CO counter in i915_dmc_info

Adding DC3CO counter in i915_dmc_info debugfs will be useful for DC3CO validation. DMC firmware uses DMC_DEBUG3 register as DC3CO counter register on TGL, as per B.Specs DMC_DEBUG3 is general purpose register. v1: comment modification for DMC_DBUG3. using GEN >= 12 check instead of IS_TIGERLAK

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/4] drm/rect: Add drm_rect_translate_to()

== Series Details == Series: series starting with [1/4] drm/rect: Add drm_rect_translate_to() URL : https://patchwork.freedesktop.org/series/67402/ State : success == Summary == CI Bug Log - changes from CI_DRM_6973_full -> Patchwork_14584_full =

[Intel-gfx] [PATCH] drm/i915: Fix g4x sprite scaling stride check with GTT remapping

From: Ville Syrjälä I forgot to update the g4x sprite scaling stride check when GTT remapping was introduced. The stride of the original framebuffer is irrelevant when remapping is used and instead we want to check the stride of the remapped view. Also drop the duplicate width_bytes check. We al

Re: [Intel-gfx] [PATCH] Make is_signed_type() simpler

>-Original Message- >From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of >Alexey Dobriyan >Sent: Sunday, September 29, 2019 4:06 PM >To: a...@linux-foundation.org >Cc: intel-gfx@lists.freedesktop.org; li...@rasmusvillemoes.dk; linux- >ker...@vger.kernel.org; rost..

Re: [Intel-gfx] [PATCH v3 1/6] drm/i915/display/icl: Save Master transcoder in slave's crtc_state for Transcoder Port Sync

On Sun, Sep 22, 2019 at 10:08:02AM -0700, Manasi Navare wrote: In case of tiled displays when the two tiles are sent across two CRTCs over two separate DP SST connectors, we need a mechanism to synchronize the two CRTCs and their corresponding transcoders. So use the master-slave mode where there

[Intel-gfx] ✗ Fi.CI.BUILD: failure for Make is_signed_type() simpler

== Series Details == Series: Make is_signed_type() simpler URL : https://patchwork.freedesktop.org/series/67413/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/generated/compile.h CC [M] drivers/g

[Intel-gfx] DDC on Thinkpad x220

Hi! Thinkpad X220 should be new enough machine to talk DDC to the monitors, right? And my monitor has DDC enable/disable in the menu, so it should support it, too... But I don't have /dev/i2c* and did not figure out how to talk to the monitor. Is the support there in the kernel? What do I need to

[Intel-gfx] ✓ Fi.CI.IGT: success for lib/string-choice: add yesno(), onoff(), enableddisabled(), plural() helpers

== Series Details == Series: lib/string-choice: add yesno(), onoff(), enableddisabled(), plural() helpers URL : https://patchwork.freedesktop.org/series/67405/ State : success == Summary == CI Bug Log - changes from CI_DRM_6973_full -> Patchwork_14586_full

[Intel-gfx] ✓ Fi.CI.BAT: success for DC3CO Support for TGL (rev13)

== Series Details == Series: DC3CO Support for TGL (rev13) URL : https://patchwork.freedesktop.org/series/64923/ State : success == Summary == CI Bug Log - changes from CI_DRM_6976 -> Patchwork_14589 Summary --- **SUCCESS** No reg

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Refuse modes with hdisplay==4096 on pre-HSW DP (rev2)

== Series Details == Series: series starting with [1/2] drm/i915: Refuse modes with hdisplay==4096 on pre-HSW DP (rev2) URL : https://patchwork.freedesktop.org/series/63892/ State : success == Summary == CI Bug Log - changes from CI_DRM_6976 -> Patchwork_14590

Re: [Intel-gfx] [PATCH v5 3/6] drm/i915/display/icl: HW state readout for transcoder port sync config

On Thu, Sep 26, 2019 at 05:11:10PM -0700, Manasi Navare wrote: After the state is committed, we readout the HW registers and compare the HW state with the SW state that we just committed. For Transcdoer port sync, we add master_transcoder and the salves bitmask to the crtc_state, hence we need to

[Intel-gfx] [CI] drm/i915/tgl: Magic interrupt shadow to relieve some random lockups

My current theory is that this masks interrupt delivery to the local CPU during a critical phase. Purely papering over the symptoms with a delay plucked out of thin air from testing on tgl1-gem, refined slightly by just waiting for the next ack (though technically the next CS event may not be the c

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/selftests: Exercise context switching in parallell (rev4)

== Series Details == Series: drm/i915/selftests: Exercise context switching in parallell (rev4) URL : https://patchwork.freedesktop.org/series/67395/ State : success == Summary == CI Bug Log - changes from CI_DRM_6973_full -> Patchwork_14587_full ===

Re: [Intel-gfx] [PATCH] drm/i915/dp: Fix DP MST error after unplugging TypeC cable

Could anyone please review the patch below & let me know if any other ideas please? https://patchwork.freedesktop.org/patch/332806/?series=66837&rev=3 Thanks, > -Original Message- > From: S, Srinivasan > Sent: Wednesday, September 25, 2019 8:33 PM > To: 'Ville Syrjälä' > Cc: Navare, Ma

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Fix g4x sprite scaling stride check with GTT remapping

== Series Details == Series: drm/i915: Fix g4x sprite scaling stride check with GTT remapping URL : https://patchwork.freedesktop.org/series/67415/ State : success == Summary == CI Bug Log - changes from CI_DRM_6976 -> Patchwork_14591 Summa

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Magic interrupt shadow to relieve some random lockups

== Series Details == Series: drm/i915/tgl: Magic interrupt shadow to relieve some random lockups URL : https://patchwork.freedesktop.org/series/67416/ State : warning == Summary == $ dim checkpatch origin/drm-tip 781c7510e4df drm/i915/tgl: Magic interrupt shadow to relieve some random lockups

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc: Update H2G enable logging action definition

On 9/28/19 3:36 AM, Patchwork wrote: == Series Details == Series: drm/i915/guc: Update H2G enable logging action definition URL : https://patchwork.freedesktop.org/series/67351/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6970_full -> Patchwork_14570_full ===

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/tgl: Magic interrupt shadow to relieve some random lockups

== Series Details == Series: drm/i915/tgl: Magic interrupt shadow to relieve some random lockups URL : https://patchwork.freedesktop.org/series/67416/ State : success == Summary == CI Bug Log - changes from CI_DRM_6976 -> Patchwork_14592 Su

Re: [Intel-gfx] [PATCH V2 6/8] mdev: introduce virtio device and its device ops

On Fri, 27 Sep 2019 16:25:13 + Parav Pandit wrote: > Hi Alex, > > > > -Original Message- > > From: Alex Williamson > > Sent: Tuesday, September 24, 2019 6:07 PM > > To: Jason Wang > > Cc: k...@vger.kernel.org; linux-s...@vger.kernel.org; linux- > > ker...@vger.kernel.org; dri-de..

[Intel-gfx] [PATCH v2] drm/i915/ehl: Add sysfs interface to control class-of-service

To provide shared last-level-cache isolation to cpu workloads running concurrently with gpu workloads, the gpu allocation of cache lines needs to be restricted to certain ways. Currently GPU hardware supports four class-of-service(CLOS) levels and there is an associated way-mask for each CLOS. Each

[Intel-gfx] [PATCH v7 3/3] drm/i915: Add background color hardware readout and state check

We should support readout and verification of crtc background color as we do with other pipe state. Note that our hardware holds less bits of precision than the CRTC state allows, so we need to take care to only verify the most significant bits of the color after performing readout. At boot time

[Intel-gfx] [PATCH v7 2/3] drm/i915/gen9+: Add support for pipe background color

Gen9+ platforms allow CRTC's to be programmed with a background/canvas color below the programmable planes. Let's expose this for use by compositors. v2: - Split out bgcolor sanitization and programming of csc/gamma bits to a separate patch that we can land before the ABI changes are ready to

[Intel-gfx] [PATCH v7 1/3] drm: Add CRTC background color property

Some display controllers can be programmed to present non-black colors for pixels not covered by any plane (or pixels covered by the transparent regions of higher planes). Compositors that want a UI with a solid color background can potentially save memory bandwidth by setting the CRTC background

[Intel-gfx] [PATCH v7 0/3] CRTC background color

The previous version of this series was posted in February here: https://lists.freedesktop.org/archives/dri-devel/2019-February/208068.html Right before we merged this in February Maarten noticed that we should be setting up the initial property state in a CRTC reset function (which didn'

[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/tgl: Add sysfs interface to control class-of-service (rev3)

== Series Details == Series: drm/i915/tgl: Add sysfs interface to control class-of-service (rev3) URL : https://patchwork.freedesktop.org/series/65769/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for CRTC background color (rev8)

== Series Details == Series: CRTC background color (rev8) URL : https://patchwork.freedesktop.org/series/50834/ State : warning == Summary == $ dim checkpatch origin/drm-tip ce8779b97946 drm: Add CRTC background color property -:255: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'shift' - possib

[Intel-gfx] [PATCH i-g-t] tests/kms_crtc_background_color: overhaul to match upstream ABI (v5.1)

CRTC background color kernel patches were written about 2.5 years ago and floated on the upstream mailing list, but since no opensource userspace materialized, we never actually merged them. However the corresponding IGT test did get merged and has basically been dead code ever since. A couple ye

Re: [Intel-gfx] [v8, 2/4] drm/panel: set display info in panel attach

On Sat, Sep 28, 2019 at 10:23 PM james qian wang (Arm Technology China) wrote: > > On Wed, Sep 25, 2019 at 03:58:31PM -0700, Derek Basehore wrote: > > Devicetree systems can set panel orientation via a panel binding, but > > there's no way, as is, to propagate this setting to the connector, > > wh

[Intel-gfx] ✓ Fi.CI.BAT: success for CRTC background color (rev8)

== Series Details == Series: CRTC background color (rev8) URL : https://patchwork.freedesktop.org/series/50834/ State : success == Summary == CI Bug Log - changes from CI_DRM_6979 -> Patchwork_14594 Summary --- **SUCCESS** No regr

[Intel-gfx] ✓ Fi.CI.IGT: success for DC3CO Support for TGL (rev13)

== Series Details == Series: DC3CO Support for TGL (rev13) URL : https://patchwork.freedesktop.org/series/64923/ State : success == Summary == CI Bug Log - changes from CI_DRM_6976_full -> Patchwork_14589_full Summary --- **SUCCESS**

[Intel-gfx] [PATCH] drm/i915/tc: Implement the TC cold exit sequence

This is required for legacy/static TC ports as IOM is not aware of the connection and will not trigger the TC cold exit. BSpec: 21750 BSpsc: 49294 Cc: Imre Deak Cc: Lucas De Marchi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_tc.c | 34 -

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Refuse modes with hdisplay==4096 on pre-HSW DP (rev2)

== Series Details == Series: series starting with [1/2] drm/i915: Refuse modes with hdisplay==4096 on pre-HSW DP (rev2) URL : https://patchwork.freedesktop.org/series/63892/ State : success == Summary == CI Bug Log - changes from CI_DRM_6976_full -> Patchwork_14590_full ==

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/tc: Implement the TC cold exit sequence

== Series Details == Series: drm/i915/tc: Implement the TC cold exit sequence URL : https://patchwork.freedesktop.org/series/67426/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6979 -> Patchwork_14595 Summary --- **

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fix g4x sprite scaling stride check with GTT remapping

== Series Details == Series: drm/i915: Fix g4x sprite scaling stride check with GTT remapping URL : https://patchwork.freedesktop.org/series/67415/ State : success == Summary == CI Bug Log - changes from CI_DRM_6976_full -> Patchwork_14591_full =

Re: [Intel-gfx] [PATCH i-g-t] tests/kms_crtc_background_color: overhaul to match upstream ABI (v5.1)

On 30/09/2019 19:13, Matt Roper wrote: > CRTC background color kernel patches were written about 2.5 years ago > and floated on the upstream mailing list, but since no opensource > userspace materialized, we never actually merged them. However the > corresponding IGT test did get merged and has ba

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/tgl: Magic interrupt shadow to relieve some random lockups

== Series Details == Series: drm/i915/tgl: Magic interrupt shadow to relieve some random lockups URL : https://patchwork.freedesktop.org/series/67416/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6976_full -> Patchwork_14592_full ==

[Intel-gfx] [PATCH 2/2] drm/i915: FB backing gem obj should reside in LMEM

If Local memory is supported by hardware, we want framebuffer backing gem objects from local memory. pin_to_display is failed, if the backing obj is not from LMEM. This is developed on top of LMEM Basics https://patchwork.freedesktop.org/series/67350/ v2: memory regions are correctly assigned

[Intel-gfx] [PATCH 1/2] drm/i915: Create dumb buffer from LMEM

When LMEM is supported, dumb buffer preferred to be created from LMEM. This is developed on top of LMEM Basics https://patchwork.freedesktop.org/series/67350/ v2: Parameters are reshuffled. [Chris] Signed-off-by: Ramalingam C cc: Matthew Auld --- drivers/gpu/drm/i915/i915_gem.c | 18 +++

[Intel-gfx] ✗ Fi.CI.BUILD: failure for series starting with [1/2] drm/i915: Create dumb buffer from LMEM

== Series Details == Series: series starting with [1/2] drm/i915: Create dumb buffer from LMEM URL : https://patchwork.freedesktop.org/series/67428/ State : failure == Summary == CALLscripts/checksyscalls.sh CALLscripts/atomic/check-atomics.sh DESCEND objtool CHK include/gen

[Intel-gfx] [PATCH] drm/i915/color: fix broken display in icl+

Premature gamma lut prepration and loading which was getting reflected in first modeset causing different colors on screen during boot. Issue: In BIOS, gamma is disabled by default. However, legacy_read_luts() was getting called even before the legacy_load_luts() which was setting crtc_state->base

Re: [Intel-gfx] [PATCH v3 35/37] drm/i915: Introduce GEM_OBJECT_SETPARAM with I915_PARAM_MEMORY_REGION

On Fri, Aug 09, 2019 at 11:26:41PM +0100, Matthew Auld wrote: From: Abdiel Janulgue This call will specify which memory region an object should be placed. Note that changing the object's backing storage should be immediately done after an object is created or if it's not yet in use, otherwise

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/color: fix broken display in icl+

== Series Details == Series: drm/i915/color: fix broken display in icl+ URL : https://patchwork.freedesktop.org/series/67429/ State : warning == Summary == $ dim checkpatch origin/drm-tip 5d9d27e6eccf drm/i915/color: fix broken display in icl+ -:31: WARNING:SUSPECT_CODE_INDENT: suspect code in