Quoting Ramalingam C (2019-09-26 06:21:34)
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> index 0f33da5e541d..e6f8426dedff 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.c
> @@ -
On Thu, 26 Sep 2019 01:03:20 +0200, Summers, Stuart
wrote:
On Wed, 2019-09-25 at 15:21 -0700, Daniele Ceraolo Spurio wrote:
The HuC FW has silently switched to encoding the version the same way
as
the GuC FW does, i.e. major.minor.patch instead of just major.minor.
All
the current blobs foll
== Series Details ==
Series: series starting with [1/3] drm/dp/mst: Reduce nested ifs
URL : https://patchwork.freedesktop.org/series/67222/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6956_full -> Patchwork_14531_full
Sum
On Tuesday, 2019-09-24 15:58:56 +0300, Jani Nikula wrote:
> Hi all, v2 of [1], a little refactoring around drm_debug access to
> abstract it better. There shouldn't be any functional changes.
>
> I'd appreciate acks for merging the lot via drm-misc. If there are any
> objections to that, we'll nee
On 2019/9/26 上午8:48, Tian, Kevin wrote:
+};
I'm not sure how stable above ops are.
It's the kernel internal API, so there's no strict requirement for this.
We will export a version value for userspace for compatibility.
Does it make sense if defining
just two callbacks here, e.g. vq_ctrl an
On Thu, Sep 26, 2019 at 12:04:46PM +0800, Jason Wang wrote:
> > > > I'm not sure how stable above ops are.
> > > It's the kernel internal API, so there's no strict requirement for this.
> > > We
> > > will export a version value for userspace for compatibility.
> > Given it's tied to virtio we pro
== Series Details ==
Series: drm/edid: Add new modes from CTA-861-G (rev2)
URL : https://patchwork.freedesktop.org/series/63554/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6956_full -> Patchwork_14532_full
Summary
--
Op 25-09-2019 om 23:42 schreef Matt Roper:
> On Wed, Sep 25, 2019 at 04:59:01PM +0200, Maarten Lankhorst wrote:
>> This can all be done from the intel_update_crtc function. Split out the
>> pipe update into a separate function, just like is done for the planes.
>> Pull in all the changes done durin
On 26/09/2019 06:21, Ramalingam C wrote:
If Local memory is supported by hardware, we want framebuffer backing
gem objects out of local memory.
If local memory is supported and gem object if not from local memory we
migrate the obj into local memory. And once framebuffer is created we
block the
On 26/09/2019 06:21, Ramalingam C wrote:
When LMEM is supported, dumb buffer preferred to be created from LMEM.
This is developed on top of v3 LMEM series
https://patchwork.freedesktop.org/series/56683/.
v2:
Parameters are reshuffled. [Chris]
Signed-off-by: Ramalingam C
cc: Matthew Auld
On 2019-09-26 at 09:55:16 +0100, Tvrtko Ursulin wrote:
>
> On 26/09/2019 06:21, Ramalingam C wrote:
> > When LMEM is supported, dumb buffer preferred to be created from LMEM.
> >
> > This is developed on top of v3 LMEM series
> > https://patchwork.freedesktop.org/series/56683/.
> >
> > v2:
> >
On 2019-09-26 at 09:53:03 +0100, Tvrtko Ursulin wrote:
>
> On 26/09/2019 06:21, Ramalingam C wrote:
> > If Local memory is supported by hardware, we want framebuffer backing
> > gem objects out of local memory.
> >
> > If local memory is supported and gem object if not from local memory we
> > mi
Quoting Tvrtko Ursulin (2019-09-26 09:53:03)
>
> On 26/09/2019 06:21, Ramalingam C wrote:
> > If Local memory is supported by hardware, we want framebuffer backing
> > gem objects out of local memory.
> >
> > If local memory is supported and gem object if not from local memory we
> > migrate the
Op 25-09-2019 om 23:42 schreef Matt Roper:
> On Wed, Sep 25, 2019 at 04:59:01PM +0200, Maarten Lankhorst wrote:
>> This can all be done from the intel_update_crtc function. Split out the
>> pipe update into a separate function, just like is done for the planes.
>> Pull in all the changes done durin
== Series Details ==
Series: series starting with [1/4] drm/i915: Prepare to split crtc state in
uapi and hw state
URL : https://patchwork.freedesktop.org/series/67227/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6956_full -> Patchwork_14533_full
===
This can all be done from the intel_update_crtc function. Split out the
pipe update into a separate function, just like is done for the planes.
Pull in all the changes done during fastset as well. It makes no sense
for it to still exist as a separate function.
Changes since v1:
- Inline intel_upda
On 26/09/2019 10:14, Ramalingam C wrote:
On 2019-09-26 at 09:53:03 +0100, Tvrtko Ursulin wrote:
On 26/09/2019 06:21, Ramalingam C wrote:
If Local memory is supported by hardware, we want framebuffer backing
gem objects out of local memory.
If local memory is supported and gem object if not f
Default length value of MI_LOAD_REGISTER_REG is 1.
Also move it out of cmd-parser-only registers since we're going to use
it in i915.
Signed-off-by: Michał Winiarski
Cc: Chris Wilson
Cc: Jani Nikula
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 2 +-
1 file changed, 1 insertion(+), 1 dele
Some of our commands (MI_FLUSH_DW / PIPE_CONTROL) require a post-sync write
operation to be performed. Currently we're using dedicated VMA for
PIPE_CONTROL and global HWSP for MI_FLUSH_DW.
On execlists platforms, each of our contexts has an area that can be
used as scratch space. Let's use that ins
We're currently using scratch presence as a way of identifying that we
entered wedged state at driver initialization time.
Let's use a separate flag rather than rely on scratch.
Signed-off-by: Michał Winiarski
Cc: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_reset.c |
We're currently doing one workaround where we're using scratch as a
temporary storage place, while we're overwriting the value of one
register with some known constant value in order to perform a
workaround.
While we could just do similar thing with CS_GPR register
and MI_LOAD_REGISTER_REG instead
We can use it in i915 for updating parts of unmasked registers from
within a batch. We're also adding Gen8+ versions of CS_GPR registers
(aka MI_MATH_REG in the coprocessor).
Signed-off-by: Michał Winiarski
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 24 +
== Series Details ==
Series: series starting with [1/4] drm/i915: Prepare to split crtc state in
uapi and hw state (rev2)
URL : https://patchwork.freedesktop.org/series/67227/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1368d49f2ac9 drm/i915: Prepare to split crtc state in u
We're no longer using it on execlists platforms. There's no point in
allocating it.
Signed-off-by: Michał Winiarski
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 --
drivers/gpu/drm/i915/gt/intel_gt.c| 6 ++
2 files changed, 6 insertions(+), 2 deletions(-)
diff
Quoting Michał Winiarski (2019-09-26 11:06:32)
> Default length value of MI_LOAD_REGISTER_REG is 1.
> Also move it out of cmd-parser-only registers since we're going to use
> it in i915.
Hmm. So we do find_cmd_in_table() [cmdparser] that ignores the length
field, this should not affect cmdparser.
Quoting Michał Winiarski (2019-09-26 11:06:31)
> Some of our commands (MI_FLUSH_DW / PIPE_CONTROL) require a post-sync write
> operation to be performed. Currently we're using dedicated VMA for
> PIPE_CONTROL and global HWSP for MI_FLUSH_DW.
> On execlists platforms, each of our contexts has an are
Quoting Michał Winiarski (2019-09-26 11:06:30)
> We're currently using scratch presence as a way of identifying that we
> entered wedged state at driver initialization time.
> Let's use a separate flag rather than rely on scratch.
>
> Signed-off-by: Michał Winiarski
> Cc: Chris Wilson
> Cc: Mika
Quoting Michał Winiarski (2019-09-26 11:06:34)
> We're currently doing one workaround where we're using scratch as a
> temporary storage place, while we're overwriting the value of one
> register with some known constant value in order to perform a
> workaround.
> While we could just do similar thi
== Series Details ==
Series: series starting with [1/6] drm/i915: Define explicit wedged on init
reset state
URL : https://patchwork.freedesktop.org/series/67276/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8abcbd48e83e drm/i915: Define explicit wedged on init reset state
f0
Quoting Michał Winiarski (2019-09-26 11:06:35)
> We're no longer using it on execlists platforms. There's no point in
> allocating it.
>
> Signed-off-by: Michał Winiarski
> Cc: Chris Wilson
> ---
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 --
> drivers/gpu/drm/i915/gt/intel_gt.c| 6
== Series Details ==
Series: series starting with [1/4] drm/i915: Prepare to split crtc state in
uapi and hw state (rev2)
URL : https://patchwork.freedesktop.org/series/67227/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14549
==
On 2019/9/26 下午4:21, Michael S. Tsirkin wrote:
On Thu, Sep 26, 2019 at 12:04:46PM +0800, Jason Wang wrote:
I'm not sure how stable above ops are.
It's the kernel internal API, so there's no strict requirement for this. We
will export a version value for userspace for compatibility.
Given it's
Detect the modifier corresponding to media compression to enable
display decompression for YUV and xRGB packed formats. A new modifier is
added so that the driver can distinguish between media and render
compressed buffers. Unlike render decompression, plane 6 and plane 7 do not
support media deco
== Series Details ==
Series: series starting with [1/6] drm/i915: Define explicit wedged on init
reset state
URL : https://patchwork.freedesktop.org/series/67276/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14550
===
The lockdep_assert_irqs_disabled() check is needless. The previous
lockdep_assert_held() check ensures that the lock is acquired and while
the lock is acquired lockdep also prints a warning if the interrupts are
not disabled if they have to be.
These IRQ-off asserts trigger on PREEMPT_RT because th
Two locking related changed which popped up on PREEMPT_RT.
Sebastian
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
The function intel_engine_breadcrumbs_irq() is always invoked from an interrupt
handler and for that reason it invokes (as an optimisation) only spin_lock()
for locking assuming that the interrupts are already disabled. The
function intel_engine_signal_breadcrumbs() is provided to disable
interrupt
== Series Details ==
Series: Gen12 E2E compression (rev2)
URL : https://patchwork.freedesktop.org/series/67078/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b4a0858736dc drm/framebuffer: Format modifier for Intel Gen-12 render
compression
97529f698ecd drm/i915: Use intel_tile
== Series Details ==
Series: drm/i915/tgl: Swap rps disable for rc6 disable (rev2)
URL : https://patchwork.freedesktop.org/series/67214/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6956_full -> Patchwork_14534_full
Summar
== Series Details ==
Series: Gen12 E2E compression (rev2)
URL : https://patchwork.freedesktop.org/series/67078/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14551
Summary
---
**FAILURE**
Serious
== Series Details ==
Series: drm/i915: Acquire locks with interrupts disabled
URL : https://patchwork.freedesktop.org/series/67280/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ad5e66a449c0 drm/i915: Don't disable interrupts for
intel_engine_breadcrumbs_irq()
-:7: WARNING:COM
== Series Details ==
Series: drm/i915: Acquire locks with interrupts disabled
URL : https://patchwork.freedesktop.org/series/67280/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14552
Summary
---
**
On Wed, Sep 25, 2019 at 04:45:06PM -0700, José Roberto de Souza wrote:
> From: Clinton A Taylor
>
> BSpec was updated(r146548) with a new MG_DP_MODE Programming table,
> now taking in consideration the pin assignment and allowing us to
> optimize power by shutting down available but not needed la
== Series Details ==
Series: drm/i915: Don't skip debug messages when dp link config fails
URL : https://patchwork.freedesktop.org/series/67232/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6956_full -> Patchwork_14535_full
On Thu, Sep 26, 2019 at 06:48:54PM +0800, Jason Wang wrote:
>
> On 2019/9/26 下午4:21, Michael S. Tsirkin wrote:
> > On Thu, Sep 26, 2019 at 12:04:46PM +0800, Jason Wang wrote:
> > > > > > I'm not sure how stable above ops are.
> > > > > It's the kernel internal API, so there's no strict requirement
We're no longer using it on execlists platforms. There's no point in
allocating it.
v2: Move scratch init to legacy ring submission backend. (Chris)
Signed-off-by: Michał Winiarski
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 --
drivers/gpu/drm/i915/gt/intel_gt.c
Insert structure members names into their descriptions to follow
kernel-doc format.
Cc: Chris Wilson
Signed-off-by: Anna Karas
---
drivers/gpu/drm/i915/i915_drv.h | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm
== Series Details ==
Series: series starting with [1/6] drm/i915: Define explicit wedged on init
reset state (rev2)
URL : https://patchwork.freedesktop.org/series/67276/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
5883d760ee3b drm/i915: Define explicit wedged on init reset s
On Wed, Sep 25, 2019 at 11:37:58AM -0700, Manasi Navare wrote:
> On Wed, Sep 25, 2019 at 01:08:23PM +0300, Ville Syrjälä wrote:
> > On Tue, Sep 24, 2019 at 10:59:57AM -0700, Manasi Navare wrote:
> > > On Tue, Sep 24, 2019 at 05:38:00PM +0200, Maarten Lankhorst wrote:
> > > > Op 22-09-2019 om 19:08
On Wed, Sep 25, 2019 at 01:33:52PM -0700, James Ausmus wrote:
> For Gen12, BSpec no longer tells us to disable SAGV when > 1 pipe is
> active. Update intel_can_enable_sagv to allow this, and loop through all
> active planes on all active crtcs to check against the interlaced and
> latency restricti
On Wed, Sep 25, 2019 at 02:07:27PM -0700, Stuart Summers wrote:
No commit message.
> Signed-off-by: Stuart Summers
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_pci.c | 3 ++-
> drivers/gpu/drm/i9
Replace PLLs names used in documentation to that used in the code.
Cc: Vandita Kulkarni
Fixes: commit d0570414f3d1 ("drm/i915/tgl: Add new pll ids")
Signed-off-by: Anna Karas
---
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
On Wed, Sep 25, 2019 at 02:42:12PM -0700, Matt Roper wrote:
> On Wed, Sep 25, 2019 at 04:59:01PM +0200, Maarten Lankhorst wrote:
> > This can all be done from the intel_update_crtc function. Split out the
> > pipe update into a separate function, just like is done for the planes.
> > Pull in all th
On Wed, Sep 25, 2019 at 4:52 AM Tian, Kevin wrote:
> > From: Alex Williamson
> > Sent: Wednesday, September 25, 2019 7:07 AM
> >
> > On Tue, 24 Sep 2019 21:53:29 +0800
> > Jason Wang wrote:
> >
> > > Currently, except for the create and remove, the rest of
> > > mdev_parent_ops is designed for v
On Fri, Sep 20, 2019 at 01:42:28PM +0200, Maarten Lankhorst wrote:
> Now that we can program planes from the update_slave callback, and
> we have done all fb pinning correctly, it's time to program those
> planes as well.
>
> We use the update_slave callback as it allows us to use the
> separate s
On Wed, Sep 25, 2019 at 04:45:08PM -0700, José Roberto de Souza wrote:
> Link training is failling when running link at 2.7GHz and 1.62GHz and
> following BSpec pll algorithm.
>
> Comparing the values calculated and the ones from the reference table
> it looks like MG_CLKTOP2_CORECLKCTL1_A_DIVRATI
Make it easier to discern in the noise of the module reload where each
begins.
Signed-off-by: Chris Wilson
Cc: Andi Shyti
---
tests/i915/i915_pm_rpm.c | 4
1 file changed, 4 insertions(+)
diff --git a/tests/i915/i915_pm_rpm.c b/tests/i915/i915_pm_rpm.c
index a2bdabee2..f5f813c3d 100644
--
== Series Details ==
Series: series starting with [1/6] drm/i915: Define explicit wedged on init
reset state (rev2)
URL : https://patchwork.freedesktop.org/series/67276/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14553
Hi Chris,
On Thu, Sep 26, 2019 at 02:10:06PM +0100, Chris Wilson wrote:
> Make it easier to discern in the noise of the module reload where each
> begins.
>
> Signed-off-by: Chris Wilson
> Cc: Andi Shyti
thanks for this patch!
Acked-by: Andi Shyti
Andi
> ---
> tests/i915/i915_pm_rpm.c | 4
== Series Details ==
Series: drm/i915/perf: Fix use of kernel-doc format in structure members
URL : https://patchwork.freedesktop.org/series/67282/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14554
Summa
On 26/09/2019 15:21, Anna Karas wrote:
Insert structure members names into their descriptions to follow
kernel-doc format.
Cc: Chris Wilson
Signed-off-by: Anna Karas
Still
Acked-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 14 +++---
1 file changed, 7 insertio
Quoting Michał Winiarski (2019-09-26 11:06:33)
> We can use it in i915 for updating parts of unmasked registers from
> within a batch. We're also adding Gen8+ versions of CS_GPR registers
> (aka MI_MATH_REG in the coprocessor).
>
> Signed-off-by: Michał Winiarski
> Cc: Chris Wilson
Checked agai
Quoting Michał Winiarski (2019-09-26 13:20:19)
> We're no longer using it on execlists platforms. There's no point in
> allocating it.
>
> v2: Move scratch init to legacy ring submission backend. (Chris)
>
> Signed-off-by: Michał Winiarski
> Cc: Chris Wilson
Reviewed-by: Chris Wilson
-Chris
__
From: Michał Winiarski
We're currently using scratch presence as a way of identifying that we
entered wedged state at driver initialization time.
Let's use a separate flag rather than rely on scratch.
Signed-off-by: Michał Winiarski
Cc: Chris Wilson
Cc: Mika Kuoppala
Reviewed-by: Chris Wilson
From: Michał Winiarski
Some of our commands (MI_FLUSH_DW / PIPE_CONTROL) require a post-sync write
operation to be performed. Currently we're using dedicated VMA for
PIPE_CONTROL and global HWSP for MI_FLUSH_DW.
On execlists platforms, each of our contexts has an area that can be
used as scratch
From: Michał Winiarski
Default length value of MI_LOAD_REGISTER_REG is 1.
Also move it out of cmd-parser-only registers since we're going to use
it in i915.
Signed-off-by: Michał Winiarski
Cc: Chris Wilson
Cc: Jani Nikula
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_gpu_comma
Quoting Michał Winiarski (2019-09-26 11:06:34)
> We're currently doing one workaround where we're using scratch as a
> temporary storage place, while we're overwriting the value of one
> register with some known constant value in order to perform a
> workaround.
> While we could just do similar thi
On 25/09/2019 11:01, Chris Wilson wrote:
Keep track of the GEM contexts underneath i915->gem.contexts and assign
them their own lock for the purposes of list management.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gem/i915_gem_context.c | 155 +++---
== Series Details ==
Series: drm/i915/tgl: Fix doc not corresponding to code (rev2)
URL : https://patchwork.freedesktop.org/series/67088/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14555
Summary
---
Moving our primary irq handler to a RT thread incurs an extra 1us delay
in process interrupts. This is most notice in waking up client threads,
where it adds about 20% of extra latency. It also imposes a delay in
feeding the GPU, an extra 1us before signaling secondary engines and
extra latency in
Update references to reservation.c and reservation.h since these files
have been renamed to dma-resv.c and dma-resv.h respectively.
Cc: Christian König
Link: https://patchwork.freedesktop.org/patch/323401/?series=65037&rev=1
Signed-off-by: Anna Karas
---
Documentation/driver-api/dma-buf.rst | 6
== Series Details ==
Series: drm/i915/selftests: Exercise concurrent submission to all engines
URL : https://patchwork.freedesktop.org/series/67237/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6958_full -> Patchwork_14537_full
On 26/09/2019 15:25, Chris Wilson wrote:
Moving our primary irq handler to a RT thread incurs an extra 1us delay
in process interrupts. This is most notice in waking up client threads,
where it adds about 20% of extra latency. It also imposes a delay in
feeding the GPU, an extra 1us before signa
On Thu, 2019-09-26 at 15:36 +0300, Ville Syrjälä wrote:
> On Wed, Sep 25, 2019 at 02:07:27PM -0700, Stuart Summers wrote:
>
> No commit message.
I'll add one here, should have caught this before posting, sorry.
>
> > Signed-off-by: Stuart Summers
> > ---
> > drivers/gpu/drm/i915/i915_drv.c
== Series Details ==
Series: series starting with [CI,1/3] drm/i915: Define explicit wedged on init
reset state
URL : https://patchwork.freedesktop.org/series/67289/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14556
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
DC3CO enable bit will be used by driver to make DC3CO
ready for DMC f/w and status bit will be used as DC3CO
entry status.
2. Transcoder EXITLINE register and its bit fields and mask.
Transcode
Enable dc3co state in enable_dc module param and add dc3co
enable mask to allowed_dc_mask and gen9_dc_mask.
v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6
independently. [Animesh]
v2: Using a switch statement for cleaner code. [Animesh]
Cc: Jani Nikula
Cc: Imre Deak
Cc: A
Add target_dc_state and tgl_set_target_dc_state() API
in order to enable DC3CO state with existing DC states.
target_dc_state will enable/disable the desired DC state in
DC_STATE_EN reg when "DC Off" power well gets disable/enable.
v2: commit log improvement.
v3: Used intel_wait_for_register to wa
Disallow DC3CO state before PSR2 exit.
Store dc3co_exitline from crtc state to psr dev_priv
structure to use it easily whenever it requires.
v1: Moved calling of tgl_enable_psr2_transcoder_exitline() to
intel_psr_enable(). [Imre]
v2: Moved tgl_psr2_deep_sleep_enable/disable function to
the
DC3CO is useful power state, when DMC detects PSR2 idle frame
while an active video playback, playing 30fps video on 60hz panel
is the classic example of this use case.
B.Specs:49196 has a restriction to enable DC3CO only for Video Playback.
It will be worthy to enable DC3CO after completion of ea
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
d
Resending V9 series after fixing CI warnings and CI IGT failures.
v9 revision is a rework of series, which has fixed the review comments
provided by Imre and added Animesh's RB on following two patches.
1.Add DC3CO required register and bits
2.Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
An
DC3CO enabling B.Specs sequence requires to enable end configure
exit scanlines to TRANS_EXITLINE register, programming this register
has to be part of modeset sequence as this can't be change when
transcoder or port is enabled.
When system boots with only eDP panel there may not be real
modeset as
Quoting Tvrtko Ursulin (2019-09-26 15:57:07)
>
> On 26/09/2019 15:25, Chris Wilson wrote:
> > Moving our primary irq handler to a RT thread incurs an extra 1us delay
> > in process interrupts. This is most notice in waking up client threads,
> > where it adds about 20% of extra latency. It also im
On 2019-09-26 15:25:38 [+0100], Chris Wilson wrote:
> Moving our primary irq handler to a RT thread incurs an extra 1us delay
> in process interrupts. This is most notice in waking up client threads,
> where it adds about 20% of extra latency. It also imposes a delay in
> feeding the GPU, an extra
On 2019-09-26 15:57:07 [+0100], Tvrtko Ursulin wrote:
> 2. What about our tasklets - with threaded irqs we don't need them any more,
> right? So in this case they just add additional latency.
If you enqueue / schedule tasklets from your threaded handler then this
will wake up ksoftirqd and perform
Quoting Sebastian Andrzej Siewior (2019-09-26 16:13:08)
> On 2019-09-26 15:25:38 [+0100], Chris Wilson wrote:
> > Moving our primary irq handler to a RT thread incurs an extra 1us delay
> > in process interrupts. This is most notice in waking up client threads,
> > where it adds about 20% of extra
== Series Details ==
Series: drm/i915/dmc: Update ICL DMC version to v1.09 (rev2)
URL : https://patchwork.freedesktop.org/series/66560/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6958_full -> Patchwork_14538_full
Summary
== Series Details ==
Series: drm/i915: Delegate our irq handler to a thread
URL : https://patchwork.freedesktop.org/series/67294/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14557
Summary
---
**FA
On 2019-09-26 16:24:59 [+0100], Chris Wilson wrote:
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > b/drivers/gpu/drm/i915/i915_irq.c
> > > index bc83f094065a..f3df7714a3f3 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -4491,8 +449
On Wed, Sep 25, 2019 at 04:45:07PM -0700, José Roberto de Souza wrote:
> From: Clinton A Taylor
>
> Added DKL Phy sequences and helpers functions to program voltage
> swing, clock gating and dp mode.
>
> It is not written in DP enabling sequence but "PHY Clockgating
> programming" states that cl
Moving our primary irq handler to a RT thread incurs an extra 1us delay
in process interrupts. This is most notice in waking up client threads,
where it adds about 20% of extra latency. It also imposes a delay in
feeding the GPU, an extra 1us before signaling secondary engines and
extra latency in
From: Sebastian Andrzej Siewior
The lockdep_assert_irqs_disabled() check is needless. The previous
lockdep_assert_held() check ensures that the lock is acquired and while
the lock is acquired lockdep also prints a warning if the interrupts are
not disabled if they have to be.
These IRQ-off assert
From: Sebastian Andrzej Siewior
The function intel_engine_breadcrumbs_irq() is always invoked from an interrupt
handler and for that reason it invokes (as an optimisation) only spin_lock()
for locking assuming that the interrupts are already disabled. The
function intel_engine_signal_breadcrumbs(
Quoting Sebastian Andrzej Siewior (2019-09-26 16:32:52)
> On 2019-09-26 16:24:59 [+0100], Chris Wilson wrote:
> > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > > b/drivers/gpu/drm/i915/i915_irq.c
> > > > index bc83f094065a..f3df7714a3f3 100644
> > > > --- a/drivers/gpu/drm/i915/i915_irq.c
Quoting Chris Wilson (2019-09-26 16:40:34)
> Quoting Sebastian Andrzej Siewior (2019-09-26 16:32:52)
> > On 2019-09-26 16:24:59 [+0100], Chris Wilson wrote:
> > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c
> > > > > b/drivers/gpu/drm/i915/i915_irq.c
> > > > > index bc83f094065a..f3df7714a3f3
On Wed, Sep 25, 2019 at 10:30:28AM -0600, Alex Williamson wrote:
> On Wed, 25 Sep 2019 10:11:00 -0400
> Rob Miller wrote:
> > > > On Tue, 24 Sep 2019 21:53:29 +0800
> > > > Jason Wang wrote:
> > > > > diff --git a/drivers/vfio/mdev/vfio_mdev.c
> > > > b/drivers/vfio/mdev/vfio_mdev.c
> > > > >
Op 26-09-2019 om 15:06 schreef Ville Syrjälä:
> On Fri, Sep 20, 2019 at 01:42:28PM +0200, Maarten Lankhorst wrote:
>> Now that we can program planes from the update_slave callback, and
>> we have done all fb pinning correctly, it's time to program those
>> planes as well.
>>
>> We use the update_sl
== Series Details ==
Series: drm/i915: Update references to previously renamed files
URL : https://patchwork.freedesktop.org/series/67295/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6963 -> Patchwork_14558
Summary
--
Op 26-09-2019 om 00:09 schreef Manasi Navare:
> On Tue, Sep 24, 2019 at 10:30:39PM -0700, Matt Roper wrote:
>> On Fri, Sep 20, 2019 at 01:42:22PM +0200, Maarten Lankhorst wrote:
>>> Small changes to intel_dp_mode_valid(), allow listing modes that
>>> can only be supported in the bigjoiner configura
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