== Series Details ==
Series: i915 vgpu PV to improve vgpu performance
URL : https://patchwork.freedesktop.org/series/66787/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6905 -> Patchwork_14425
Summary
---
**SUCCESS*
== Series Details ==
Series: drm/i915/cml: Add second PCH ID for CMP
URL : https://patchwork.freedesktop.org/series/66782/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6905_full -> Patchwork_14423_full
Summary
---
*
On Thu, 12 Sep 2019, Animesh Manna wrote:
> On 9/12/2019 6:37 PM, Jani Nikula wrote:
>> On Thu, 12 Sep 2019, Animesh Manna wrote:
>>> Gamma lut programming can be programmed using DSB
>>> where bulk register programming can be done using indexed
>>> register write which takes number of data and t
As we need to take a walk back along the signaler timeline to find the
fence before upon which we want to wait, we need to lock that timeline
to prevent it being modified as we walk. Similarly, we also need to
acquire a reference to the earlier fence while it still exists!
Though we lack the corre
> From: Jason Wang
> Sent: Thursday, September 12, 2019 5:40 PM
>
> Mdev bus only support vfio driver right now, so it doesn't implement
> match method. But in the future, we may add drivers other than vfio,
> one example is virtio-mdev[1] driver. This means we need to add device
> id support in b
Quoting Daniele Ceraolo Spurio (2019-09-16 22:41:04)
> Our assumption that the we can ask the HW to lock the SFC even if not
> currently in use does not match the HW commitment. The expectation from
> the HW is that SW will not try to lock the SFC if the engine is not
> using it and if we do that t
If we try to clear, or even set, a bit in the register that doesn't
change the register state; skip the write. There's a slight danger in
that the register acts as a latch-on-write, but I do not think we use a
rmw cycle with any such latch registers.
Suggested-by: Daniele Ceraolo Spurio
Signed-of
> From: Jason Wang
> Sent: Thursday, September 12, 2019 5:40 PM
>
> Currently, except for the crate and remove. The rest fields of
> mdev_parent_ops is just designed for vfio-mdev driver and may not help
> for kernel mdev driver. So follow the device id support by previous
> patch, this patch intr
== Series Details ==
Series: drm: Handle connector tile support only for modes that match tile size
URL : https://patchwork.freedesktop.org/series/66784/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6905_full -> Patchwork_14424_full
===
== Series Details ==
Series: drm/i915: Lock signaler timeline while navigating
URL : https://patchwork.freedesktop.org/series/66799/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6906 -> Patchwork_14426
Summary
---
*
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_faulting_reloc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tests/i915/gem_exec_faulting_reloc.c
b/tests/i915/gem_exec_faulting_reloc.c
index 6b05e43fe..0bb5fa91a 100644
--- a/tests/i915/gem_exec_faulting_reloc.c
+++ b/tests/i915/gem
Chris Wilson writes:
> Signed-off-by: Chris Wilson
Acked-by: Mika Kuoppala
> ---
> tests/i915/gem_exec_faulting_reloc.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/tests/i915/gem_exec_faulting_reloc.c
> b/tests/i915/gem_exec_faulting_reloc.c
> index 6b05e43fe..0bb5fa91a 10064
== Series Details ==
Series: drm/i915: Only apply a rmw mmio update if the value changes
URL : https://patchwork.freedesktop.org/series/66800/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6906 -> Patchwork_14427
Summary
--
On 9/17/2019 1:00 PM, Jani Nikula wrote:
On Thu, 12 Sep 2019, Animesh Manna wrote:
On 9/12/2019 6:37 PM, Jani Nikula wrote:
On Thu, 12 Sep 2019, Animesh Manna wrote:
Gamma lut programming can be programmed using DSB
where bulk register programming can be done using indexed
register write w
Quoting Xiaolin Zhang (2019-09-17 06:48:15)
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index e62e9d1..00b187a 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1015,7 +1015,7 @@ static u64 __gen8_p
Quoting Xiaolin Zhang (2019-09-17 06:48:14)
> based on the shared memory setup between guest and GVT, the simple
> pv command buffer ring was introduced by this patch used to perform
> guest-2-gvt single direction communication.
>
> v1: initial support, added to address i915 PV v6 patch set commen
Quoting Xiaolin Zhang (2019-09-17 06:48:16)
> It is performance optimization to override the actual submisison backend
> in order to eliminate execlists csb process and reduce mmio trap numbers
> for workload submission without context switch interrupt by talking with
> GVT via PV submisison notifi
== Series Details ==
Series: i915 vgpu PV to improve vgpu performance
URL : https://patchwork.freedesktop.org/series/66787/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6905_full -> Patchwork_14425_full
Summary
---
On 2019/9/17 下午3:55, Tian, Kevin wrote:
From: Jason Wang
Sent: Thursday, September 12, 2019 5:40 PM
Mdev bus only support vfio driver right now, so it doesn't implement
match method. But in the future, we may add drivers other than vfio,
one example is virtio-mdev[1] driver. This means we need
On 2019/9/17 下午4:09, Tian, Kevin wrote:
From: Jason Wang
Sent: Thursday, September 12, 2019 5:40 PM
Currently, except for the crate and remove. The rest fields of
mdev_parent_ops is just designed for vfio-mdev driver and may not help
for kernel mdev driver. So follow the device id support by pr
On 16/09/2019 22:41, Daniele Ceraolo Spurio wrote:
Our assumption that the we can ask the HW to lock the SFC even if not
currently in use does not match the HW commitment. The expectation from
the HW is that SW will not try to lock the SFC if the engine is not
using it and if we do that the beha
Op 16-09-2019 om 21:19 schreef Manasi Navare:
> On Fri, Sep 13, 2019 at 03:36:39PM +0200, Maarten Lankhorst wrote:
>> Hey,
>>
>> Op 29-07-2019 om 21:17 schreef Manasi Navare:
>>> Hi Ville,
>>>
>>> Thanks for your review, so do we want to merge this as is or
>>> do we need some function to reject th
Chris Wilson writes:
> On Tigerlake, MI_SEMAPHORE_WAIT grew an extra dword, so be sure to
> update the length field and emit that extra parameter and any padding
> noop as required.
>
> v2: Define the token shift while we are adding the updated MI_SEMAPHORE_WAIT
>
> Signed-off-by: Chris Wilson
>
Quoting Mika Kuoppala (2019-09-17 11:56:40)
> Chris Wilson writes:
>
> > On Tigerlake, MI_SEMAPHORE_WAIT grew an extra dword, so be sure to
> > update the length field and emit that extra parameter and any padding
> > noop as required.
> >
> > v2: Define the token shift while we are adding the up
Tigerlake does not seem to be suffering from the same fault as Icelake
did, so let the tests run as they should complete within the timeout.
Early tgl results:
basic-small-copy: SUCCESS (1,671s)
forked-basic-small-copy: SUCCESS (37,568s)
medium-copy: SUCCESS (3,307s)
forked-medium-copy: SUCCESS
On 17/09/2019 14:23, Chris Wilson wrote:
> Tigerlake does not seem to be suffering from the same fault as Icelake
> did, so let the tests run as they should complete within the timeout.
>
> Early tgl results:
>
> basic-small-copy: SUCCESS (1,671s)
> forked-basic-small-copy: SUCCESS (37,568s)
>
On 13/09/2019 19:43, Chris Wilson wrote:
> Now that we have CI testing of iommu, let's enable stolen + iommu with a
> lot more confidence that we can diagnose any potential erors.
AFAIK, we still haven't checked that these machines indeed have the
IOMMU enabled yet. Am I wrong?
If I am not, then
Quoting Martin Peres (2019-09-17 12:37:25)
>
>
> On 17/09/2019 14:23, Chris Wilson wrote:
> > Tigerlake does not seem to be suffering from the same fault as Icelake
> > did, so let the tests run as they should complete within the timeout.
> >
> > Early tgl results:
> >
> > basic-small-copy: SUC
== Series Details ==
Series: drm/i915: Lock signaler timeline while navigating
URL : https://patchwork.freedesktop.org/series/66799/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6906_full -> Patchwork_14426_full
Summary
--
Quoting Martin Peres (2019-09-17 12:39:13)
> On 13/09/2019 19:43, Chris Wilson wrote:
> > Now that we have CI testing of iommu, let's enable stolen + iommu with a
> > lot more confidence that we can diagnose any potential erors.
>
> AFAIK, we still haven't checked that these machines indeed have t
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_color.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 318308d..b1f0f7e 100644
--- a/drivers/gpu/d
For icl+, have hw read out to create hw blob of gamma
lut values. icl+ platforms supports multi segmented gamma
mode, add hw lut creation for this mode.
This will be used to validate gamma programming using dsb
(display state buffer) which is a tgl feature.
v2: -readout code for multisegmented ga
In this patch series, added state checker to validate gamma lut values
for icelake+ platforms. It's extension of the
patch series https://patchwork.freedesktop.org/patch/328246/?series=58039
which enabled the basic infrastructure and state checker for
legacy platforms.
Swati Sharma (2):
drm/i915
Chris Wilson writes:
> Tigerlake does not seem to be suffering from the same fault as Icelake
> did, so let the tests run as they should complete within the timeout.
>
> Early tgl results:
>
> basic-small-copy: SUCCESS (1,671s)
> forked-basic-small-copy: SUCCESS (37,568s)
>
> medium-copy: SUCCESS
On Thu, 12 Sep 2019 17:40:11 +0800
Jason Wang wrote:
> Mdev bus only support vfio driver right now, so it doesn't implement
> match method. But in the future, we may add drivers other than vfio,
> one example is virtio-mdev[1] driver. This means we need to add device
> id support in bus match met
commit 4f5368b5541a902f6596558b05f5c21a9770dd32
Author: Daniel Vetter
Date: Fri Jun 14 08:17:23 2019 +0200
drm/kms: Catch mode_object lifetime errors
uncovered a bit a mess in dp drivers. Most drivers (from a quick look,
all except i915) register all the dp stuff in their init code, which
Support for Clear Color is contained in the last two patches
submitted by Radhakrishna Sripada. The first 4 patches are
currently undergoing review/revision changes. The first 4 patches
are cherry-picked from the series
https://patchwork.freedesktop.org/series/65290/
Expecting feedback for the las
Render Decompression is supported with Y-Tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Additional Clear Color information is passed from the
user-space through an offset in the GEM BO. Add a new modifier to identify
and parse n
Current code is quite a mess unfortunately, so also add a todo.rst
entry to maybe fix it up eventually.
Cc: Michel Dänzer
Signed-off-by: Daniel Vetter
---
Documentation/gpu/todo.rst | 12
drivers/gpu/drm/drm_connector.c | 10 --
drivers/gpu/drm/drm_dp_helper.c | 8 +++
From: Dhinakaran Pandiyan
Gen-12 has a new compression format, add a new modifier for userspace to
indicate that.
Cc: Ville Syrjälä
Cc: Daniel Vetter
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Lucas De Marchi
---
include/uapi/drm/drm_fourcc.h | 10 ++
1 file changed, 10 inser
From: Dhinakaran Pandiyan
Gen-12 display can decompress surfaces compressed by the media engine.
Detect the modifier corresponding to media compression to enable
decompression for YUV and ARGB packed formats. A new modifier is added
so that the driver can distinguish between media and render comp
From: Dhinakaran Pandiyan
Gen-12 decompression is supported with Y-tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Gen-12 display decompression is incompatible with buffers
compressed by earlier GPUs, so make use of a new modif
Gen12 display can decompress surfaces compressed by render engine with Clear
Color, add
a new modifier as the driver needs to know the surface was compressed by render
engine.
V2: Description changes as suggested by Rafael.
Cc: Ville Syrjala
Cc: Dhinakaran Pandiyan
Cc: Kalyan Kondapally
Cc:
From: Dhinakaran Pandiyan
Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.
Cc: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Lucas De Marchi
---
in
Quoting Mika Kuoppala (2019-09-17 13:04:32)
> Chris Wilson writes:
>
> > Tigerlake does not seem to be suffering from the same fault as Icelake
> > did, so let the tests run as they should complete within the timeout.
> >
> > Early tgl results:
> >
> > basic-small-copy: SUCCESS (1,671s)
> > forke
== Series Details ==
Series: drm/i915: Only apply a rmw mmio update if the value changes
URL : https://patchwork.freedesktop.org/series/66800/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6906_full -> Patchwork_14427_full
On Tigerlake, MI_SEMAPHORE_WAIT grew an extra dword, so be sure to
update the length field and emit that extra parameter and any padding
noop as required.
v2: Define the token shift while we are adding the updated MI_SEMAPHORE_WAIT
v3: Use int instead of bool in the addition so that readers are no
On Mon, Sep 16, 2019 at 02:23:13PM +0200, Christian König wrote:
> Ping? Any further comment on this or can't we merge at least the locking
> change?
I was at plumbers ...
>
> Christian.
>
> Am 11.09.19 um 12:53 schrieb Christian König:
> > Am 03.09.19 um 10:05 schrieb Daniel Vetter:
> > > On Th
== Series Details ==
Series: i915/gem_mmap_gtt: Run forked mmap tests on tgl
URL : https://patchwork.freedesktop.org/series/66809/
State : success
== Summary ==
CI Bug Log - changes from IGT_5189 -> IGTPW_3470
Summary
---
**SUCCESS**
== Series Details ==
Series: adding gamma state checker for icl+ platforms
URL : https://patchwork.freedesktop.org/series/66811/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2da6cea43f48 drm/i915/display: Fix formatting issues
-:7: WARNING:COMMIT_MESSAGE: Missing commit descri
Am 17.09.19 um 14:31 schrieb Daniel Vetter:
> On Mon, Sep 16, 2019 at 02:23:13PM +0200, Christian König wrote:
>> Ping? Any further comment on this or can't we merge at least the locking
>> change?
> I was at plumbers ...
>> Christian.
>>
>> Am 11.09.19 um 12:53 schrieb Christian König:
>>> Am 03.0
On Thu, 12 Sep 2019 17:40:12 +0800
Jason Wang wrote:
> Currently, except for the crate and remove. The rest fields of
> mdev_parent_ops is just designed for vfio-mdev driver and may not help
> for kernel mdev driver. So follow the device id support by previous
> patch, this patch introduces devic
For icl+, have hw read out to create hw blob of gamma
lut values. icl+ platforms supports multi segmented gamma
mode, add hw lut creation for this mode.
This will be used to validate gamma programming using dsb
(display state buffer) which is a tgl feature.
v2: -readout code for multisegmented ga
In this patch series, added state checker to validate gamma lut values
for icelake+ platforms. It's extension of the
patch series https://patchwork.freedesktop.org/patch/328246/?series=58039
which enabled the basic infrastructure and state checker for
legacy platforms.
Swati Sharma (3):
drm/i915
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_color.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 318308d..b1f0f7e 100644
--- a/drivers/gpu/d
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_color.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 0008011..4bf098f 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
== Series Details ==
Series: adding gamma state checker for icl+ platforms
URL : https://patchwork.freedesktop.org/series/66811/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6908 -> Patchwork_14428
Summary
---
**FAI
Added bandwidth calculation algorithm and checks,
similar way as it was done for ICL, some constants
were corrected according to BSpec.
Signed-off-by: Stanislav Lisovskiy
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=111600
---
drivers/gpu/drm/i915/display/intel_bw.c | 108 +++
== Series Details ==
Series: series starting with [1/2] drm/kms: Duct-tape for mode object lifetime
checks
URL : https://patchwork.freedesktop.org/series/66812/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ae5a3497bdd7 drm/kms: Duct-tape for mode object lifetime checks
-:9: E
Introduce a new 2-process fork test that is bound to a single cpu to
exercise contention during pagefaults. This is a much lighter variant of
the all-cpus test intended to be viable even on the legendary frozen
lakes of molasses.
References: https://bugs.freedesktop.org/show_bug.cgi?id=110882
Sign
On Tue, Sep 17, 2019 at 12:40:51PM +, Koenig, Christian wrote:
> Am 17.09.19 um 14:31 schrieb Daniel Vetter:
> > On Mon, Sep 16, 2019 at 02:23:13PM +0200, Christian König wrote:
> >> Ping? Any further comment on this or can't we merge at least the locking
> >> change?
> > I was at plumbers ...
Chris Wilson writes:
> On Tigerlake, MI_SEMAPHORE_WAIT grew an extra dword, so be sure to
> update the length field and emit that extra parameter and any padding
> noop as required.
>
> v2: Define the token shift while we are adding the updated MI_SEMAPHORE_WAIT
> v3: Use int instead of bool in t
Am 17.09.19 um 15:13 schrieb Daniel Vetter:
> On Tue, Sep 17, 2019 at 12:40:51PM +, Koenig, Christian wrote:
>> Am 17.09.19 um 14:31 schrieb Daniel Vetter:
>>> On Mon, Sep 16, 2019 at 02:23:13PM +0200, Christian König wrote:
Ping? Any further comment on this or can't we merge at least the
== Series Details ==
Series: series starting with [1/2] drm/kms: Duct-tape for mode object lifetime
checks
URL : https://patchwork.freedesktop.org/series/66812/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6908 -> Patchwork_14429
=
Chris Wilson writes:
> Introduce a new 2-process fork test that is bound to a single cpu to
> exercise contention during pagefaults. This is a much lighter variant of
> the all-cpus test intended to be viable even on the legendary frozen
> lakes of molasses.
>
> References: https://bugs.freedeskt
Mika Kuoppala writes:
> Chris Wilson writes:
>
>> Introduce a new 2-process fork test that is bound to a single cpu to
>> exercise contention during pagefaults. This is a much lighter variant of
>> the all-cpus test intended to be viable even on the legendary frozen
>> lakes of molasses.
>>
>> R
On Tue, Sep 17, 2019 at 04:00:57PM +0300, Stanislav Lisovskiy wrote:
> Added bandwidth calculation algorithm and checks,
> similar way as it was done for ICL, some constants
> were corrected according to BSpec.
>
> Signed-off-by: Stanislav Lisovskiy
>
> Fixes: https://bugs.freedesktop.org/show_b
On Tue, Sep 17, 2019 at 01:24:10PM +, Koenig, Christian wrote:
> Am 17.09.19 um 15:13 schrieb Daniel Vetter:
> > On Tue, Sep 17, 2019 at 12:40:51PM +, Koenig, Christian wrote:
> >> Am 17.09.19 um 14:31 schrieb Daniel Vetter:
> >>> On Mon, Sep 16, 2019 at 02:23:13PM +0200, Christian König wr
Chris Wilson writes:
> If we try to clear, or even set, a bit in the register that doesn't
> change the register state; skip the write. There's a slight danger in
> that the register acts as a latch-on-write, but I do not think we use a
> rmw cycle with any such latch registers.
>
> Suggested-by:
Am 17.09.19 um 15:45 schrieb Daniel Vetter:
> On Tue, Sep 17, 2019 at 01:24:10PM +, Koenig, Christian wrote:
>> Am 17.09.19 um 15:13 schrieb Daniel Vetter:
>>> On Tue, Sep 17, 2019 at 12:40:51PM +, Koenig, Christian wrote:
Am 17.09.19 um 14:31 schrieb Daniel Vetter:
> On Mon, Sep 1
On 2019-09-17 2:09 p.m., Daniel Vetter wrote:
> commit 4f5368b5541a902f6596558b05f5c21a9770dd32
> Author: Daniel Vetter
> Date: Fri Jun 14 08:17:23 2019 +0200
>
> drm/kms: Catch mode_object lifetime errors
>
> uncovered a bit a mess in dp drivers. Most drivers (from a quick look,
> all exc
Op 09-09-2019 om 05:43 schreef Manasi Navare:
> In case of tiled displays when the two tiles are sent across two CRTCs
> over two separate DP SST connectors, we need a mechanism to synchronize
> the two CRTCs and their corresponding transcoders.
> So use the master-slave mode where there is one mas
On 17/09/2019 08:43, Chris Wilson wrote:
As we need to take a walk back along the signaler timeline to find the
fence before upon which we want to wait, we need to lock that timeline
to prevent it being modified as we walk. Similarly, we also need to
acquire a reference to the earlier fence whil
Op 09-09-2019 om 05:43 schreef Manasi Navare:
> In case of tiled displays where different tiles are displayed across
> different ports, we need to synchronize the transcoders involved.
> This patch implements the transcoder port sync feature for
> synchronizing one master transcoder with one or mor
Op 09-09-2019 om 05:43 schreef Manasi Navare:
> In case of tiled displays where different tiles are displayed across
> different ports, we need to synchronize the transcoders involved.
> This patch implements the transcoder port sync feature for
> synchronizing one master transcoder with one or mor
Op 09-09-2019 om 05:43 schreef Manasi Navare:
> After the state is committed, we readout the HW registers and compare
> the HW state with the SW state that we just committed.
> For Transcdoer port sync, we add master_transcoder and the
> salves bitmask to the crtc_state, hence we need to read those
On Tue, Sep 17, 2019 at 4:47 PM Koenig, Christian
wrote:
>
> Am 17.09.19 um 15:45 schrieb Daniel Vetter:
> > On Tue, Sep 17, 2019 at 01:24:10PM +, Koenig, Christian wrote:
> >> Am 17.09.19 um 15:13 schrieb Daniel Vetter:
> >>> On Tue, Sep 17, 2019 at 12:40:51PM +, Koenig, Christian wrote:
On 16/09/2019 12:38, Chris Wilson wrote:
When using virtual engines, the rq->engine is not stable until we hold
the engine->active.lock (as the virtual engine may be exchanged with the
sibling). Since commit 22b7a426bbe1 ("drm/i915/execlists: Preempt-to-busy")
we may retire a request concurrentl
Op 09-09-2019 om 17:52 schreef Manasi Navare:
> As per the display enable sequence, we need to follow the enable sequence
> for slaves first with DP_TP_CTL set to Idle and configure the transcoder
> port sync register to select the corersponding master, then follow the
> enable sequence for master
Quoting Tvrtko Ursulin (2019-09-17 15:51:45)
>
> On 17/09/2019 08:43, Chris Wilson wrote:
> > As we need to take a walk back along the signaler timeline to find the
> > fence before upon which we want to wait, we need to lock that timeline
> > to prevent it being modified as we walk. Similarly, we
Op 09-09-2019 om 05:43 schreef Manasi Navare:
> This clears the transcoder port sync bits of the TRANS_DDI_FUNC_CTL2
> register during crtc_disable().
>
> Cc: Ville Syrjälä
> Cc: Maarten Lankhorst
> Cc: Matt Roper
> Cc: Jani Nikula
> Signed-off-by: Manasi Navare
> ---
> drivers/gpu/drm/i915/d
== Series Details ==
Series: Clear Color Support for TGL Render Decompression
URL : https://patchwork.freedesktop.org/series/66814/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1b45d10a93b6 drm/framebuffer/tgl: Format modifier for Intel Gen-12 render
compression
8c34c16a8118
Op 09-09-2019 om 17:52 schreef Manasi Navare:
> In the transcoder port sync mode, the slave transcoders mask their vblanks
> until master transcoder's vblank so while disabling them, make
> sure slaves are disabled first and then the masters.
>
> v4:
> * Obtain slave state from master (Maarten)
> v
As we need to take a walk back along the signaler timeline to find the
fence before upon which we want to wait, we need to lock that timeline
to prevent it being modified as we walk. Similarly, we also need to
acquire a reference to the earlier fence while it still exists!
Though we lack the corre
Quoting Tvrtko Ursulin (2019-09-17 15:59:25)
>
> On 16/09/2019 12:38, Chris Wilson wrote:
> > When using virtual engines, the rq->engine is not stable until we hold
> > the engine->active.lock (as the virtual engine may be exchanged with the
> > sibling). Since commit 22b7a426bbe1 ("drm/i915/execl
On 17/09/2019 16:09, Chris Wilson wrote:
As we need to take a walk back along the signaler timeline to find the
fence before upon which we want to wait, we need to lock that timeline
to prevent it being modified as we walk. Similarly, we also need to
acquire a reference to the earlier fence whil
On 17/09/2019 16:04, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-09-17 15:51:45)
On 17/09/2019 08:43, Chris Wilson wrote:
As we need to take a walk back along the signaler timeline to find the
fence before upon which we want to wait, we need to lock that timeline
to prevent it being modi
== Series Details ==
Series: Clear Color Support for TGL Render Decompression
URL : https://patchwork.freedesktop.org/series/66814/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6909 -> Patchwork_14430
Summary
---
**
== Series Details ==
Series: drm/i915/tgl: Extend MI_SEMAPHORE_WAIT (rev3)
URL : https://patchwork.freedesktop.org/series/66625/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
99968bd8d581 drm/i915/tgl: Extend MI_SEMAPHORE_WAIT
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrap
As we need to take a walk back along the signaler timeline to find the
fence before upon which we want to wait, we need to lock that timeline
to prevent it being modified as we walk. Similarly, we also need to
acquire a reference to the earlier fence while it still exists!
Though we lack the corre
== Series Details ==
Series: drm/i915/tgl: Extend MI_SEMAPHORE_WAIT (rev3)
URL : https://patchwork.freedesktop.org/series/66625/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6909 -> Patchwork_14431
Summary
---
**SUC
== Series Details ==
Series: adding gamma state checker for icl+ platforms (rev2)
URL : https://patchwork.freedesktop.org/series/66811/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
58295b9b8527 drm/i915/display: Fix formatting issues
-:7: WARNING:COMMIT_MESSAGE: Missing commit
Quoting Daniele Ceraolo Spurio (2019-09-16 22:41:04)
> @@ -401,7 +407,10 @@ static void gen11_unlock_sfc(struct intel_engine_cs
> *engine)
> return;
> }
>
> - rmw_clear_fw(uncore, sfc_forced_lock, sfc_forced_lock_bit);
> + lock = intel_uncore_read_fw(uncore, s
== Series Details ==
Series: adding gamma state checker for icl+ platforms (rev2)
URL : https://patchwork.freedesktop.org/series/66811/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6909 -> Patchwork_14432
Summary
---
On Tue, Sep 17, 2019 at 05:04:28PM +0200, Maarten Lankhorst wrote:
> Op 09-09-2019 om 05:43 schreef Manasi Navare:
> > This clears the transcoder port sync bits of the TRANS_DDI_FUNC_CTL2
> > register during crtc_disable().
> >
> > Cc: Ville Syrjälä
> > Cc: Maarten Lankhorst
> > Cc: Matt Roper
>
== Series Details ==
Series: drm/i915: Add TigerLake bandwidth checking
URL : https://patchwork.freedesktop.org/series/66817/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b3e5a03f489c drm/i915: Add TigerLake bandwidth checking
-:39: CHECK:LINE_SPACING: Please don't use multipl
On Tue, Sep 17, 2019 at 04:52:54PM +0200, Maarten Lankhorst wrote:
> Op 09-09-2019 om 05:43 schreef Manasi Navare:
> > In case of tiled displays where different tiles are displayed across
> > different ports, we need to synchronize the transcoders involved.
> > This patch implements the transcoder
== Series Details ==
Series: drm/i915: Add TigerLake bandwidth checking
URL : https://patchwork.freedesktop.org/series/66817/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6910 -> Patchwork_14433
Summary
---
**SUCCES
[cc +Parav]
On Thu, 12 Sep 2019 17:40:10 +0800
Jason Wang wrote:
> Hi all:
>
> During the development of virtio-mdev[1]. I find that mdev needs to be
> extended to support devices other than vfio mdev device. So this
> series tries to extend the mdev to be able to differ from different
> device
On Mon, Sep 16, 2019 at 09:11:58PM -0700, Ashutosh Dixit wrote:
On Mon, 16 Sep 2019 12:17:54 -0700, Umesh Nerlige Ramappa wrote:
On Sun, Sep 15, 2019 at 02:24:41PM +0300, Lionel Landwerlin wrote:
> On 14/09/2019 02:06, Umesh Nerlige Ramappa wrote:
>> OA perf unit supports non-power of 2 report
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