On 10/09/2019 16:17, Patchwork wrote:
== Series Details ==
Series: Few loose end intel_gt cleanups
URL : https://patchwork.freedesktop.org/series/66490/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6861 -> Patchwork_14342
===
Quoting Kenneth Graunke (2019-09-10 23:42:26)
> This allows userspace to use "legacy" mode for push constants, where
> they are committed at 3DPRIMITIVE or flush time, rather than being
> committed at 3DSTATE_BINDING_TABLE_POINTERS_XS time. Gen6-8 and Gen11
> both use the "legacy" behavior - only
Quoting Kenneth Graunke (2019-09-11 02:48:01)
> This allows userspace to use "legacy" mode for push constants, where
> they are committed at 3DPRIMITIVE or flush time, rather than being
> committed at 3DSTATE_BINDING_TABLE_POINTERS_XS time. Gen6-8 and Gen11
> both use the "legacy" behavior - only
Commit 736da8112fee ("drm/i915: Use literal representation of cdclk
tables") pushed the cdclk logic into tables, adding glk_cdclk_table but
not using yet:
drivers/gpu/drm/i915/display/intel_cdclk.c:1173:38: error: ‘glk_cdclk_table’
defined but not used [-Werror=unused-const-variable=]
Fixes: 736
Quoting Chris Wilson (2019-09-11 08:42:22)
> Quoting Kenneth Graunke (2019-09-11 02:48:01)
> > This allows userspace to use "legacy" mode for push constants, where
> > they are committed at 3DPRIMITIVE or flush time, rather than being
> > committed at 3DSTATE_BINDING_TABLE_POINTERS_XS time. Gen6-8
On Mon, Sep 09, 2019 at 09:49:17PM +0530, Anshuman Gupta wrote:
> On 2019-09-08 at 19:44:35 +0300, Imre Deak wrote:
> > On Sat, Sep 07, 2019 at 10:44:39PM +0530, Anshuman Gupta wrote:
> Hi Imre,
> Thanks for reviewing the pacthes i will rework the patches.
> There are few comments from my side whic
== Series Details ==
Series: drm/i915: Whitelist COMMON_SLICE_CHICKEN2 (rev2)
URL : https://patchwork.freedesktop.org/series/66503/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6863_full -> Patchwork_14352_full
Summary
---
On Tue, Sep 10, 2019 at 03:26:20PM +0530, Anshuman Gupta wrote:
> On 2019-09-08 at 20:55:17 +0300, Imre Deak wrote:
> Hi Imre ,
> Thanks for review, could you please provide your response on below
> comments.
> > On Sat, Sep 07, 2019 at 10:44:42PM +0530, Anshuman Gupta wrote:
> > > DC3CO is useful
In preparation for reducing struct_mutex stranglehold around the vm,
make the vma.flags atomic so that we can acquire a pin on the vma
atomically before deciding if we need to take the mutex.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_object.c |
== Series Details ==
Series: drm/i915/display: Put glk_cdclk_table
URL : https://patchwork.freedesktop.org/series/66516/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6868 -> Patchwork_14353
Summary
---
**SUCCESS**
On Tue, 10 Sep 2019, Manasi Navare wrote:
> On Tue, Sep 10, 2019 at 11:07:30AM -0700, Manasi Navare wrote:
>> On Tue, Sep 10, 2019 at 12:29:19PM +0300, Jani Nikula wrote:
>> > On Sun, 08 Sep 2019, Manasi Navare wrote:
>> > > This patch series addresses all review comments and now the enable and
>
On 9/7/2019 10:44 PM, Anshuman Gupta wrote:
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers
Hi,
On 9/7/2019 10:44 PM, Anshuman Gupta wrote:
Enable dc3co state in enable_dc module param and add dc3co
enable mask to allowed_dc_mask and gen9_dc_mask.
v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6
independently.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Abstract away direct access to ->num_pipes to allow further
refactoring. No functional changes.
Cc: Chris Wilson
Cc: José Roberto de Souza
Cc: Ville Syrjälä
Reviewed-by: José Roberto de Souza
Acked-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c
Op 08-07-2019 om 14:53 schreef Ville Syrjala:
> From: Ville Syrjälä
>
> Bspec says that glk+ max downscale factor is <3.0 for all pixel formats.
> Older platforms had a max of <2.0 for NV12. Update the code to deal with
> this.
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm/i915/displa
Quoting Ville Syrjälä (2019-09-10 09:58:38)
> On Tue, Sep 10, 2019 at 09:32:45AM +0100, Chris Wilson wrote:
> > Quoting Ville Syrjälä (2019-09-10 08:39:31)
> > > On Mon, Sep 09, 2019 at 11:55:35PM +0100, Chris Wilson wrote:
> > > > If the display is inactive, we need not worry about the gpu reset
>
On 2019-09-11 at 11:50:26 +0300, Imre Deak wrote:
> On Tue, Sep 10, 2019 at 03:26:20PM +0530, Anshuman Gupta wrote:
> > On 2019-09-08 at 20:55:17 +0300, Imre Deak wrote:
> > Hi Imre ,
> > Thanks for review, could you please provide your response on below
> > comments.
> > > On Sat, Sep 07, 2019 at
When using a spinner to trigger a hang, make it unpreemptable so that it
appears like a true hang.
References: https://bugs.freedesktop.org/show_bug.cgi?id=109661
Signed-off-by: Chris Wilson
---
tests/i915/gem_eio.c| 4 +++-
tests/i915/gem_exec_fence.c | 3 ++-
tests/kms_busy.c
Use an explicit fence to circumvent the [i915] GPU hang detection rather
than tweak the i915 specific modparam (and remove the assertion that
such a param exists). Note, that with a bit more work, the fence could
be used be directly rather than via dirtying the fb with a dummyload.
Signed-off-by:
On older platforms, performing a GPU reset clobbers the display.
Exercise the interactions between reset/wedge and the display and
hopefully prevent any races creeping in.
Signed-off-by: Chris Wilson
Cc: Ville Syrjälä
---
tests/i915/gem_eio.c | 79
1
If the display is inactive, we need not worry about the gpu reset
clobbering the display! To prevent the display changing state between us
checking the active state and doing the hard reset, we introduce the
lightweight reset lock to the atomic commit for the affected (legacy)
platforms.
Testcase:
== Series Details ==
Series: drm/i915: Make i915_vma.flags atomic_t for mutex reduction
URL : https://patchwork.freedesktop.org/series/66518/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6868 -> Patchwork_14354
Summary
---
== Series Details ==
Series: drm/i915: add INTEL_NUM_PIPES() and use it
URL : https://patchwork.freedesktop.org/series/66520/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6868 -> Patchwork_14355
Summary
---
**SUCCES
On Tue, Sep 10, 2019 at 09:15:06AM -0700, Matt Roper wrote:
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h
> b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index 4d6f7f5f8930..1afa84ab6018 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/int
On Wed, Sep 11, 2019 at 08:47:27AM +0100, Chris Wilson wrote:
> Commit 736da8112fee ("drm/i915: Use literal representation of cdclk
> tables") pushed the cdclk logic into tables, adding glk_cdclk_table but
> not using yet:
>
> drivers/gpu/drm/i915/display/intel_cdclk.c:1173:38: error: ‘glk_cdclk_t
On Wed, Sep 11, 2019 at 11:53:54AM +0200, Maarten Lankhorst wrote:
> Op 08-07-2019 om 14:53 schreef Ville Syrjala:
> > From: Ville Syrjälä
> >
> > Bspec says that glk+ max downscale factor is <3.0 for all pixel formats.
> > Older platforms had a max of <2.0 for NV12. Update the code to deal with
>
While srcu may use an integer tag, it does not exclude potential error
codes and so may overlap with our own use of -EINTR. Use a separate
outparam to store the tag, and report the error code separately. While
changing the function signature allow the caller to choose whether or not
the potential w
On Mon, Sep 09, 2019 at 12:00:10PM +0100, Chris Wilson wrote:
> drivers/iommu/intel-iommu.c | 44 +
> 1 file changed, 35 insertions(+), 9 deletions(-)
Applied, thanks.
___
Intel-gfx mailing list
Intel-gfx@lists.freede
Quoting Chris Wilson (2019-09-11 11:19:59)
> If the display is inactive, we need not worry about the gpu reset
> clobbering the display! To prevent the display changing state between us
> checking the active state and doing the hard reset, we introduce the
> lightweight reset lock to the atomic com
On Wed, Sep 11, 2019 at 11:19:59AM +0100, Chris Wilson wrote:
> If the display is inactive, we need not worry about the gpu reset
> clobbering the display! To prevent the display changing state between us
> checking the active state and doing the hard reset, we introduce the
> lightweight reset loc
== Series Details ==
Series: series starting with [v2] drm/i915/gt: Allow clobbering gpu resets if
the display is off (rev2)
URL : https://patchwork.freedesktop.org/series/66459/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1b207a558e6e drm/i915/gt: Allow clobbering gpu reset
Quoting Ville Syrjälä (2019-09-11 11:52:29)
> On Wed, Sep 11, 2019 at 11:19:59AM +0100, Chris Wilson wrote:
> > If the display is inactive, we need not worry about the gpu reset
> > clobbering the display! To prevent the display changing state between us
> > checking the active state and doing the
From: Colin Ian King
There is a spelling mistake in a gvt_dbg_core debug message. Fix it.
Signed-off-by: Colin Ian King
---
drivers/gpu/drm/i915/gvt/vgpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c
inde
== Series Details ==
Series: drm/i915: Don't mix srcu tag and negative error codes
URL : https://patchwork.freedesktop.org/series/66524/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Don't mix srcu tag and negative error codes
+drivers/gpu/d
On 09/09/2019 14:52, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-26 14:38:40)
On 17/07/2019 21:09, Tvrtko Ursulin wrote:
On 17/07/2019 15:06, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-07-17 14:46:15)
On 17/07/2019 14:35, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-0
== Series Details ==
Series: series starting with [v2] drm/i915/gt: Allow clobbering gpu resets if
the display is off (rev2)
URL : https://patchwork.freedesktop.org/series/66459/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6868 -> Patchwork_14356
===
Quoting Tvrtko Ursulin (2019-09-11 12:31:32)
>
> On 09/09/2019 14:52, Chris Wilson wrote:
> > Quoting Lionel Landwerlin (2019-07-26 14:38:40)
> >> On 17/07/2019 21:09, Tvrtko Ursulin wrote:
> >>>
> >>> On 17/07/2019 15:06, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-07-17 14:46:15)
> >
== Series Details ==
Series: drm/i915: Don't mix srcu tag and negative error codes
URL : https://patchwork.freedesktop.org/series/66524/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6868 -> Patchwork_14357
Summary
---
There's no easy way of checking whether iommu is enabled for the GPU
(you can grep dmesg if you know the device, or you can grep
i915_gpu_info if that's available). We do have a central
i915_capabilities with the intent of listing such pertinent information,
so add the iommu status.
Suggested-by:
On 11/09/2019 12:38, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-09-11 12:31:32)
On 09/09/2019 14:52, Chris Wilson wrote:
Quoting Lionel Landwerlin (2019-07-26 14:38:40)
On 17/07/2019 21:09, Tvrtko Ursulin wrote:
On 17/07/2019 15:06, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-0
Quoting Balestrieri, Francesco (2019-09-11 13:03:25)
> On 04/09/2019, 13.33, "Intel-gfx on behalf of Daniel Vetter"
> wrote:
>
> On Mon, Aug 26, 2019 at 2:21 PM Abdiel Janulgue
> > - ret = create_mmap_offset(obj);
> > - if (ret == 0)
> > - *offset = drm
On 11/09/2019 14:46, Chris Wilson wrote:
> There's no easy way of checking whether iommu is enabled for the GPU
> (you can grep dmesg if you know the device, or you can grep
> i915_gpu_info if that's available). We do have a central
> i915_capabilities with the intent of listing such pertinent in
Quoting Martin Peres (2019-09-11 13:19:06)
>
>
> On 11/09/2019 14:46, Chris Wilson wrote:
> > There's no easy way of checking whether iommu is enabled for the GPU
> > (you can grep dmesg if you know the device, or you can grep
> > i915_gpu_info if that's available). We do have a central
> > i915_
== Series Details ==
Series: drm/i915/gvt: fix spelling mistake "resseting" -> "resetting"
URL : https://patchwork.freedesktop.org/series/66529/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6868 -> Patchwork_14358
Summary
== Series Details ==
Series: drm/i915: Squeeze iommu status into debugfs/i915_capabilities
URL : https://patchwork.freedesktop.org/series/66530/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6868 -> Patchwork_14359
Summary
On 2019-09-11 at 11:21:42 +0300, Imre Deak wrote:
> On Mon, Sep 09, 2019 at 09:49:17PM +0530, Anshuman Gupta wrote:
> > On 2019-09-08 at 19:44:35 +0300, Imre Deak wrote:
> > > On Sat, Sep 07, 2019 at 10:44:39PM +0530, Anshuman Gupta wrote:
> > Hi Imre,
> > Thanks for reviewing the pacthes i will re
Quoting Ville Syrjälä (2019-09-11 11:36:53)
> On Wed, Sep 11, 2019 at 08:47:27AM +0100, Chris Wilson wrote:
> > Commit 736da8112fee ("drm/i915: Use literal representation of cdclk
> > tables") pushed the cdclk logic into tables, adding glk_cdclk_table but
> > not using yet:
> >
> > drivers/gpu/drm
The same read-only affliction as befell Icelake is affecting Tigerlake.
Disable the read-only support as cleary it was not fixed.
Testcase: igt/i915_selftests/live_gem_context
References: 3936867dbc1e ("drm/i915: Disable read only ppgtt support for gen11")
Signed-off-by: Chris Wilson
Cc: Mika Kuo
Chris Wilson writes:
> The same read-only affliction as befell Icelake is affecting Tigerlake.
> Disable the read-only support as cleary it was not fixed.
>
> Testcase: igt/i915_selftests/live_gem_context
> References: 3936867dbc1e ("drm/i915: Disable read only ppgtt support for
> gen11")
> Sign
On Mon, 09 Sep 2019, nnet wrote:
> Searching on the kernel warnings and errors didn't bring it up, but in
> browsing bugzilla I stumbled on this.
>
> Bug 111501 - [CFL] Kernel 5.3.0-rc6: i915 fails at typec_displayport
> 5120x1440
> https://bugs.freedesktop.org/show_bug.cgi?id=111501
>
> It's t
On Tue, Sep 10, 2019 at 07:56:51AM -0700, James Ausmus wrote:
> The returned memory value does not align with BSpec - update to correct
> this.
Hrm. The values came directly from "IceLake PCODE/Punit Mailboxes MAS"
.doc. The question is which documentation is more correct?
>
> BSpec: 54023
>
>
From: Ville Syrjälä
The cnl and icl .modeset_calc_cdclk() functions are identical. Drop one
copy.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 37 ++
1 file changed, 2 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/display
From: Ville Syrjälä
Reuse the same .modeset_calc_cdclk() function for all bxt+.
The only difference in between the cnl/icl and the bxt variants
is the call to cnl_compute_min_voltage_level(). We can do that call
just fine on older platforms since they leave min_voltage_level[]
zeroed. Let's rena
From: Ville Syrjälä
We're forgetting to mask off all three pipe select bits from the
CDCLK_CTL value on icl+ which may lead to the extra bit being
left in. That will cause us to consider the current hardware
cdclk state as invalid, and we proceed to sanitize it even
though the hardware may have a
From: Ville Syrjälä
On tgl/bxt/glk the cdclk bypass frequency depends on the PLL
reference clock. So let's read out the ref clock before we
try to compute the bypass clock.
Cc: Matt Roper
Fixes: 71dc367e2bc3 ("drm/i915: Consolidate bxt/cnl/icl cdclk readout")
Signed-off-by: Ville Syrjälä
---
Our "whisper" consists of writing the secret value given to us by our
predecessors into the next batch, i.e. we are modifying on the GPU the
chain of inflight batches. As the preparser on gen12 will read the batch
instructions ahead of time, we need to disable it around the
self-modifications.
Sig
== Series Details ==
Series: drm/i915/tgl: Disable read-only support
URL : https://patchwork.freedesktop.org/series/66535/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8f09708f48ff drm/i915/tgl: Disable read-only support
-:10: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped c
From: Ville Syrjälä
We need to select IOMMU_SUPPORT as well, otherwise we can be left
with:
CONFIG_IOMMU_IOVA=m
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_INTEL_IOMMU=y
which complains:
"WARNING: unmet direct dependencies detected for INTEL_IOMMU"
and fails to link:
ld: drivers/iommu/intel-iom
Quoting Ville Syrjala (2019-09-11 14:50:00)
> From: Ville Syrjälä
>
> We need to select IOMMU_SUPPORT as well, otherwise we can be left
> with:
> CONFIG_IOMMU_IOVA=m
> # CONFIG_IOMMU_SUPPORT is not set
> CONFIG_INTEL_IOMMU=y
>
> which complains:
> "WARNING: unmet direct dependencies detected
On Wed, Sep 11, 2019 at 02:59:29PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2019-09-11 14:50:00)
> > From: Ville Syrjälä
> >
> > We need to select IOMMU_SUPPORT as well, otherwise we can be left
> > with:
> > CONFIG_IOMMU_IOVA=m
> > # CONFIG_IOMMU_SUPPORT is not set
> > CONFIG_INTEL
Quoting Ville Syrjälä (2019-09-11 15:08:24)
> > Already in the updated
> > 41dfd5f67ae4 ("drm/i915: Force compilation with intel-iommu for CI
> > validation")
>
> That's not upstream though. So my build is still broken.
It should be there. I checked in drm-tip. Could you double check if I've
som
== Series Details ==
Series: drm/i915/tgl: Disable read-only support
URL : https://patchwork.freedesktop.org/series/66535/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6870 -> Patchwork_14360
Summary
---
**SUCCESS**
On Wed, Sep 11, 2019 at 05:08:24PM +0300, Ville Syrjälä wrote:
> On Wed, Sep 11, 2019 at 02:59:29PM +0100, Chris Wilson wrote:
> > Quoting Ville Syrjala (2019-09-11 14:50:00)
> > > From: Ville Syrjälä
> > >
> > > We need to select IOMMU_SUPPORT as well, otherwise we can be left
> > > with:
> > >
== Series Details ==
Series: drm/i915/display: Put glk_cdclk_table
URL : https://patchwork.freedesktop.org/series/66516/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6868_full -> Patchwork_14353_full
Summary
---
**S
Am 03.09.19 um 10:05 schrieb Daniel Vetter:
On Thu, Aug 29, 2019 at 04:29:14PM +0200, Christian König wrote:
This patch is a stripped down version of the locking changes
necessary to support dynamic DMA-buf handling.
For compatibility we cache the DMA-buf mapping as soon as
exporter/importer di
Can anyone tell me how to disable power management in the i915 drivers?
It appears enable_rc6 has been disabled?
-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
Eskimo North Linux Friendly Internet Access, Shell Accounts, and Hosting.
Knowledgeable human
On Wed, Sep 11, 2019 at 04:31:26PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> On tgl/bxt/glk the cdclk bypass frequency depends on the PLL
> reference clock. So let's read out the ref clock before we
> try to compute the bypass clock.
>
> Cc: Matt Roper
> Fixes: 71dc367e2bc3 ("drm/i9
On Wed, 11 Sep 2019, Robert Dinse wrote:
> Can anyone tell me how to disable power management in the i915
> drivers? It appears enable_rc6 has been disabled?
Why do you think you need it? See [1]. If you have issues, please file
bugs at [2].
BR,
Jani.
[1] https://en.wikipedia.org/wiki/XY_prob
On Wed, Sep 11, 2019 at 04:31:27PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We're forgetting to mask off all three pipe select bits from the
> CDCLK_CTL value on icl+ which may lead to the extra bit being
> left in. That will cause us to consider the current hardware
> cdclk state as
On Wed, Sep 11, 2019 at 04:31:28PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The cnl and icl .modeset_calc_cdclk() functions are identical. Drop one
> copy.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 37 ++---
Hi Dave & Daniel -
A couple more fixes for v5.3, both cc: stable.
drm-intel-fixes-2019-09-11:
Final drm/i915 fixes for v5.3:
- Fox DP MST high color depth regression
- Fix GPU hangs on Vulkan compute workloads
BR,
Jani.
The following changes since commit f74c2bb98776e2de508f4d607cd51987306511
Quoting Matt Roper (2019-09-11 16:00:44)
> I'm confused why pre-merge CI flagged the results as a success if TGL
> was hitting this?
We've only just (Fri) got CI's Tigerlake surviving boot, so a second
failure during boot would have been missed. For the summary report,
Tigerlake is currently suppr
On Wed, 11 Sep 2019, Matt Roper wrote:
> I'm confused why pre-merge CI flagged the results as a success if TGL
> was hitting this?
I didn't check the specifics, but the full set of IGT tests is only run
on a limited number of platforms, and TGL is not yet one of them. You
get the narrow range of
Quoting Mika Kuoppala (2019-09-11 14:08:10)
> Chris Wilson writes:
>
> > The same read-only affliction as befell Icelake is affecting Tigerlake.
> > Disable the read-only support as cleary it was not fixed.
> >
> > Testcase: igt/i915_selftests/live_gem_context
> > References: 3936867dbc1e ("drm/i
On Wed, Sep 11, 2019 at 04:31:29PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Reuse the same .modeset_calc_cdclk() function for all bxt+.
>
> The only difference in between the cnl/icl and the bxt variants
> is the call to cnl_compute_min_voltage_level(). We can do that call
> just fi
== Series Details ==
Series: drm/i915: Make i915_vma.flags atomic_t for mutex reduction
URL : https://patchwork.freedesktop.org/series/66518/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6868_full -> Patchwork_14354_full
S
On Wednesday, September 11, 2019 1:00:51 AM PDT Chris Wilson wrote:
> Quoting Chris Wilson (2019-09-11 08:42:22)
> > Quoting Kenneth Graunke (2019-09-11 02:48:01)
> > > This allows userspace to use "legacy" mode for push constants, where
> > > they are committed at 3DPRIMITIVE or flush time, rather
== Series Details ==
Series: series starting with [1/4] drm/i915: Fix cdclk bypass freq readout for
tgl/bxt/glk
URL : https://patchwork.freedesktop.org/series/66537/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6871 -> Patchwork_14361
== Series Details ==
Series: drm/i915: Fix DRM_I915_DEBUG IOMMU stuff
URL : https://patchwork.freedesktop.org/series/66539/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
59352cdaf9bc drm/i915: Fix DRM_I915_DEBUG IOMMU stuff
-:20: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped
From: Tvrtko Ursulin
Since d0aa694b9239 ("drm/i915/pmu: Always sample an active ringbuffer")
the cost of sampling the engine state on execlists platforms became a
little bit higher when both engine busyness and one of the wait states are
being monitored. (Previously the busyness sampling on legac
== Series Details ==
Series: drm/i915: add INTEL_NUM_PIPES() and use it
URL : https://patchwork.freedesktop.org/series/66520/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6868_full -> Patchwork_14355_full
Summary
---
Quoting Tvrtko Ursulin (2019-09-11 17:07:30)
> From: Tvrtko Ursulin
>
> Since d0aa694b9239 ("drm/i915/pmu: Always sample an active ringbuffer")
> the cost of sampling the engine state on execlists platforms became a
> little bit higher when both engine busyness and one of the wait states are
> be
== Series Details ==
Series: drm/i915: Fix DRM_I915_DEBUG IOMMU stuff
URL : https://patchwork.freedesktop.org/series/66539/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6872 -> Patchwork_14362
Summary
---
**SUCCESS*
On Wed, Sep 11, 2019 at 12:08:00PM +0300, Jani Nikula wrote:
> On Tue, 10 Sep 2019, Manasi Navare wrote:
> > On Tue, Sep 10, 2019 at 11:07:30AM -0700, Manasi Navare wrote:
> >> On Tue, Sep 10, 2019 at 12:29:19PM +0300, Jani Nikula wrote:
> >> > On Sun, 08 Sep 2019, Manasi Navare wrote:
> >> > > T
== Series Details ==
Series: drm/i915/pmu: Skip busyness sampling when and where not needed
URL : https://patchwork.freedesktop.org/series/66541/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
48733870bba8 drm/i915/pmu: Skip busyness sampling when and where not needed
-:7: ERROR
== Series Details ==
Series: drm/i915/pmu: Skip busyness sampling when and where not needed
URL : https://patchwork.freedesktop.org/series/66541/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6872 -> Patchwork_14363
Summary
As we track when we put the GT device to sleep upon idling, we can use
that callback to sample the current rc6 counters and record the
timestamp for estimating samples after that point while asleep.
v2: Stick to using ktime_t
v3: Track user_wakerefs that interfere with the new
intel_gt_pm_wait_for
As we remove the struct_mutex protection from around the vma pinning,
counters need to be atomic and aware that there may be multiple threads
simultaneously active.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 39 -
This 3 non-atomic drivers all have the same function getting the
only encoder available in the connector, also atomic drivers have
this fallback. So moving it a common place and sharing between atomic
and non-atomic drivers.
While at it I also removed the mention of
drm_atomic_helper_best_encoder(
== Series Details ==
Series: drm/i915: Don't mix srcu tag and negative error codes
URL : https://patchwork.freedesktop.org/series/66524/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6868_full -> Patchwork_14357_full
Summar
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Shashank Sharma
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 9 +
drivers/gp
Batch buffer will be created through dsb-reg-write function which can have
single/multiple request based on usecase and once the buffer is ready
commit function will trigger the execution of the batch buffer. All
the registers will be updated simultaneously.
v1: Initial version.
v2: Optimized code
Gamma lut programming can be programmed using DSB
where bulk register programming can be done using indexed
register write which takes number of data and the mmio offset
to be written.
Currently enabled for 12-bit gamma LUT which is enabled by
default and later 8-bit/10-bit will be enabled in futu
From: Dhinakaran Pandiyan
Currently we restrict the number of encoders that can be linked to
a connector to 3, increase it to match the maximum number of encoders
that can be initialized(32).
To more effiently do that lets switch from an array of encoder ids to
bitmask.
v2: Fixing missed return
The FBC requires a couple of contiguous buffers, which we allocate from
stolen memory. If stolen memory is unavailable, we cannot allocate those
buffers and so cannot support FBC. Mark it so.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/display/intel_fbc.c | 3 +++
1 file changed, 3 inse
HI,
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Matt
> Roper
> Sent: keskiviikko 11. syyskuuta 2019 18.01
> To: Ville Syrjala
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 2/4] drm/i915: Fix CD2X pipe s
On Wed, Sep 11, 2019 at 08:01:55PM +, Souza, Jose wrote:
> On Wed, 2019-09-11 at 21:10 +0300, Ville Syrjälä wrote:
> > On Wed, Sep 11, 2019 at 10:56:02AM -0700, José Roberto de Souza
> > wrote:
> > > This 3 non-atomic drivers all have the same function getting the
> > > only encoder available i
HI,
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Chris
> Wilson
> Sent: keskiviikko 11. syyskuuta 2019 18.09
> To: Roper, Matthew D ; Ville Syrjala
>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 2/4] dr
On Wed, Sep 11, 2019 at 10:56:02AM -0700, José Roberto de Souza wrote:
> This 3 non-atomic drivers all have the same function getting the
> only encoder available in the connector, also atomic drivers have
> this fallback. So moving it a common place and sharing between atomic
> and non-atomic driv
== Series Details ==
Series: drm/i915: Squeeze iommu status into debugfs/i915_capabilities
URL : https://patchwork.freedesktop.org/series/66530/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6868_full -> Patchwork_14359_full
1 - 100 of 145 matches
Mail list logo
