We are meant to register the kmem cache at init, such the supplied exit
and shrink hooks can be called.
Signed-off-by: Matthew Auld
---
drivers/gpu/drm/i915/i915_buddy.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_buddy.c
b/drivers/gpu/drm/i915/i915_buddy.c
ind
== Series Details ==
Series: drm/i915/buddy: add missing call to i915_global_register
URL : https://patchwork.freedesktop.org/series/66263/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6838 -> Patchwork_14280
Summary
-
When trying to reset a device with reset capability disabled or not
supported while rings are full of requests, it has been observed when
running in execlists submission mode that command stream buffer tail
tends to be incremented by apparently still running GPU regardless of
all requests being alr
== Series Details ==
Series: drm/i915/buddy: add missing call to i915_global_register
URL : https://patchwork.freedesktop.org/series/66263/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6838_full -> Patchwork_14280_full
Sum
== Series Details ==
Series: drm/i915: Don't unwedge if reset is disabled
URL : https://patchwork.freedesktop.org/series/66264/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6838 -> Patchwork_14281
Summary
---
**SUCC
From: Ville Syrjälä
The panel fitter imposes extra limits on the maximum pipe source
size we can use. Check for that.
v2: Skip the checks if the crtc is disabled
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 57
1 file changed, 57 inserti
From: Ville Syrjälä
Make sure we're not exceeding the max scaling factors for the panel
fitter.
v2: Rebase due to crtc enable check
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 46 +++-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --
From: Ville Syrjälä
Transcoder hdisplay/vdisplay have documented minimum limits
when using the panel fitter. Enforce those limits.
v2: Skip the checks if the crtc is disabled
Add debugs for the failures
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 63 +++
This series introduce to drm a way to determine if something else
except connection_status had changed during probing, which
can be used by other drivers as well. Another i915 specific part
uses this approach to determine if edid had changed without
changing the connection status and send a hotplug
This counter will be used by drm_helper_probe_detect caller to determine
if something else had changed except connection status,
like for example edid. Hardware specific drivers are responsible
for updating this counter when some change is detected to notify
the drm part, which can trigger for exam
Added edid checking to dp and hdmi edid setting functions, which
are called from detect hooks. The result currently is propagated
to calling layer using drm_connector->change_counter(proposed by Daniel Vetter).
drm_helper_hpd_irq_event and intel_encoder_hotplug are currently both
responsible for ch
Many drivers would benefit from using
drm helper to compare edid, rather
than bothering with own implementation.
v2: Added documentation for this function.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/drm_edid.c | 33 +
include/drm/drm_edid.h | 9 +
== Series Details ==
Series: drm/i915: Don't unwedge if reset is disabled
URL : https://patchwork.freedesktop.org/series/66264/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6838_full -> Patchwork_14281_full
Summary
---
On Wed, Sep 04, 2019 at 04:02:41PM -0700, José Roberto de Souza wrote:
> Tiger Lake has up to 4 pipes so the mask would need to be 0xf instead of
> 0x7. Do not hardcode the mask so it allows the fake MST encoders to
> connect to all pipes no matter how many the platform has.
>
> Iterating over all
This series introduce to drm a way to determine if something else
except connection_status had changed during probing, which
can be used by other drivers as well. Another i915 specific part
uses this approach to determine if edid had changed without
changing the connection status and send a hotplug
Many drivers would benefit from using
drm helper to compare edid, rather
than bothering with own implementation.
v2: Added documentation for this function.
Signed-off-by: Stanislav Lisovskiy
---
drivers/gpu/drm/drm_edid.c | 33 +
include/drm/drm_edid.h | 9 +
Added edid checking to dp and hdmi edid setting functions, which
are called from detect hooks. The result currently is propagated
to calling layer using drm_connector->change_counter(proposed by Daniel Vetter).
drm_helper_hpd_irq_event and intel_encoder_hotplug are currently both
responsible for ch
This counter will be used by drm_helper_probe_detect caller to determine
if something else had changed except connection status,
like for example edid. Hardware specific drivers are responsible
for updating this counter when some change is detected to notify
the drm part, which can trigger for exam
On Thu, Sep 05, 2019 at 06:38:30AM +, Lisovskiy, Stanislav wrote:
> On Mon, 2019-07-08 at 15:53 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Allow drivers to call drm_atomic_helper_check_modeset() without
> > having the crtc helper funcs specified. i915 doesn't need those
> > a
Op 05-09-2019 om 12:37 schreef Stanislav Lisovskiy:
> This counter will be used by drm_helper_probe_detect caller to determine
> if something else had changed except connection status,
> like for example edid. Hardware specific drivers are responsible
> for updating this counter when some change is
== Series Details ==
Series: drm/i915: Expose margin connector properties for underscan (rev4)
URL : https://patchwork.freedesktop.org/series/66225/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/edid: Add drm_hdmi_avi_infoframe_bars()
Okay!
Commi
Refactor the GT power management interface to work through the GT now
that it is under the control of gt/
Based on a patch by Chris Wilson.
Signed-off-by: Andi Shyti
Cc: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 1 +
drivers/gpu/drm/i915/gt/intel_gt.c | 45
The driver always assumes active GuC submission mode if it is
supported. That's not true if GuC initialization fails for some
reason. That may lead to kernel panics, caused e.g. by execlists
fallback submission mode incorrectly detecting GuC submission in use.
Fix it by also checking for GuC ena
On Thu, 2019-09-05 at 13:01 +0200, Maarten Lankhorst wrote:
> Op 05-09-2019 om 12:37 schreef Stanislav Lisovskiy:
> > This counter will be used by drm_helper_probe_detect caller to
> > determine
> > if something else had changed except connection status,
> > like for example edid. Hardware specific
== Series Details ==
Series: drm/i915: Expose margin connector properties for underscan (rev4)
URL : https://patchwork.freedesktop.org/series/66225/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6838 -> Patchwork_14282
Summ
== Series Details ==
Series: Send a hotplug when edid changes (rev6)
URL : https://patchwork.freedesktop.org/series/62816/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1b3a1a6c8669 drm: Add helper to compare edids.
-:32: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be wr
From: Michel Thierry
Gen12 has subtle changes in the reg state context offsets (some fields
are gone, some are in a different location), compared to previous Gens.
The simplest approach seems to be keeping Gen12 (and future platform)
changes apart from the previous gens, while keeping the regist
== Series Details ==
Series: Send a hotplug when edid changes (rev6)
URL : https://patchwork.freedesktop.org/series/62816/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6838 -> Patchwork_14283
Summary
---
**SUCCESS**
We're planning to use this for a couple of new feature where we need
to provide additional parameters to execbuf.
v2: Check for invalid flags in execbuffer2 (Lionel)
v3: Rename I915_EXEC_EXT -> I915_EXEC_USE_EXTENSIONS (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson (v1)
---
Reporting this version will help application figure out what level of
the support the running kernel provides.
v2: Add i915_perf_ioctl_version() (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_getparam.c | 4
drivers/gpu/drm/i915/i915_perf
Hi all,
While exercising this series with Renderdoc I found a couple of
issues :
- Leaked perf_fd in execbuf when running into an error
- The wait on the completion of the configure request being
interrupted
I also fixed an error return value issue reported by Dan Carpenter.
Cheers,
Here we introduce a mechanism by which the execbuf part of the i915
driver will be able to request that a batch buffer containing the
programming for a particular OA config be created.
We'll execute these OA configuration buffers right before executing a
set of userspace commands so that a particu
We'll use this information later to verify that a client trying to
reconfigure the stream does so on the right engine.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_drv.h | 5 +
drivers/gpu/drm/i915/i915_perf.c | 7 +++
2 files changed, 12 insertions(+)
diff --git a/dr
We want the ability to dispatch a set of command buffer to the
hardware, each with a different OA configuration. To achieve this, we
reuse a couple of fields from the execbuf2 struct (I CAN HAZ
execbuf3?) to notify what OA configuration should be used for a batch
buffer. This requires the process m
At some point in time there was the idea that we could have multiple
stream from the same piece of HW but that never materialized and given
the hard time we already have making everything work with the
submission side, there is no real point having this list of 1 element
around.
Signed-off-by: Lio
NOA configuration take some amount of time to apply. That amount of
time depends on the size of the GT. There is no documented time for
this. For example, past experimentations with powergating
configuration changes seem to indicate a 60~70us delay. We go with
500us as default for now which should
An upcoming change needs not to be interrupted.
Signed-off-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_active.c | 4 +++-
drivers/gpu/drm/i915/i915_active.h | 5 ++---
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_active.c
b/drivers/gpu/drm/i91
Introduces a new parameters to execbuf so that we can specify syncobj
handles as well as timeline points.
v2: Reuse i915_user_extension_fn
v3: Check that the chained extension is only present once (Chris)
v4: Check that dma_fence_chain_find_seqno returns a non NULL fence (Lionel)
v5: Use BIT_UL
We haven't run into issues with programming the global OA/NOA
registers configuration from CPU so far, but HW engineers actually
recommend doing this from the command streamer. On TGL in particular
one of the clock domain in which some of that programming goes might
not be powered when we poke thin
Listing configurations at the moment is supported only through sysfs.
This might cause issues for applications wanting to list
configurations from a container where sysfs isn't available.
This change adds a way to query the number of configurations and their
content through the i915 query uAPI.
v
We would like to make use of perf in Vulkan. The Vulkan API is much
lower level than OpenGL, with applications directly exposed to the
concept of command buffers (pretty much equivalent to our batch
buffers). In Vulkan, queries are always limited in scope to a command
buffer. In OpenGL, the lack of
If DROP_RESET_ACTIVE is requested while there is a large queue of pending
GEM requests, waiting for idle engines performed as a first step of
i915_gem_drop_caches debugfs request handler times out and an otherwise
healthy device is marked wedged. If that happens while reset capabilities
are disabl
On Thu, 05 Sep 2019 13:16:31 +0200, Janusz Krzysztofik
wrote:
The driver always assumes active GuC submission mode if it is
supported. That's not true if GuC initialization fails for some
reason. That may lead to kernel panics, caused e.g. by execlists
fallback submission mode incorrectly d
On Mon, Sep 02, 2019 at 09:08:12PM +0300, Jani Nikula wrote:
> Deconflate not having display hardware from having disabled display
> hardware, with some collateral improvements.
>
> This doesn't actually fix any of the issues resulting from the two being
> conflated, but unblocks fixing both indep
== Series Details ==
Series: drm/i915: Hook up GT power management (rev2)
URL : https://patchwork.freedesktop.org/series/66137/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6838 -> Patchwork_14284
Summary
---
**SUCC
On Thu, Sep 05, 2019 at 01:37:06PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The panel fitter imposes extra limits on the maximum pipe source
> size we can use. Check for that.
>
> v2: Skip the checks if the crtc is disabled
>
> Signed-off-by: Ville Syrjälä
> ---
> drivers/gpu/drm
On Wed, Sep 4, 2019 at 2:57 PM Kazlauskas, Nicholas
wrote:
>
> On 2019-09-03 3:06 p.m., Daniel Vetter wrote:
> > It's the only flag anyone actually cares about. Plus if we're unlucky,
> > the atomic ioctl might need a different flag for async flips. So
> > better to abstract this away from the uap
Hi Michał,
On Thursday, September 5, 2019 2:08:12 PM CEST Michal Wajdeczko wrote:
> On Thu, 05 Sep 2019 13:16:31 +0200, Janusz Krzysztofik
> wrote:
>
> > The driver always assumes active GuC submission mode if it is
> > supported. That's not true if GuC initialization fails for some
> > reaso
Resend of the first three patches of [1], omitting the one that fails CI
until I get that debugged.
BR,
Jani.
[1] https://patchwork.freedesktop.org/series/66135/
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org
Prepare for making a distinction between not having display and having
disabled display. Add INTEL_DISPLAY_ENABLED() and use it where
HAS_DISPLAY() is used. This is initially duplication, as disabling
display still leads to ->pipe_mask = 0 and HAS_DISPLAY() being false.
Since INTEL_DISPLAY_ENABLED
Replace device info number of pipes with a bit mask of available
pipes. This will prove handy in the future. There's still a bunch of
future work to do to actually allow a non-consecutive mask of pipes, but
it's a start. No functional changes.
Cc: Chris Wilson
Cc: José Roberto de Souza
Cc: Ville
Abstract away direct access to ->num_pipes to allow further
refactoring. No functional changes.
Cc: Chris Wilson
Cc: José Roberto de Souza
Cc: Ville Syrjälä
Reviewed-by: José Roberto de Souza
Acked-by: Ville Syrjälä
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/display/intel_display.c
On Wed, 04 Sep 2019, Matt Roper wrote:
> ICL+ DSI outputs operate a bit differently than DP/HDMI/eDP and are more
> closely tied to the PHY than to the DDI. Since we've separated PHY's
> out into their own namespace it makes sense to operate on 'enum phy'
> throughout most of the ICL DSI code rat
On Thu, 5 Sep 2019 at 01:25, Greg KH wrote:
>
> On Tue, Sep 03, 2019 at 02:55:26PM +0800, Baolin Wang wrote:
> > From: Chris Wilson
> >
> > If we skipped all the connectors that were not part of a tile, we would
> > leave conn_seq=0 and conn_configured=0, convincing ourselves that we
> > had stag
On Wed, 4 Sep 2019 at 21:19, Jani Nikula wrote:
>
> On Tue, 03 Sep 2019, Baolin Wang wrote:
> > From: Chris Wilson
> >
> > If we skipped all the connectors that were not part of a tile, we would
> > leave conn_seq=0 and conn_configured=0, convincing ourselves that we
> > had stagnated in our con
== Series Details ==
Series: drm/i915: Expose margin connector properties for underscan (rev4)
URL : https://patchwork.freedesktop.org/series/66225/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6838_full -> Patchwork_14282_full
On Wed, Sep 04, 2019 at 06:20:37PM -0700, Matt Roper wrote:
> ICL+ DSI outputs operate a bit differently than DP/HDMI/eDP and are more
> closely tied to the PHY than to the DDI. Since we've separated PHY's
> out into their own namespace it makes sense to operate on 'enum phy'
> throughout most of
== Series Details ==
Series: drm/i915/guc: Fix detection of GuC submission in use
URL : https://patchwork.freedesktop.org/series/66274/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6838 -> Patchwork_14285
Summary
---
On Thu, Sep 05, 2019 at 02:34:55PM +0300, Mika Kuoppala wrote:
> From: Michel Thierry
>
> Gen12 has subtle changes in the reg state context offsets (some fields
> are gone, some are in a different location), compared to previous Gens.
>
> The simplest approach seems to be keeping Gen12 (and futu
On Thu, Sep 05, 2019 at 02:14:03PM +0300, Andi Shyti wrote:
> Refactor the GT power management interface to work through the GT now
> that it is under the control of gt/
>
> Based on a patch by Chris Wilson.
>
> Signed-off-by: Andi Shyti
> Cc: Chris Wilson
Reviewed-by: Chris Wilson
Andi
_
== Series Details ==
Series: Send a hotplug when edid changes (rev6)
URL : https://patchwork.freedesktop.org/series/62816/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6838_full -> Patchwork_14283_full
Summary
---
*
== Series Details ==
Series: drm/i915/tgl: Register state context definition for Gen12
URL : https://patchwork.freedesktop.org/series/66276/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6838 -> Patchwork_14286
Summary
From: Ville Syrjälä
Modern platforms allow the transcoders hdisplay/vdisplay to exceed the
planes' max resolution. This has the nasty implication that modes on the
connectors' mode list may not be usable when the user asks for a
fullscreen plane. Seeing as that is the most common use case it seem
From: Ville Syrjälä
The officially validated plane width limit is 4k on skl+, however
we already had people using 5k displays before we started to enforce
the limit. Also it seems Windows allows 5k resolutions as well
(though not sure if they do it with one plane or two).
According to hw folks 5
On Thu, Sep 5, 2019 at 2:33 PM Mario Kleiner wrote:
> On Wed, Sep 4, 2019 at 2:57 PM Kazlauskas, Nicholas
> wrote:
> >
> > On 2019-09-03 3:06 p.m., Daniel Vetter wrote:
> > > It's the only flag anyone actually cares about. Plus if we're unlucky,
> > > the atomic ioctl might need a different flag
== Series Details ==
Series: drm/i915: Vulkan performance query support (rev15)
URL : https://patchwork.freedesktop.org/series/60916/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
CALLscripts/atomic/check-atomics.sh
DESCEND objtool
CHK include/generated/compile.
== Series Details ==
Series: series starting with [CI,1/3] drm/i915: add INTEL_NUM_PIPES() and use it
URL : https://patchwork.freedesktop.org/series/66281/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
32a7f2cee71f drm/i915: add INTEL_NUM_PIPES() and use it
f691171ff4b3 drm/i91
Op 03-09-2019 om 21:06 schreef Daniel Vetter:
> The -modesetting ddx has a totally broken idea of how atomic works:
> - doesn't disable old connectors, assuming they get auto-disable like
> with the legacy setcrtc
> - assumes ASYNC_FLIP is wired through for the atomic ioctl
> - not a single call
Matthew Auld writes:
> We are meant to register the kmem cache at init, such the supplied exit
> and shrink hooks can be called.
>
> Signed-off-by: Matthew Auld
Reviewed-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_buddy.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drive
On Thu, Sep 5, 2019 at 4:19 PM Maarten Lankhorst
wrote:
>
> Op 03-09-2019 om 21:06 schreef Daniel Vetter:
> > The -modesetting ddx has a totally broken idea of how atomic works:
> > - doesn't disable old connectors, assuming they get auto-disable like
> > with the legacy setcrtc
> > - assumes AS
== Series Details ==
Series: drm/i915: Hook up GT power management (rev2)
URL : https://patchwork.freedesktop.org/series/66137/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6838_full -> Patchwork_14284_full
Summary
---
== Series Details ==
Series: series starting with [CI,1/3] drm/i915: add INTEL_NUM_PIPES() and use it
URL : https://patchwork.freedesktop.org/series/66281/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6838 -> Patchwork_14288
===
The MCC hpd table is just a subset of the ICP table; we can eliminate it
and use the ICP table everywhere. The extra pins in the table won't be
a problem for MCC since we still supply an appropriate hotplug trigger
mask anywhere the pin table is used.
Cc: José Roberto de Souza
Signed-off-by: Mat
We generally assume future platforms will inherit the behavior of the
most recent platforms, so update our DDC pin mapping defaults to match
how ICP/TGP behave (i.e., pins starting from GMBUS_PIN_1_BXT for combo
PHY's and pins starting from GMBUS_PIN_9_TC1_ICP for TC PHY's). MCC's
non-standard han
== Series Details ==
Series: series starting with [1/2] drm/i915: Bump skl+ max plane width to 5k
for linear/x-tiled
URL : https://patchwork.freedesktop.org/series/66286/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6838 -> Patchwork_14289
===
== Series Details ==
Series: series starting with [1/2] drm/i915: Future-proof DDC pin mapping
URL : https://patchwork.freedesktop.org/series/66290/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6838 -> Patchwork_14290
Summ
On 9/5/2019 4:34 AM, Mika Kuoppala wrote:
From: Michel Thierry
Gen12 has subtle changes in the reg state context offsets (some fields
are gone, some are in a different location), compared to previous Gens.
The simplest approach seems to be keeping Gen12 (and future platform)
changes apart fr
== Series Details ==
Series: drm/i915/guc: Fix detection of GuC submission in use
URL : https://patchwork.freedesktop.org/series/66274/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6838_full -> Patchwork_14285_full
Summary
Hi Dave and Daniel,
Fixes for v5.3 final! Hopefully last for v5.3 now. :)
drm-misc-fixes-2019-09-05:
drm-misc-fixes for v5.3 final:
- Make ingenic panel type DPI instead of unknown.
- Fixes for command line parser modes.
The following changes since commit 6978bce054247e4cfccdf689ce263e076499f905:
== Series Details ==
Series: drm/i915/tgl: Register state context definition for Gen12
URL : https://patchwork.freedesktop.org/series/66276/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6838_full -> Patchwork_14286_full
Su
On Tue, Sep 3, 2019 at 12:07 PM Daniel Vetter wrote:
>
> The -modesetting ddx has a totally broken idea of how atomic works:
> - doesn't disable old connectors, assuming they get auto-disable like
> with the legacy setcrtc
> - assumes ASYNC_FLIP is wired through for the atomic ioctl
> - not a si
On Thu, 2019-09-05 at 00:56 +, Patchwork wrote:
> == Series Details ==
>
> Series: series starting with [1/2] drm/i915: Apply FBC WA for TGL too
> URL : https://patchwork.freedesktop.org/series/66240/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_6837_full -> Pat
Unlike gen11, which always ran at 50MHz when the cdclk PLL was disabled,
TGL runs at refclk/2. The 50MHz croclk/2 is only used by hardware
during some power state transitions.
Bspec: 49201
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 7 ++
The -modesetting ddx has a totally broken idea of how atomic works:
- doesn't disable old connectors, assuming they get auto-disable like
with the legacy setcrtc
- assumes ASYNC_FLIP is wired through for the atomic ioctl
- not a single call to TEST_ONLY
Iow the implementation is a 1:1 translatio
Add support to load the latest version of HuC on SKL.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc
Add support to load the latest version of HuC on CFL.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index d29ade3b7de6..f9fbb1f2fabf 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b
Add support to load the latest version of HuC on KBL.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc
Add support to load HuC on CML.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
index c8a22fde254c..c9e
Add support to load the latest version of HuC on ICL.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc
Add support to load the latest version of HuC on BXT.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc
Add support to load the latest version of HuC on GLK.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
b/drivers/gpu/drm/i915/gt/uc
The -modesetting ddx has a totally broken idea of how atomic works:
- doesn't disable old connectors, assuming they get auto-disable like
with the legacy setcrtc
- assumes ASYNC_FLIP is wired through for the atomic ioctl
- not a single call to TEST_ONLY
Iow the implementation is a 1:1 translatio
== Series Details ==
Series: drm/i915/tgl: Use refclk/2 as bypass frequency
URL : https://patchwork.freedesktop.org/series/66293/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6839 -> Patchwork_14291
Summary
---
**SU
== Series Details ==
Series: series starting with drm/atomic: Take the atomic toys away from X (rev2)
URL : https://patchwork.freedesktop.org/series/66180/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e86b20096a9f drm/atomic: Take the atomic toys away from X
-:36: WARNING:COMM
== Series Details ==
Series: series starting with drm/atomic: Take the atomic toys away from X (rev2)
URL : https://patchwork.freedesktop.org/series/66180/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6839 -> Patchwork_14292
===
== Series Details ==
Series: series starting with [1/8] drm/i915/firmware: Load v2.0.0 HuC for SKL
URL : https://patchwork.freedesktop.org/series/66295/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ffb4658195a6 drm/i915/firmware: Load v2.0.0 HuC for SKL
173f98eab10b drm/i915/f
For i965, add hw read out to create hw blob of gamma
lut values.
Review comments from old series:
https://patchwork.freedesktop.org/series/58039/
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
v5: -Returned blob instead of assigning
In this patch series, added state checker to validate gamma lut values
for cherryview and i965 platforms. It's extension of the
patch series https://patchwork.freedesktop.org/patch/328246/?series=58039
which enabled the basic infrastructure and state checker for
few legacy platforms.
Swati Sharma
For cherryview, add hw read out to create hw blob of gamma
lut values.
Review comments from previous series:
https://patchwork.freedesktop.org/patch/328252
v4: -No need to initialize *blob [Jani]
-Removed right shifts [Jani]
-Dropped dev local var [Jani]
v5: -Returned blob instead of assi
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