/commits/Chris-Wilson/drm-i915-selftests-Add-the-usual-batch-vma-managements-to-st_workarounds/20190827-004721
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-allyesconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-10) 7.4.0
reproduce:
# save the
Hello Ankit,
On 8/27/2019 11:59 AM, Nautiyal, Ankit K wrote:
From: Ankit Nautiyal
Currently, the transcoder port sync feature is not available, due to
which the 5K-tiled dual DP monitors experience corruption when
2560x2880 mode is applied for both of the tiled DP connectors.
Bugzilla: https:/
On 26/08/2019 15.48, Chris Wilson wrote:
> Quoting Abdiel Janulgue (2019-08-26 13:21:02)
>> +int
>> +i915_gem_mmap_dumb(struct drm_file *file,
>> + struct drm_device *dev,
>> + u32 handle,
>> + u64 *offset)
>> +{
>> + struct drm_i915_private *
On Mon, Aug 26, 2019 at 04:20:00PM +0100, Chris Wilson wrote:
> Signed-off-by: Chris Wilson
> Cc: Abdiel Janulgue
> ---
> tests/i915/gem_mmap_gtt.c | 98 +++
> 1 file changed, 98 insertions(+)
>
> diff --git a/tests/i915/gem_mmap_gtt.c b/tests/i915/gem_mmap_g
Yf tiling was removed in gen-12, so do not expose Yf modifiers to user
space. Gen-12 display also is incompatible with pre-gen12 Y-tiled
CCS, so do not expose I915_FORMAT_MOD_Y_TILED_CCS.
v2: Rebase to carry forward recently added gen11 formats.
Cc: Ville Syrjälä
Cc: Stanislav Lisovskiy
Signed-
== Series Details ==
Series: series starting with [CI,1/8] drm/i915/tgl: Guard and warn if more than
one eDP panel is present
URL : https://patchwork.freedesktop.org/series/65835/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6787 -> Patchwork_14193
==
== Series Details ==
Series: New cdclk values for gen11+
URL : https://patchwork.freedesktop.org/series/65838/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6787 -> Patchwork_14194
Summary
---
**SUCCESS**
No regre
On 26/08/2019 08:21, Chris Wilson wrote:
To properly handle asynchronous migration of batch objects, we need to
couple the fences on the incoming batch into the request and should not
assume that they always start idle.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
Reviewed-by: Matthew Auld
On Thu, 22 Aug 2019, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Reogranize the HDMI deep color state computation to just
> loop over possible bpc values. Avoids having to maintain
> so many variants of the clock etc.
>
> The current code also looks confused w.r.t. port_clock vs.
> bw_constrai
On 26/08/2019 14:07, Chris Wilson wrote:
The intention is that we first try to pin the current vma into the
mappable aperture only if it is already in use or t fits in the free
it fits
space and will not cause contention. The first attempt was meant to be
using PIN_NOEVICT to reuse the current
Hi Shashank,
Thanks for the comments.
If we see the connector info, the 5K display is detected as two DP
connectors with the various modes (pasted below, based on some limited
experimentation with Dell UP2715K Panel).
The problem is only observed when on both the connectors the mode
2560x2880
Hi Lu,
On Monday, August 26, 2019 10:29:12 AM CEST Lu Baolu wrote:
> Hi Janusz,
>
> On 8/26/19 4:15 PM, Janusz Krzysztofik wrote:
> > Hi Lu,
> >
> > On Friday, August 23, 2019 3:51:11 AM CEST Lu Baolu wrote:
> >> Hi,
> >>
> >> On 8/22/19 10:29 PM, Janusz Krzysztofik wrote:
> >>> When a perfectly
Hello Chris Wilson,
The patch 75b974a859e5: "drm/i915/selftests: Teach igt_gpu_fill_dw()
to take intel_context" from Aug 24, 2019, leads to the following
static checker warning:
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c:402 igt_ctx_exec()
error: 'ce' dereferencing poss
Quoting Dan Carpenter (2019-08-27 10:40:16)
> Hello Chris Wilson,
>
> The patch 75b974a859e5: "drm/i915/selftests: Teach igt_gpu_fill_dw()
> to take intel_context" from Aug 24, 2019, leads to the following
> static checker warning:
>
> drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
If we create a new live_context() we should have a mapping for each
engine. Document that assumption with an assertion.
Reported-by: Dan Carpenter
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c | 3 +++
1 file changed, 3 insertions(+)
di
== Series Details ==
Series: drm/i915: Prune 2560x2880 mode for 5K tiled dual DP monitors
URL : https://patchwork.freedesktop.org/series/65845/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6787 -> Patchwork_14195
Summary
-
On 27/08/2019 10:49, Chris Wilson wrote:
If we create a new live_context() we should have a mapping for each
engine. Document that assumption with an assertion.
Reported-by: Dan Carpenter
Signed-off-by: Chris Wilson
Cc: Matthew Auld
Reviewed-by: Matthew Auld
Regards
Shashank
On 8/22/2019 8:49 PM, Ramalingam C wrote:
From Gen12 onwards, HDCP HW block is implemented within transcoders.
Till Gen11 HDCP HW block was part of DDI.
Hence required changes in HW programming is handled here.
As ME FW needs the transcoder detail on which HDCP is enabled
on
On Tue, 27 Aug 2019, "Nautiyal, Ankit K" wrote:
> From: Ankit Nautiyal
>
> Currently, the transcoder port sync feature is not available, due to
> which the 5K-tiled dual DP monitors experience corruption when
> 2560x2880 mode is applied for both of the tiled DP connectors.
> Bugzilla: https://bug
Enabling the HDCP1.4 and 2.2 on TGL by supporting the HW block movement
from DDI into transcoder.
v10:
Review comments from shashank addressed
Ramalingam C (6):
drm/i915: mei_hdcp: I915 sends ddi index as per ME FW
drm: Move port definition back to i915 header
drm: Extend I915 mei interfa
We dont need the definition of the enum port outside I915, anymore.
Hence move enum port definition into I915 driver itself.
v2:
intel_display.h is included in intel_hdcp.h
v3:
enum port is declared in headers.
v4:
commit msg is rephrased.
Signed-off-by: Ramalingam C
Reviewed-by: Jani Niku
I915 converts it's port value into ddi index defiend by ME FW
and pass it as a member of hdcp_port_data structure.
Hence expose the enum mei_fw_ddi to I915 through
i915_mei_interface.h.
Signed-off-by: Ramalingam C
Acked-by: Jani Nikula
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/i915/dis
I915 needs to send the index of the transcoder as per ME FW.
To support this, define enum mei_fw_tc and add as a member into
the struct hdcp_port_data.
v2:
Typo in commit msg is fixed [Shashank]
Signed-off-by: Ramalingam C
Acked-by: Jani Nikula
---
include/drm/i915_mei_hdcp_interface.h | 13
For gen12+ platform we need to pass the transcoder info
as part of the port info into ME FW.
This change fills the payload for ME FW from hdcp_port_data.
Signed-off-by: Ramalingam C
Acked-by: Jani Nikula
Reviewed-by: Shashank Sharma
---
drivers/misc/mei/hdcp/mei_hdcp.c | 11 +++
drive
>From Gen12 onwards, HDCP HW block is implemented within transcoders.
Till Gen11 HDCP HW block was part of DDI.
Hence required changes in HW programming is handled here.
As ME FW needs the transcoder detail on which HDCP is enabled
on Gen12+ platform, we are populating the detail in hdcp_port_dat
On gen12+ platforms, HDCP HW is associated to the transcoder.
Hence on every modeset update associated transcoder into the
intel_hdcp of the port.
v2:
s/trans/cpu_transcoder [Jani]
v3:
comment is added for fw_ddi init for gen12+ [Shashank]
only hdcp capable transcoder is translated into fw_t
== Series Details ==
Series: drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
URL : https://patchwork.freedesktop.org/series/65858/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6790 -> Patchwork_14196
Su
Quite rarely we see that the CS completion event fires before the
breadcrumb is coherent. Try rearranging the breadcrumb write sequence
such that the CS_STALL is on the post-sync write pipecontrol.
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 17 ++
Quoting Chris Wilson (2019-08-27 12:54:13)
> Quite rarely we see that the CS completion event fires before the
> breadcrumb is coherent. Try rearranging the breadcrumb write sequence
> such that the CS_STALL is on the post-sync write pipecontrol.
>
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppal
Quite rarely we see that the CS completion event fires before the
breadcrumb is coherent, which presumably is a result of the CS_STALL not
waiting for the post-sync operation. Try following in a DC_FLUSH into
the following pipecontrol to see if that makes any difference.
Signed-off-by: Chris Wilso
== Series Details ==
Series: series starting with [CI,1/8] drm/i915/tgl: Guard and warn if more than
one eDP panel is present
URL : https://patchwork.freedesktop.org/series/65835/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6787_full -> Patchwork_14193_full
== Series Details ==
Series: drm/i915/selftests: Markup impossible error pointers
URL : https://patchwork.freedesktop.org/series/65862/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6791 -> Patchwork_14197
Summary
---
== Series Details ==
Series: drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ (rev8)
URL : https://patchwork.freedesktop.org/series/63432/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6791 -> Patchwork_14198
Summary
---
== Series Details ==
Series: drm/i915/execlists: stall on render flush before writing seqno
URL : https://patchwork.freedesktop.org/series/65869/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6791 -> Patchwork_14199
Summary
On 8/13/2019 8:16 PM, Imre Deak wrote:
On Sat, Aug 10, 2019 at 12:02:17AM +0530, Anshuman Gupta wrote:
"DC3CO Off" power well inherits its power domains from
"DC Off" power well, these power domains will disallow
DC3CO when any external displays are connected and at
time of modeset and aux pro
> Enabling the HDCP1.4 and 2.2 on TGL by supporting the HW block movement
> from DDI into transcoder.
In some files needs to bump the copyright to 2019.
>
> v10:
> Review comments from shashank addressed
>
> Ramalingam C (6):
> drm/i915: mei_hdcp: I915 sends ddi index as per ME FW
> drm
On Tue, Aug 27, 2019 at 06:31:31PM +0530, Gupta, Anshuman wrote:
>
>
> On 8/13/2019 8:16 PM, Imre Deak wrote:
> > On Sat, Aug 10, 2019 at 12:02:17AM +0530, Anshuman Gupta wrote:
> > > "DC3CO Off" power well inherits its power domains from
> > > "DC Off" power well, these power domains will disall
On 2019-08-27 at 18:32:13 +0530, Winkler, Tomas wrote:
>
> > Enabling the HDCP1.4 and 2.2 on TGL by supporting the HW block movement
> > from DDI into transcoder.
>
> In some files needs to bump the copyright to 2019.
Tomas,
I am not aware when a copyright year needs to be bumped, as
copyrigh
The point of debug_object_activate is to mark we first, only the first,
acquisition. The object then remains active until the last release.
However, we marked up all successful first acquires even though we
allowed concurrent parties to try and acquire the i915_active
simultaneously (serialised by
Only files are that are modified in this year should be updated.
For example.
include/drm/i915_mei_hdcp_interface.h
- * Copyright © 2017-2018 Intel Corporation
+ * Copyright © 2017-2019 Intel Corporation
> -Original Message-
> From: C, Ramalingam
> Sent: Tuesday, August 27, 2019 16:23
== Series Details ==
Series: New cdclk values for gen11+
URL : https://patchwork.freedesktop.org/series/65838/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6787_full -> Patchwork_14194_full
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915/execlists: Flush the post-sync breadcrumb write harder
URL : https://patchwork.freedesktop.org/series/65871/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6792 -> Patchwork_14200
Summar
On Fri, 2019-08-23 at 13:07 +0300, Imre Deak wrote:
> There is a difference in BSpec's and the driver's designation of DDI
> ports. BSpec uses the following names:
> - before GEN11:
> BSpec/driver:
> port A/B/C/D etc
> - GEN11:
> BSpec/driver:
> port A-F
> - GEN12:
> BSpec:
>
On Mon, Aug 26, 2019 at 03:55:39PM -0700, Matt Roper wrote:
> The bspec has just recently been updated with new cdclk values that
> require the use of a /2 CD2X divider rather than a /1 divider. Once we
> add the divider selection logic to ICL+ cdclk programming, we have
> pretty much the same log
On Tue, Aug 27, 2019 at 04:42:12PM +0300, Lisovskiy, Stanislav wrote:
> On Fri, 2019-08-23 at 13:07 +0300, Imre Deak wrote:
> > There is a difference in BSpec's and the driver's designation of DDI
> > ports. BSpec uses the following names:
> > - before GEN11:
> > BSpec/driver:
> > port A/B/C/
A virtual engine itself does not have a batch pool, but we can gleefully
use any of its siblings instead.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++--
drivers/gpu/drm/i915/gem/i915_gem_object_blt.c | 4 ++--
drivers/gpu/drm/i915/gt/
>
> I915 needs to send the index of the transcoder as per ME FW.
>
> To support this, define enum mei_fw_tc and add as a member into the struct
> hdcp_port_data.
>
> v2:
> Typo in commit msg is fixed [Shashank]
>
> Signed-off-by: Ramalingam C
> Acked-by: Jani Nikula
> ---
> include/drm/i91
On Mon, Aug 26, 2019 at 09:39:48AM +0100, Chris Wilson wrote:
> Quoting Prathap Kumar Valsan (2019-08-26 00:35:27)
> > To provide shared last-level-cache isolation to cpu workloads running
> > concurrently with gpu workloads, the gpu allocation of cache lines needs
> > to be restricted to certain w
On Mon, Aug 26, 2019 at 10:17:55AM +0100, Chris Wilson wrote:
> Quoting Prathap Kumar Valsan (2019-08-26 00:35:27)
> > To provide shared last-level-cache isolation to cpu workloads running
> > concurrently with gpu workloads, the gpu allocation of cache lines needs
> > to be restricted to certain w
On Mon, Aug 26, 2019 at 3:26 PM Andrzej Pietrasiewicz
wrote:
>
> Use the ddc pointer provided by the generic connector.
>
> Signed-off-by: Andrzej Pietrasiewicz
Acked-by: Alex Deucher
> ---
> drivers/gpu/drm/radeon/radeon_connectors.c | 143 +++--
> 1 file changed, 107 inserti
With DSC, bpp can be fractional in multiples of 1/16.
Change drm_dp_calc_pbn_mode to reflect this, adding a new
parameter bool dsc. When this parameter is true, treat the
bpp parameter as having units not of bits per pixel, but
1/16 of a bit per pixel
v2: Don't add separate function for this
Cc:
On Fri, 2019-08-23 at 13:07 +0300, Imre Deak wrote:
> There is a difference in BSpec's and the driver's designation of DDI
> ports. BSpec uses the following names:
> - before GEN11:
> BSpec/driver:
> port A/B/C/D etc
> - GEN11:
> BSpec/driver:
> port A-F
> - GEN12:
> BSpec:
>
> For gen12+ platform we need to pass the transcoder info as part of the port
> info into ME FW.
>
> This change fills the payload for ME FW from hdcp_port_data.
>
> Signed-off-by: Ramalingam C
> Acked-by: Jani Nikula
> Reviewed-by: Shashank Sharma
> ---
> drivers/misc/mei/hdcp/mei_hdcp.c | 1
== Series Details ==
Series: drm/i915: Only activate i915_active debugobject once
URL : https://patchwork.freedesktop.org/series/65874/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6792 -> Patchwork_14201
Summary
---
On 2019-08-27 at 19:30:23 +0530, Winkler, Tomas wrote:
> >
> > I915 needs to send the index of the transcoder as per ME FW.
> >
> > To support this, define enum mei_fw_tc and add as a member into the struct
> > hdcp_port_data.
> >
> > v2:
> > Typo in commit msg is fixed [Shashank]
> >
> > Sig
On 2019-08-26 3:25 p.m., Andrzej Pietrasiewicz wrote:
> Use the ddc pointer provided by the generic connector.
>
> Signed-off-by: Andrzej Pietrasiewicz
Reviewed-by: Harry Wentland
Harry
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++--
> 1 file changed, 3 insertions(+), 2
On 2019-08-26 2:05 p.m., David Francis wrote:
> With DSC, bpp can be fractional in multiples of 1/16.
>
> Change drm_dp_calc_pbn_mode to reflect this, adding a new
> parameter bool dsc. When this parameter is true, treat the
> bpp parameter as having units not of bits per pixel, but
> 1/16 of a bi
On 2019-08-27 at 19:49:19 +0530, Winkler, Tomas wrote:
> > For gen12+ platform we need to pass the transcoder info as part of the port
> > info into ME FW.
> >
> > This change fills the payload for ME FW from hdcp_port_data.
> >
> > Signed-off-by: Ramalingam C
> > Acked-by: Jani Nikula
> > Revi
> On gen12+ platforms, HDCP HW is associated to the transcoder.
> Hence on every modeset update associated transcoder into the intel_hdcp of
> the port.
>
> v2:
> s/trans/cpu_transcoder [Jani]
> v3:
> comment is added for fw_ddi init for gen12+ [Shashank]
> only hdcp capable transcoder is tr
Quoting Kumar Valsan, Prathap (2019-08-27 15:17:51)
> We want to support this on Gen11 as well, where these registers
> are context saved and restored and we prime the register values of new
> contexts
> from recorded defaults. What could be the correct way to handle this, write
> to the
> defaul
>
> On 2019-08-27 at 19:49:19 +0530, Winkler, Tomas wrote:
> > > For gen12+ platform we need to pass the transcoder info as part of
> > > the port info into ME FW.
> > >
> > > This change fills the payload for ME FW from hdcp_port_data.
> > >
> > > Signed-off-by: Ramalingam C
> > > Acked-by: Jan
On 2019-08-27 at 20:07:04 +0530, Winkler, Tomas wrote:
>
> >
> > On 2019-08-27 at 19:49:19 +0530, Winkler, Tomas wrote:
> > > > For gen12+ platform we need to pass the transcoder info as part of
> > > > the port info into ME FW.
> > > >
> > > > This change fills the payload for ME FW from hdcp_po
On Tue, Aug 27, 2019 at 03:35:14PM +0100, Chris Wilson wrote:
> Quoting Kumar Valsan, Prathap (2019-08-27 15:17:51)
> > We want to support this on Gen11 as well, where these registers
> > are context saved and restored and we prime the register values of new
> > contexts
> > from recorded defaults
On 2019-08-27 at 20:03:21 +0530, Winkler, Tomas wrote:
> > On gen12+ platforms, HDCP HW is associated to the transcoder.
> > Hence on every modeset update associated transcoder into the intel_hdcp of
> > the port.
> >
> > v2:
> > s/trans/cpu_transcoder [Jani]
> > v3:
> > comment is added for f
== Series Details ==
Series: drm/i915: Make engine batch pool's safe for use with virtual engines
URL : https://patchwork.freedesktop.org/series/65875/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6792 -> Patchwork_14202
S
If we are writing the relocations using the GPU they will not be written
into the batch immediately. Instead there will be a write-fence while
the relocation is being performed, giving us something to conveniently
wait upon.
Signed-off-by: Chris Wilson
---
tests/i915/gem_exec_big.c | 10 ++--
On 27/08/2019 14:26, Chris Wilson wrote:
The point of debug_object_activate is to mark we first, only the first,
acquisition.
-eparse
The object then remains active until the last release.
However, we marked up all successful first acquires even though we
allowed concurrent parties to try and
Quoting Matthew Auld (2019-08-27 16:30:40)
> On 27/08/2019 14:26, Chris Wilson wrote:
> > The point of debug_object_activate is to mark we first, only the first,
> > acquisition.
> -eparse
It was meant to be "the first, and only the first,"
-Chris
___
I
On 27/08/2019 14:59, Chris Wilson wrote:
A virtual engine itself does not have a batch pool, but we can gleefully
use any of its siblings instead.
Signed-off-by: Chris Wilson
Cc: Matthew Auld
Reviewed-by: Matthew Auld
___
Intel-gfx mailing list
In
On Mon, 26 Aug 2019 at 08:24, Chris Wilson wrote:
>
> Upon object creation for live_gem_contexts, we fill the object with
> known scratch and flush it out of the CPU cache. Before performing the
> GPU fill, we don't need to flush it again and so avoid serialising with
> previous fills.
>
> However
Upon object creation for live_gem_contexts, we fill the object with
known scratch and flush it out of the CPU cache. Before performing the
GPU fill, we don't need to flush it again and so avoid serialising with
previous fills.
However, we do need some throttling on the internal interfaces if we do
On Mon, 26 Aug 2019 at 08:23, Chris Wilson wrote:
>
> igt_ctx_exec allocates a new context for each iteration, keeping them
> all allocated until the end. Instead, release the local ctx reference at
> the end of each iteration, allowing ourselves to reap those if under
> mempressure.
>
> Signed-of
e.g. benchmarks/gem_wsim.c:2936:4: warning: absolute value function ‘abs’ given
an argument of type ‘long int’ but has parameter of type ‘int’ which may cause
truncation of value [-Wabsolute-value]
Signed-off-by: Chris Wilson
---
benchmarks/gem_syslatency.c | 2 +-
benchmarks/gem_wsim.c
igt_ctx_exec allocates a new context for each iteration, keeping them
all allocated until the end. Instead, release the local ctx reference at
the end of each iteration, allowing ourselves to reap those if under
mempressure.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/
Upon object creation for live_gem_contexts, we fill the object with
known scratch and flush it out of the CPU cache. Before performing the
GPU fill, we don't need to flush it again and so avoid serialising with
previous fills.
However, we do need some throttling on the internal interfaces if we do
On 8/27/2019 6:50 PM, Imre Deak wrote:
On Tue, Aug 27, 2019 at 06:31:31PM +0530, Gupta, Anshuman wrote:
On 8/13/2019 8:16 PM, Imre Deak wrote:
On Sat, Aug 10, 2019 at 12:02:17AM +0530, Anshuman Gupta wrote:
"DC3CO Off" power well inherits its power domains from
"DC Off" power well, these p
On Mon, Aug 26, 2019 at 10:43:36AM -0700, Runyan, Arthur J wrote:
-Original Message-
From: Imre Deak
Sent: Monday, 26 August, 2019 6:42 AM
To: Souza, Jose ; De Marchi, Lucas
; Runyan, Arthur J
Cc: intel-gfx@lists.freedesktop.org; Pandiyan, Dhinakaran
Subject: Re: [Intel-gfx] [PATCH v3
On Mon, Aug 26, 2019 at 08:28:33PM +0300, Imre Deak wrote:
On Fri, Aug 23, 2019 at 01:20:35AM -0700, Lucas De Marchi wrote:
From: José Roberto de Souza
It was enabling and checking PSR interruptions in every transcoder
while it should keep the interruptions on the non-used transcoders
masked.
On Tue, Aug 27, 2019 at 01:34:15PM +0300, Jani Nikula wrote:
> On Tue, 27 Aug 2019, "Nautiyal, Ankit K" wrote:
> > From: Ankit Nautiyal
> >
> > Currently, the transcoder port sync feature is not available, due to
> > which the 5K-tiled dual DP monitors experience corruption when
> > 2560x2880 mod
== Series Details ==
Series: drm/i915/selftests: Remove accidental serialization between gpu_fill
URL : https://patchwork.freedesktop.org/series/65886/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6794 -> Patchwork_14203
S
On Tue, 2019-08-27 at 09:36 -0700, Lucas De Marchi wrote:
> On Mon, Aug 26, 2019 at 10:43:36AM -0700, Runyan, Arthur J wrote:
> > > -Original Message-
> > > From: Imre Deak
> > > Sent: Monday, 26 August, 2019 6:42 AM
> > > To: Souza, Jose ; De Marchi, Lucas
> > > ; Runyan, Arthur J <
> > >
== Series Details ==
Series: drm/i915: Prune 2560x2880 mode for 5K tiled dual DP monitors
URL : https://patchwork.freedesktop.org/series/65845/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6787_full -> Patchwork_14195_full
The CS pre-parser can pre-fetch commands across memory sync points and
starting from gen12 it is able to pre-fetch across BB_START and BB_END
boundaries as well, so when we emit gpu relocs the pre-parser might
fetch the target location of the reloc before the memory write lands.
The parser can't p
Added docbook info regarding Display State Buffer(DSB) which
is added from gen12 onwards to batch submit display HW programming.
v1: Initial version as RFC.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Acked-by: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
Documentation/gpu/i915.rst | 9
The function will internally get the gem buffer from global GTT
which is mapped in cpu domain to feed the data + opcode for DSB engine.
v1: initial version.
v2:
- removed some unwanted code. (Chris)
- Used i915_gem_object_create_internal instead of _shmem. (Chris)
- cmd_buf_tail removed and can
Added key register definitions of DSB.
dsb-ctrl register is required to enable dsb-engine.
head-ptr register hold the head of buffer address from where the
execution will start.
Programming tail-ptr register is a trigger point to start execution.
Cc: Uma Shankar
Cc: Jani Nikula
Cc: Rodrigo Vi
DSB support single register write through opcode 0x1. Generic
api created which accumulate all single register write in a batch
buffer and once DSB is triggered, it will program all the registers
at the same time.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/dr
DSB will be used for performance improvement for some special scenario.
DSB engine will be enabled based on need and after completion of its work
will be disabled. Api added for enable/disable operation by using DSB_CTRL
register.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-b
As per bspec check for DSB status before programming any
of its register. Inline function added to check the dsb status.
Cc: Michel Thierry
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/display/intel_dsb.c | 9 +
1 file changed, 9 insertions(+)
Gamma lut programming can be programmed using DSB
where bulk register programming can be done using indexed
register write which takes number of data and the mmio offset
to be written.
v1: Initial version.
v2: Directly call dsb-api at callsites. (Jani)
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-of
From gen12 onwards Display State Buffer(DSB) is hardware capability
added which allows driver to batch submit display HW programming.
Feature flag has_dsb added to identify the driver/platform support
at runtime.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm
Display State Buffer (DSB) is hardware capability which allows driver
to batch submit HW programming.
As part of initial enablement common api created which currently used
to program gamma lut proramming.
Going forwad DSB support can be added for HDR and flip related operation.
HSDES: 1209978241
Batch buffer will be created through dsb-reg-write function which can have
single/multiple request based on usecase and once the buffer is ready
commit function will trigger the execution of the batch buffer. All
the registers will be updated simultaneously.
v1: Initial version.
v2: Optimized code
DSB can program large set of data through indexed register write
(opcode 0x9) in one shot. Will be using for bulk register programming
e.g. gamma lut programming, HDR meta data programming.
v1: Initial version.
v2: simplified code by using ALIGN(). (Chris)
Cc: Shashank Sharma
Cc: Imre Deak
Cc:
Enabling DSB by setting 1 to has_dsb flag for gen12.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Animesh Manna
---
drivers/gpu/drm/i915/i915_pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 1
== Series Details ==
Series: DSB enablement. (rev3)
URL : https://patchwork.freedesktop.org/series/63013/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
da32d51f5b17 drm/i915/dsb: feature flag added for display state buffer.
3b8233fa3574 drm/i915/dsb: DSB context creation.
-:49:
== Series Details ==
Series: DSB enablement. (rev3)
URL : https://patchwork.freedesktop.org/series/63013/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/dsb: feature flag added for display state buffer.
Okay!
_
Quoting Daniele Ceraolo Spurio (2019-08-27 19:58:05)
> The CS pre-parser can pre-fetch commands across memory sync points and
> starting from gen12 it is able to pre-fetch across BB_START and BB_END
> boundaries as well, so when we emit gpu relocs the pre-parser might
> fetch the target location of
== Series Details ==
Series: drm/i915: use a separate context for gpu relocs (rev2)
URL : https://patchwork.freedesktop.org/series/65729/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6794 -> Patchwork_14205
Summary
---
== Series Details ==
Series: DSB enablement. (rev3)
URL : https://patchwork.freedesktop.org/series/63013/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6794 -> Patchwork_14206
Summary
---
**SUCCESS**
No regression
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