== Series Details ==
Series: drm/i915/selftests: Teach igt_gpu_fill_dw() to take intel_context (rev5)
URL : https://patchwork.freedesktop.org/series/65701/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6780_full -> Patchwork_14179_full
=
== Series Details ==
Series: drm/i915/selftests: Add the usual batch vma managements to
st_workarounds
URL : https://patchwork.freedesktop.org/series/65733/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6782_full -> Patchwork_14181_full
===
== Series Details ==
Series: dma-buf: Extend selftests to exercise dma-fence-array
URL : https://patchwork.freedesktop.org/series/65736/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6783_full -> Patchwork_14182_full
Summar
Am 24.08.19 um 21:12 schrieb Chris Wilson:
> Quoting Koenig, Christian (2019-08-24 20:04:43)
>> Am 24.08.19 um 15:58 schrieb Chris Wilson:
>>> In order to allow dma-fence-array as a generic container for fences, we
>>> need to allow for it to contain other dma-fence-arrays. By giving each
>>> dma-f
== Series Details ==
Series: dma-buf: Give dma-fence-array distinct lockclasses
URL : https://patchwork.freedesktop.org/series/65739/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6783_full -> Patchwork_14183_full
Summary
-
To provide shared last-level-cache isolation to cpu workloads running
concurrently with gpu workloads, the gpu allocation of cache lines needs
to be restricted to certain ways. Currently GPU hardware supports four
class-of-service(CLOS) levels and there is an associated way-mask for
each CLOS.
Har
== Series Details ==
Series: drm/i915/tgl: Add sysfs interface to control class-of-service
URL : https://patchwork.freedesktop.org/series/65769/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/tgl: Add sysfs interface to control class-of-servic
== Series Details ==
Series: drm/i915/tgl: Add sysfs interface to control class-of-service
URL : https://patchwork.freedesktop.org/series/65769/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6783 -> Patchwork_14184
Summary
To provide shared last-level-cache isolation to cpu workloads running
concurrently with gpu workloads, the gpu allocation of cache lines needs
to be restricted to certain ways. Currently GPU hardware supports four
class-of-service(CLOS) levels and there is an associated way-mask for
each CLOS.
Har
== Series Details ==
Series: drm/i915/tgl: Add sysfs interface to control class-of-service (rev2)
URL : https://patchwork.freedesktop.org/series/65769/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6783 -> Patchwork_14185
S
Hi all,
Today's linux-next merge of the drm tree got a conflict in:
drivers/gpu/drm/arm/display/komeda/komeda_dev.c
between commit:
51a44a28eefd ("drm/komeda: Add missing of_node_get() call")
from the drm-misc-fixes tree and commit:
8965ad8433ea ("drm/komeda: Enable dual-link support")
On 2019.08.23 09:35:22 +0100, Chris Wilson wrote:
> Quoting Zhang, Xiaolin (2019-08-23 09:07:01)
> > On 08/23/2019 03:58 PM, Chris Wilson wrote:
> > > Quoting Xiaolin Zhang (2019-08-23 07:57:31)
> > >> vgpu ppgtt notification was split into 2 steps, the first step is to
> > >> update PVINFO's pdp r
For the legacy gamma, have hw read out to create hw blob of gamma
lut values. Also, add function intel_color_lut_pack to convert hw value with
given bit_precision to lut property val.
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_color.c | 51 ++
Add func intel_color_lut_equal() to compare hw/sw gamma
lut values. Since hw/sw gamma lut sizes and lut enteries comparsion
will be different for different gamma modes, add gamma mode dependent
checks.
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_color.c | 71 ++
In this patch series, added state checker to validate gamma (8BIT and 10BIT).
This reads hardware state, and compares the originally requested state(s/w) to
the
state read from the hardware.
This is done for legacy, i965, ilk, glk and their variant platforms.
Intentionally, excluded bdw and ivb
Each platform supports different gamma modes and each gamma mode
has different bit precision. Add func/platform to get bit precision
corresponding to gamma mode.
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_color.c | 79 ++
drivers/gpu/drm/i915/d
Add macro to compare hw/sw gamma lut values. First need to
check whether hw/sw gamma mode matches or not. If not
no need to compare lut values, if matches then only compare
lut entries.
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_display.c | 25 +
1
For i965, have hw read out to create hw blob of gamma
lut values.
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_color.c | 39 ++
drivers/gpu/drm/i915/i915_reg.h| 3 +++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i
For glk, have hw read out to create hw blob of gamma
lut values.
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_color.c | 48 --
drivers/gpu/drm/i915/i915_reg.h| 3 ++
2 files changed, 49 insertions(+), 2 deletions(-)
diff --git a/dri
For ilk, have hw read out to create hw blob of gamma
lut values.
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_color.c | 41 +-
drivers/gpu/drm/i915/i915_reg.h| 3 +++
2 files changed, 43 insertions(+), 1 deletion(-)
diff --git a/dri
Add debug log for color related parameters like gamma_mode, gamma_enable,
csc_enable, etc inside intel_dump_pipe_config().
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_display.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_
For cherryview, have hw read out to create hw blob of gamma
lut values.
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_color.c | 39 ++
drivers/gpu/drm/i915/i915_reg.h| 3 +++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/display/intel_color.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c
b/drivers/gpu/drm/i915/display/intel_color.c
index 3762bdf..56fdf83 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
== Series Details ==
Series: drm/i915: adding state checker for gamma lut value
URL : https://patchwork.freedesktop.org/series/65784/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2922e0d8ceeb drm/i915/display: Add func to get gamma bit precision
766a11160765 drm/i915/display:
On 2019-08-23 at 01:20:37 -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza
>
> Now that is allowed to have PSR enabled in any port from BDW+, lets
> guard intel_psr_init_dpcd() against multiple eDP panels and warn about
> it.
>
> For now we will keep just one instance of PSR.
Looks go
== Series Details ==
Series: drm/i915: adding state checker for gamma lut value
URL : https://patchwork.freedesktop.org/series/65784/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/display: Add func to get gamma bit precision
Okay!
Commit: dr
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