== Series Details ==
Series: drm/i915: to make vgpu ppgtt notificaiton as atomic operation
URL : https://patchwork.freedesktop.org/series/65669/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
09841439a4f2 drm/i915: to make vgpu ppgtt notificaiton as atomic operation
-:28: CHECK:
We're planning to use this for a couple of new feature where we need
to provide additional parameters to execbuf.
v2: Check for invalid flags in execbuffer2 (Lionel)
v3: Rename I915_EXEC_EXT -> I915_EXEC_USE_EXTENSIONS (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson (v1)
---
Hi,
Just fiddling with enums to avoid default 0 values as recommended by
Jason.
Cheers,
Lionel Landwerlin (2):
drm/i915: introduce a mechanism to extend execbuf2
drm/i915: add syncobj timeline support
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 346 +++---
drivers/gpu/drm/i
Introduces a new parameters to execbuf so that we can specify syncobj
handles as well as timeline points.
v2: Reuse i915_user_extension_fn
v3: Check that the chained extension is only present once (Chris)
v4: Check that dma_fence_chain_find_seqno returns a non NULL fence (Lionel)
v5: Use BIT_UL
Quoting Daniele Ceraolo Spurio (2019-08-23 03:09:09)
> TGL has an improved CS pre-parser that can now pre-fetch commands across
> batch boundaries. This improves performances when lots of small batches
> are used, but has an impact on self-modifying code. If we want to modify
> the content of a bat
vgpu ppgtt notification was split into 2 steps, the first step is to
update PVINFO's pdp register and then write PVINFO's g2v_notify register
with action code to tirgger ppgtt notification to GVT side.
currently these steps were not atomic operations due to no any protection,
so it is easy to ente
== Series Details ==
Series: drm/i915: timeline semaphore support (rev5)
URL : https://patchwork.freedesktop.org/series/61032/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ba7c1e11cc5e drm/i915: introduce a mechanism to extend execbuf2
-:141: CHECK:SPACING: spaces preferred ar
== Series Details ==
Series: drm/i915: to make vgpu ppgtt notificaiton as atomic operation
URL : https://patchwork.freedesktop.org/series/65669/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6772 -> Patchwork_14153
Summary
Introduces a new parameters to execbuf so that we can specify syncobj
handles as well as timeline points.
v2: Reuse i915_user_extension_fn
v3: Check that the chained extension is only present once (Chris)
v4: Check that dma_fence_chain_find_seqno returns a non NULL fence (Lionel)
v5: Use BIT_UL
On Thu, 22 Aug 2019, Manasi Navare wrote:
> Ville/Maarten/Daniel,
>
> This is a simple rename patch as suggested by danvet, can any one of
> you review this? So that rest of Maarten's patches can also use these
> new functions.
Please repost the patches. They were posted two months ago, and neve
On Thu, 2019-08-22 at 22:39 +0530, Gupta, Anshuman wrote:
>
> On 8/22/2019 10:19 PM, Souza, Jose wrote:
> > On Thu, 2019-08-22 at 21:37 +0530, Gupta, Anshuman wrote:
> > > On 8/22/2019 1:36 AM, Souza, Jose wrote:
> > > > On Wed, 2019-08-21 at 10:06 +0530, Anshuman Gupta wrote:
> > > > > On 2019-08
Op 17-08-2019 om 11:38 schreef Lucas De Marchi:
> From: José Roberto de Souza
>
> On TGL the blending of all the streams have moved from DDI to
> transcoder, so now every transcoder working over the same MST port must
> send its stream to a master transcoder and master will send to DDI
> respectin
We're planning to use this for a couple of new feature where we need
to provide additional parameters to execbuf.
v2: Check for invalid flags in execbuffer2 (Lionel)
v3: Rename I915_EXEC_EXT -> I915_EXEC_USE_EXTENSIONS (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson (v1)
---
On 8/22/2019 10:19 PM, Souza, Jose wrote:
On Thu, 2019-08-22 at 21:37 +0530, Gupta, Anshuman wrote:
On 8/22/2019 1:36 AM, Souza, Jose wrote:
On Wed, 2019-08-21 at 10:06 +0530, Anshuman Gupta wrote:
On 2019-08-20 at 15:33:23 -0700, José Roberto de Souza wrote:
PSR registers are a mess, some
On Thu, Aug 22, 2019 at 05:46:55PM -0700, Madhumitha Tolakanahalli Pradeep
wrote:
> DSC was not supported on Pipe A for previous platforms. Tigerlake onwards,
> all the pipes support DSC. Hence, the DSC and FEC restriction on
> Pipe A needs to be removed.
>
> v2: Changes in the logic around remov
Hi,
Just fiddling with enums to avoid default 0 values as recommended by
Jason.
Cheers,
Lionel Landwerlin (2):
drm/i915: introduce a mechanism to extend execbuf2
drm/i915: add syncobj timeline support
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 346 +++---
drivers/gpu/drm/i
On Wed, 2019-08-21 at 23:41 +0100, Chris Wilson wrote:
> Quoting Stuart Summers (2019-08-21 00:05:43)
> > Add a new function to copy subslices for a specified slice
> > between intel_sseu structures for the purpose of determining
> > power-gate status.
>
> And ss_stride happens to be one in all ca
Quoting Xiaolin Zhang (2019-08-23 07:57:31)
> vgpu ppgtt notification was split into 2 steps, the first step is to
> update PVINFO's pdp register and then write PVINFO's g2v_notify register
> with action code to tirgger ppgtt notification to GVT side.
>
> currently these steps were not atomic oper
== Series Details ==
Series: drm/i915/dp: Fix DSC enable code to use cpu_transcoder instead of
encoder->type
URL : https://patchwork.freedesktop.org/series/65625/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6766_full -> Patchwork_14141_full
=
On 8/22/2019 9:50 PM, Gupta, Anshuman wrote:
Verified from B.Specs:7723 and B.Spec:8041
On 8/16/2019 1:34 PM, Lucas De Marchi wrote:
From: José Roberto de Souza
From BDW+ the PSR registers moved from DDIA to transcoder, so any port
with a eDP panel connected can have PSR, so lets remove th
== Series Details ==
Series: drm/i915: timeline semaphore support (rev5)
URL : https://patchwork.freedesktop.org/series/61032/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6772 -> Patchwork_14154
Summary
---
**SUCCE
There is a difference in BSpec's and the driver's designation of DDI
ports. BSpec uses the following names:
- before GEN11:
BSpec/driver:
port A/B/C/D etc
- GEN11:
BSpec/driver:
port A-F.
- GEN12:
BSpec:
port A/B/C for combo PHY ports
port TC1-6 etc for Type C
On 08/23/2019 03:58 PM, Chris Wilson wrote:
> Quoting Xiaolin Zhang (2019-08-23 07:57:31)
>> vgpu ppgtt notification was split into 2 steps, the first step is to
>> update PVINFO's pdp register and then write PVINFO's g2v_notify register
>> with action code to tirgger ppgtt notification to GVT side
Thanks for the patch and the review, pushed to dinq
Regards
Manasi
On Tue, Aug 20, 2019 at 03:30:59PM -0700, Anusha Srivatsa wrote:
> DSC engine on ICL supports only 8 and 10 BPC as the input
> BPC. But DSC engine in TGL supports 8, 10 and 12 BPC.
> Add 12 BPC support for DSC while calculating co
Hi Dave and Daniel,
(atempt v2:
for some reason my dim didn't recognized the path apparently
)
Here goes the final pull request targeting 5.4.
It's important to highlight that we got a conflict on a backmerge yesterday
which had already been solved on linux-next with a fix up patch:
From: Steph
On 8/16/2019 1:34 PM, Lucas De Marchi wrote:
From: José Roberto de Souza
TGL PSR2 HW supports a bigger resolution, so lets add it
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_psr.c |
Verified with respect two B.Spces: 50434 and eDP specs DPCD – Sink
"Device PSR Configuration Field" 00170h address.
Looks Good to me.
On 8/16/2019 1:34 PM, Lucas De Marchi wrote:
From: José Roberto de Souza
According to BSpc if link standby is set on TGL+, PSR will not be
enabled. Vendors sh
On Thu, 22 Aug 2019, Ramalingam C wrote:
> Handled the need for exposing enum port to mei_hdcp driver, by
> converting the port into ddi index as per ME FW.
>
> Hence enum port definition moved into I915 driver itself.
For future reference, please consider using the imperative style in the
commit
From: Ville Syrjälä
Reogranize the HDMI deep color state computation to just
loop over possible bpc values. Avoids having to maintain
so many variants of the clock etc.
The current code also looks confused w.r.t. port_clock vs.
bw_constrained. It would happily update port_clock for
deep color bu
Thanks for the patch and review, pushed to dinq
Manasi
On Wed, Aug 21, 2019 at 02:59:50PM -0700, Manasi Navare wrote:
> This patch fixes the intel_configure_pps_for_dsc_encoder() function to use
> cpu_transcoder instead of encoder->type to select the correct DSC registers
> that was wrongly used
Ville/Maarten/Daniel,
Could you please review this? There is no functional changes
just moving the disable part to a separate hook
Manasi
On Thu, Jun 27, 2019 at 03:57:36PM -0700, Manasi Navare wrote:
> Create a new hook commit_modeset_disables() consistent with the naming
> in drm atomic helpe
Hi Dave and Daniel,
Here goes the final pull request targeting 5.4.
It's important to highlight that we got a conflict on a backmerge yesterday
which had already been solved on linux-next with a fix up patch:
From: Stephen Rothwell
Date: Wed, 14 Aug 2019 12:48:39 +1000
Subject: [PATCH] drm: fix
Hi,
On 8/22/2019 12:13 AM, Chris Wilson wrote:
Quoting Animesh Manna (2019-08-21 07:32:30)
Batch buffer will be created through dsb-reg-write function which can have
single/multiple request based on usecase and once the buffer is ready
commit function will trigger the execution of the batch bu
On 21/08/2019 21:03, Chris Wilson wrote:
The test assumes that the dmabuf for the batch buffer has no exclusive
fence. This is only true for the batch as it executes on the GPU; prior
to that we may be in the process of moving it into memory and the
ppGTT which cause the batch to carry an exclusi
On 8/22/2019 1:36 AM, Souza, Jose wrote:
On Wed, 2019-08-21 at 10:06 +0530, Anshuman Gupta wrote:
On 2019-08-20 at 15:33:23 -0700, José Roberto de Souza wrote:
PSR registers are a mess, some have the full address while others
just
have the additional offset from psr_mmio_base.
For BDW+ psr_m
We're planning to use this for a couple of new feature where we need
to provide additional parameters to execbuf.
v2: Check for invalid flags in execbuffer2 (Lionel)
v3: Rename I915_EXEC_EXT -> I915_EXEC_USE_EXTENSIONS (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson (v1)
---
Hi,
Just fiddling with enums to avoid default 0 values as recommended by
Jason.
Cheers,
Lionel Landwerlin (2):
drm/i915: introduce a mechanism to extend execbuf2
drm/i915: add syncobj timeline support
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 346 +++---
drivers/gpu/drm/i
On 8/22/2019 6:53 PM, Jani Nikula wrote:
On Wed, 21 Aug 2019, Animesh Manna wrote:
Gamma lut programming can be programmed using DSB
where bulk register programming can be done using indexed
register write which takes number of data and the mmio offset
to be written.
No. Please stick to addi
On 22/08/2019 12:43, Joonas Lahtinen wrote:
Quoting Lucas De Marchi (2019-08-16 11:04:57)
From: Lionel Landwerlin
The way our hardware is designed doesn't seem to let us use the
MI_RECORD_PERF_COUNT command without setting up a circular buffer.
In the case where the user didn't request OA rep
Introduces a new parameters to execbuf so that we can specify syncobj
handles as well as timeline points.
v2: Reuse i915_user_extension_fn
v3: Check that the chained extension is only present once (Chris)
v4: Check that dma_fence_chain_find_seqno returns a non NULL fence (Lionel)
v5: Use BIT_UL
Sadly lockdep records when the irqs are re-enabled and then marks up the
fake lock as being irq-unsafe. Our hand is forced and so we must mark up
the entire fake lock critical section as irq-off.
Hopefully this is the last tweak required!
Fixes: d67739268cf0 ("drm/i915/gt: Mark up the nested engi
Chris Wilson writes:
> Quoting Chris Wilson (2019-08-21 15:23:36)
>> Since we now run process_csb() outside of the engine->active.lock, we
>> can process a CS-event immediately upon our ELSP write. As we currently
>> inspect the pending queue *after* the ELSP write, there is an
>> opportunity for
On Thu, Aug 22, 2019 at 7:20 AM Manasi Navare wrote:
>
> This patch fixes the intel_configure_pps_for_dsc_encoder() function to use
> cpu_transcoder instead of encoder->type to select the correct DSC registers
> that was wrongly used in the original patch for one DSC register isntance.
>
> Fixes:
On Fri, Aug 23, 2019 at 1:13 AM Lionel Landwerlin
wrote:
>
> On 22/08/2019 12:43, Joonas Lahtinen wrote:
> > Quoting Lucas De Marchi (2019-08-16 11:04:57)
> >> From: Lionel Landwerlin
> >>
> >> The way our hardware is designed doesn't seem to let us use the
> >> MI_RECORD_PERF_COUNT command witho
On 23/08/2019 10:20, Lucas De Marchi wrote:
From: Michel Thierry
Compared to Icelake, Tigerlake's MAX_CONTEXT_HW_ID is smaller by one, but
since we just use the upper 32 bits of the lrc_desc, it's guaranteed OA
will use the correct one.
Cc: Lionel Landwerlin
Signed-off-by: Michel Thierry
Sig
In order for the Braswell top-level PD to remain the same from the time
of request construction to its submission onto HW, as we may be
asynchronously rewriting the page tables (thus changing the expected
register state after having already stored the old addresses in the
request), the top level PD
On Fri, Aug 23, 2019 at 1:14 AM Andrew Morton wrote:
>
> On Tue, 20 Aug 2019 22:24:40 +0200 Daniel Vetter wrote:
>
> > Hi Peter,
> >
> > Iirc you've been involved at least somewhat in discussing this. -mm folks
> > are a bit undecided whether these new non_block semantics are a good idea.
> > Mic
Hi Daniel, Dave,
Here is what should be the final drm-misc-next PR for 5.4.
Thanks!
Maxime
drm-misc-next-2019-08-23:
drm-misc-next for 5.4:
UAPI Changes:
Cross-subsystem Changes:
Core Changes:
- dma-buf: dma-fence selftests
Driver Changes:
- kirin: Various cleanups and reworks
- komeda
Quoting Zhang, Xiaolin (2019-08-23 09:07:01)
> On 08/23/2019 03:58 PM, Chris Wilson wrote:
> > Quoting Xiaolin Zhang (2019-08-23 07:57:31)
> >> vgpu ppgtt notification was split into 2 steps, the first step is to
> >> update PVINFO's pdp register and then write PVINFO's g2v_notify register
> >> wit
== Series Details ==
Series: iommu/vt-d: Fix IOMMU field not populated on device hot re-plug
URL : https://patchwork.freedesktop.org/series/65627/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6766_full -> Patchwork_14142_full
==
On Tue, Aug 20, 2019 at 10:24:40PM +0200, Daniel Vetter wrote:
> On Tue, Aug 20, 2019 at 10:19:01AM +0200, Daniel Vetter wrote:
> > In some special cases we must not block, but there's not a
> > spinlock, preempt-off, irqs-off or similar critical section already
> > that arms the might_sleep() debu
On Tue, Aug 20, 2019 at 10:19:50AM +0200, Daniel Vetter wrote:
> Necessary to annotate functions where we might acquire a
> mutex_lock_nested() or similar. Needed by i915.
>
> Signed-off-by: Daniel Vetter
> Cc: Peter Zijlstra
> Cc: Ingo Molnar
> Cc: Will Deacon
> Cc: linux-ker...@vger.kernel.o
On Tue, Aug 20, 2019 at 10:19:51AM +0200, Daniel Vetter wrote:
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> b/drivers/gpu/drm/i915/gem/i915_gem_object.h
> index a0b1fa8a3224..b3fd6aac93bc 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h
> +++ b/drivers/gpu/drm/i915/gem/i915
On Thu, Aug 22, 2019 at 5:46 PM Madhumitha Tolakanahalli Pradeep
wrote:
>
> DSC was not supported on Pipe A for previous platforms. Tigerlake onwards,
> all the pipes support DSC. Hence, the DSC and FEC restriction on
> Pipe A needs to be removed.
>
> v2: Changes in the logic around removing the r
From: José Roberto de Souza
On TGL the blending of all the streams have moved from DDI to
transcoder, so now every transcoder working over the same MST port must
send its stream to a master transcoder and master will send to DDI
respecting the time slots.
So here it is picking the lowest pipe/tr
From: José Roberto de Souza
It was enabling and checking PSR interruptions in every transcoder
while it should keep the interruptions on the non-used transcoders
masked.
This also already prepares for future when more than one PSR instance
will be allowed.
Cc: Dhinakaran Pandiyan
Signed-off-by
From: Dhinakaran Pandiyan
Gen-12 decompression is supported with Y-tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Gen-12 display decompression is incompatible with buffers
compressed by earlier GPUs, so make use of a new modif
From: José Roberto de Souza
Same as for_each_oldnew_intel_crtc_in_state() but iterates in reverse
order.
v2: Fix additional blank line
Cc: Rodrigo Vivi
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
Reviewed-by: Mika Kahola
---
drivers/gpu/drm/i915/d
From: Michel Thierry
Workaround no longer needed (plus L3_LRA_1_GPGPU doesn't exist).
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Signed-off-by: Michel Thierry
Signed-off-by: Lucas De Marchi
Reviewed-by: Stuart Summers
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
1 file changed, 1 i
From: José Roberto de Souza
Now that is allowed to have PSR enabled in any port from BDW+, lets
guard intel_psr_init_dpcd() against multiple eDP panels and warn about
it.
For now we will keep just one instance of PSR.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Sou
Gen 12 onwards moves the DP_TP_* registers to be transcoder-based rather
than port-based. This add the new register address and changes the
functions that are used with DDI on gen 12 to use the new registers. On
MST the master transcoder is the one to be used.
Cc: Rodrigo Vivi
Cc: Ville Syrjälä
From: Michel Thierry
HCP/MFX power gating is disabled by default, turn it on for the vd units
available. User space will also issue a MI_FORCE_WAKEUP properly to
wake up proper subwell.
During driver load, init_clock_gating happens after device_info_init_mmio
read the vdbox disable fuse register
From: Dhinakaran Pandiyan
Yf tiling was removed in gen-12, make the necessary to changes to not
expose the modifier to user space. Gen-12 display also is incompatible with
pre-gen12 Y-tiled compression, so do not expose
I915_FORMAT_MOD_Y_TILED_CCS.
Bspec: 29650
Cc: Daniel Vetter
Cc: Ville Syrj
From: Michel Thierry
Gen12 has subtle changes in the reg state context offsets (some fields
are gone, some are in a different location), compared to previous Gens.
The simplest approach seems to be keeping Gen12 (and future platform)
changes apart from the previous gens, while keeping the regist
From: José Roberto de Souza
From BDW+ the PSR registers moved from DDIA to transcoder, so any port
with a eDP panel connected can have PSR, so lets remove this
limitation.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
Reviewed-by
From: Michel Thierry
Compared to Icelake, Tigerlake's MAX_CONTEXT_HW_ID is smaller by one, but
since we just use the upper 32 bits of the lrc_desc, it's guaranteed OA
will use the correct one.
Cc: Lionel Landwerlin
Signed-off-by: Michel Thierry
Signed-off-by: Lucas De Marchi
---
drivers/gpu/
From: Dhinakaran Pandiyan
Gen-12 has a new compression format, add a new modifier for userspace to
indicate that.
Cc: Ville Syrjälä
Cc: Daniel Vetter
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Lucas De Marchi
---
include/uapi/drm/drm_fourcc.h | 10 ++
1 file changed, 10 inser
From: Dhinakaran Pandiyan
Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.
Cc: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Lucas De Marchi
---
in
v3 of https://patchwork.freedesktop.org/series/65290/
Note that some patches were handled outside of the "batch series for
Tiger Lake". Compared to v2 several patches were merged. Anothe great
portion received comments and reviews. Unfortunately some people
commented/reviewed the wrong revision of
The bspec was recently updated with these new cdclk values for ICL, EHL,
and TGL.
Bspec: 20598
Bspec: 49201
Cc: José Roberto de Souza
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff
From: Michel Thierry
GAM registers located in the 0x4xxx range have been relocated to 0xCxxx;
this is to make space for global MOCS registers.
v2: Rename register and bitfield to its new name (suggested by Mika)
HSD: 399379
Cc: Daniele Ceraolo Spurio
Signed-off-by: Michel Thierry
Reviewed-by:
From: José Roberto de Souza
TGL PSR2 HW supports a bigger resolution, so lets add it
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_psr.c | 5 -
1 file changed, 4 insertions(+), 1 deleti
From: José Roberto de Souza
For older gens PSR IIR and IMR had a fixed address that was not
relative to anything, but from TGL those registers moved to each
transcoder offset.
So here adding a new macro and a new PSR irq handler with the
transcoder parameter.
Cc: Dhinakaran Pandiyan
Cc: Rodrig
From: José Roberto de Souza
Disable CRTC/pipes in reverse order because some features (MST in
TGL+) requires master and slave relationship between pipes, so it
should always pick the lowest pipe as master as it will be enabled
first and disable in the reverse order so the master will be the last
From: Dhinakaran Pandiyan
Gen-12 display can decompress surfaces compressed by the media engine.
Detect the modifier corresponding to media compression to enable
decompression for YUV and ARGB packed formats. A new modifier is added
so that the driver can distinguish between media and render comp
From: José Roberto de Souza
The same macro as for_each_new_connector_in_state() but it uses
intel/i915 types instead of the drm ones.
Signed-off-by: José Roberto de Souza
Reviewed-by: Mika Kahola
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.h | 8
1
From: José Roberto de Souza
On TGL some registers moved from DDI to transcoder and the
DisplayPort training sequence has a separate BSpec page.
I started adding 'ifs' to the original intel_ddi_pre_enable_dp() but
it was becoming really hard to follow, so a new and cleaner function
for TGL was ad
From: José Roberto de Souza
This fix unclaimed access warnings:
[ 245.525788] [ cut here ]
[ 245.525884] Unclaimed read from register 0x62900
[ 245.526154] WARNING: CPU: 0 PID: 1234 at
drivers/gpu/drm/i915/intel_uncore.c:1100 __unclaimed_reg_debug+0x40/0x50 [i915]
[
From: José Roberto de Souza
According to BSpc if link standby is set on TGL+, PSR will not be
enabled. Vendors should not use panels that requires link standby and
even if they do, panel should assert a PSR error that will cause PSR to
be disabled.
BSpec: 50434
Signed-off-by: José Roberto de Sou
== Series Details ==
Series: drm/i915: to make vgpu ppgtt notificaiton as atomic operation (rev2)
URL : https://patchwork.freedesktop.org/series/65669/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4b318d67e6f0 drm/i915: to make vgpu ppgtt notificaiton as atomic operation
-:28:
In order for the Braswell top-level PD to remain the same from the time
of request construction to its submission onto HW, as we may be
asynchronously rewriting the page tables (thus changing the expected
register state after having already stored the old addresses in the
request), the top level PD
== Series Details ==
Series: series starting with drm/i915: Switch obj->mm.lock lockdep annotations
on its head (rev2)
URL : https://patchwork.freedesktop.org/series/65467/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6766_full -> Patchwork_14143_full
===
== Series Details ==
Series: drm/i915: to make vgpu ppgtt notificaiton as atomic operation (rev2)
URL : https://patchwork.freedesktop.org/series/65669/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6774 -> Patchwork_14155
S
This patch adds a line with the port name to connectors in
debugfs/i915_debug_info. If the port is Type-C, the Type-C port number is
printed too.
Signed-off-by: Simon Ser
Cc: Imre Deak
Cc: Manasi Navare
Reviewed-by: Imre Deak
---
Resending v2 to the correct mailing list.
drivers/gpu/drm/i91
Support for HDR10 video was introduced in DisplayPort 1.4.
On GLK+ platform, in order to use DisplayPort HDR10, we need to support
BT.2020 colorimetry and HDR Static metadata.
It implements the CTA-861-G standard for transport of static HDR metadata.
It enables writing of HDR metadata infoframe SDP
It attaches HDR metadata property to DP connector on GLK+.
It enables HDR metadata infoframe sdp on GLK+ to be used to send
HDR metadata to DP sink.
v2: Minor style fix
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/display/intel_dp.c | 5 +
1 file changed, 5 insertions(+)
diff --
When BT.2020 Colorimetry output is used for DP, we should program BT.2020
Colorimetry to MSA and VSC SDP. It adds output_colorspace to
intel_crtc_state struct as a place holder of pipe's output colorspace.
In order to distinguish needed colorimetry for VSC SDP, it adds
intel_dp_needs_vsc_colorimetr
In order to use colorspace property to Display Port connectors, it extends
DRM_MODE_CONNECTOR_DisplayPort connector_type on
drm_mode_create_colorspace_property function.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/drm_connector.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
d
It attaches the colorspace connector property to a DisplayPort connector.
Based on colorspace change, modeset will be triggered to switch to a new
colorspace.
Based on colorspace property value create a VSC SDP packet with appropriate
colorspace. This would help to enable wider color gamut like BT
Function intel_dp_setup_hdr_metadata_infoframe_sdp handles Infoframe SDP
header and data block setup for HDR Static Metadata. It enables writing of
HDR metadata infoframe SDP to panel. Support for HDR video was introduced
in DisplayPort 1.4. It implements the CTA-861-G standard for transport of
sta
It refactors and renames a function which handled vsc sdp header and data
block setup for supporting colorimetry format.
Function intel_dp_setup_vsc_sdp handles vsc sdp header and data block
setup for pixel encoding / colorimetry format.
In order to use colorspace information of a connector, it add
In order for the Braswell top-level PD to remain the same from the time
of request construction to its submission onto HW, as we may be
asynchronously rewriting the page tables (thus changing the expected
register state after having already stored the old addresses in the
request), the top level PD
Sadly lockdep records when the irqs are re-enabled and then marks up the
fake lock as being irq-unsafe. Our hand is forced and so we must mark up
the entire fake lock critical section as irq-off.
Hopefully this is the last tweak required!
v2: Not quite, we need to mark the timeline spinlock as ir
There is a difference in BSpec's and the driver's designation of DDI
ports. BSpec uses the following names:
- before GEN11:
BSpec/driver:
port A/B/C/D etc
- GEN11:
BSpec/driver:
port A-F
- GEN12:
BSpec:
port A/B/C for combo PHY ports
port TC1-6 for Type C PHY p
== Series Details ==
Series: drm/i915: timeline semaphore support
URL : https://patchwork.freedesktop.org/series/65681/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1ccd4987e97d drm/i915: introduce a mechanism to extend execbuf2
-:141: CHECK:SPACING: spaces preferred around th
On Wed, 21 Aug 2019, Manasi Navare wrote:
> On Wed, Aug 21, 2019 at 03:32:12PM +0200, Maarten Lankhorst wrote:
>> There was a integer wraparound when mode_clock became too high,
>> and we didn't correct for the FEC overhead factor when dividing,
>> also the calculations would break at HBR3.
>
> Bu
On Wed, 21 Aug 2019, Maarten Lankhorst
wrote:
> Dump the DSC and FEC in i915_dpcd as well. This is useful when
> debugging the link caps.
I thought we were going to get rid of this particular debugfs file
altogether ages ago. You can dump the DPCD using
CONFIG_DRM_DP_AUX_CHARDEV=y and dd on /dev
== Series Details ==
Series: drm/i915: Enable HDCP 1.4 and 2.2 on Gen12+ (rev7)
URL : https://patchwork.freedesktop.org/series/63432/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6766_full -> Patchwork_14144_full
Summary
-
On Wed, 21 Aug 2019, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Use hweight8() instead of hweight32() for 8bit masks. Doesn't actually
> matter for us since the arch code will go for hweight32() anyway, but
> maybe we stil want to do this for documentation purposes?
hweight32 is preparing fo
== Series Details ==
Series: drm/i915: timeline semaphore support
URL : https://patchwork.freedesktop.org/series/65681/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6775 -> Patchwork_14156
Summary
---
**SUCCESS**
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