== Series Details ==
Series: DSB enablement. (rev2)
URL : https://patchwork.freedesktop.org/series/63013/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e65049952809 drm/i915/dsb: feature flag added for display state buffer.
ff9965b61f73 drm/i915/dsb: DSB context creation.
-:43:
== Series Details ==
Series: DSB enablement. (rev2)
URL : https://patchwork.freedesktop.org/series/63013/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/dsb: feature flag added for display state buffer.
Okay!
_
== Series Details ==
Series: DSB enablement. (rev2)
URL : https://patchwork.freedesktop.org/series/63013/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6750 -> Patchwork_14117
Summary
---
**SUCCESS**
No regression
I think this patch needs to be landed after
https://patchwork.freedesktop.org/patch/319815/?series=60916&rev=10
As recommended by Joonas.
It should also bump the revision number of the perf API so that the
application can detect this feature is available.
Thanks,
-Lionel
On 16/08/2019 10:04
tree: git://anongit.freedesktop.org/drm-intel for-linux-next
head: 64b95df91f44837f961321a6c555409885ca59c4
commit: 64b95df91f44837f961321a6c555409885ca59c4 [3/3] drm/i915: Assume
exclusive access to objects inside resume
config: x86_64-randconfig-f002-201933 (attached as .config)
compiler: gc
Reviewed-by: Tony Ye
Regards, --Tony
On 8/21/2019 4:54 AM, Lucas De Marchi wrote:
On Sat, Aug 17, 2019 at 02:38:43AM -0700, Lucas De Marchi wrote:
From: Michel Thierry
HCP/MFX power gating is disabled by default, turn it on for the vd units
available. User space will also issue a MI_FORCE_W
== Series Details ==
Series: series starting with [1/5] drm/i915/dp: stylistic cleanup around
hdcp2_msg_data
URL : https://patchwork.freedesktop.org/series/65481/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6749_full -> Patchwork_14103_full
=
On Wed, Aug 21, 2019 at 9:33 AM Jason Gunthorpe wrote:
>
> On Tue, Aug 20, 2019 at 05:18:10PM +0200, Daniel Vetter wrote:
> > > > diff --git a/mm/mmu_notifier.c b/mm/mmu_notifier.c
> > > > index 538d3bb87f9b..856636d06ee0 100644
> > > > +++ b/mm/mmu_notifier.c
> > > > @@ -181,7 +181,13 @@ int __mm
We need asm/smp.h for wbinvd_on_all_cpus()
Reported-by: kbuild-...@01.org
Signed-off-by: Chris Wilson
Cc: Matthew Auld
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c9a
== Series Details ==
Series: drm/i915/gtt: Include asm/smp.h
URL : https://patchwork.freedesktop.org/series/65532/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8b9d243b31ad drm/i915/gtt: Include asm/smp.h
-:20: WARNING:INCLUDE_LINUX: Use #include instead of
#20: FILE: driver
Quoting Patchwork (2019-08-21 11:01:05)
> == Series Details ==
>
> Series: drm/i915/gtt: Include asm/smp.h
> URL : https://patchwork.freedesktop.org/series/65532/
> State : warning
>
> == Summary ==
>
> $ dim checkpatch origin/drm-tip
> 8b9d243b31ad drm/i915/gtt: Include asm/smp.h
> -:20: WARN
On 21/08/2019 10:39, Chris Wilson wrote:
We need asm/smp.h for wbinvd_on_all_cpus()
Reported-by: kbuild-...@01.org
Signed-off-by: Chris Wilson
Cc: Matthew Auld
Reviewed-by: Matthew Auld
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
htt
== Series Details ==
Series: drm/i915: Do not create a new max_bpc prop for MST connectors
URL : https://patchwork.freedesktop.org/series/65493/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6749_full -> Patchwork_14108_full
== Series Details ==
Series: drm/i915/gtt: Include asm/smp.h
URL : https://patchwork.freedesktop.org/series/65532/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6752 -> Patchwork_14118
Summary
---
**SUCCESS**
No r
On Tue, 20 Aug 2019, Ramalingam C wrote:
> On 2019-08-20 at 16:40:15 +0300, Jani Nikula wrote:
>> Split struct declaration and array definition. Fix indents and
>> whitespace. No functional changes.
>>
>
> Reviewed-by: Ramalingam C
Thanks, pushed the lot.
BR,
Jani.
>
> -Ram
>> Cc: Ramalingam
On 20/08/2019 14:52, Chris Wilson wrote:
Make sure that we wait for the vma to be pinned prior to telling the GPU
to fill the pages through that vma.
However, since our async operations fight over obj->resv->excl_fence we
must manually order them. This makes it much more fragile, and gives an
ou
Quoting Matthew Auld (2019-08-21 12:00:07)
> On 20/08/2019 14:52, Chris Wilson wrote:
> > Make sure that we wait for the vma to be pinned prior to telling the GPU
> > to fill the pages through that vma.
> >
> > However, since our async operations fight over obj->resv->excl_fence we
> > must manual
On Sat, 2019-08-17 at 02:38 -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza
>
> Same as for_each_oldnew_intel_crtc_in_state() but iterates in reverse
> order.
>
> v2: Fix additional blank line
>
> Cc: Rodrigo Vivi
> Cc: Ville Syrjälä
> Signed-off-by: José Roberto de Souza
> Signe
On Sat, 2019-08-17 at 02:38 -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza
>
> Disable CRTC/pipes in reverse order because some features (MST in
> TGL+) requires master and slave relationship between pipes, so it
> should always pick the lowest pipe as master as it will be enabled
>
On Tue, 20 Aug 2019 at 15:28, Chris Wilson wrote:
>
> When under severe stress for GTT mappable space, the LRU eviction model
> falls off a cliff. We spend all our time scanning the much large
> non-mappable vma searching for something within the mappable zone we can
> evict. Turn this on its head
On Tue, 20 Aug 2019 at 15:28, Chris Wilson wrote:
>
> The premise here is to simply avoiding having to acquire the vm->mutex
> inside vma create/destroy to update the vm->unbound_lists, to avoid some
> nasty lock recursions later.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
___
When under severe stress for GTT mappable space, the LRU eviction model
falls off a cliff. We spend all our time scanning the much larger
non-mappable area searching for something within the mappable zone we can
evict. Turn this on its head by only using the full vma for the object if
it is already
The premise here is to simply avoiding having to acquire the vm->mutex
inside vma create/destroy to update the vm->unbound_lists, to avoid some
nasty lock recursions later.
Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_stolen.c| 2 +-
drivers/g
On Fri, 16 Aug 2019, Nathaniel Russell wrote:
> Here is the file you requested with the debug information
Please attach it to the bug you've hopefully created.
BR,
Jani.
--
Jani Nikula, Intel Open Source Graphics Center
___
Intel-gfx mailing list
Int
On Wed, Aug 21, 2019 at 04:33:58PM +1000, Ben Skeggs wrote:
> On Wed, 14 Aug 2019 at 20:14, Gerd Hoffmann wrote:
> >
> > Hi,
> >
> > > > Changing the order doesn't look hard. Patch attached (untested, have no
> > > > test hardware). But maybe I missed some detail ...
> > >
> > > I came up with
== Series Details ==
Series: drm/i915: disable set/get_tiling ioctl on gen12+ (rev2)
URL : https://patchwork.freedesktop.org/series/65495/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6750_full -> Patchwork_14110_full
Summ
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Replace PIN_NONFAULT with calls
to PIN_NOEVICT
URL : https://patchwork.freedesktop.org/series/65537/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6753 -> Patchwork_14119
When under severe stress for GTT mappable space, the LRU eviction model
falls off a cliff. We spend all our time scanning the much larger
non-mappable area searching for something within the mappable zone we can
evict. Turn this on its head by only using the full vma for the object if
it is already
On 17/08/2019 11:38, Lucas De Marchi wrote:
From: Michel Thierry
Compared to Icelake, Tigerlake's MAX_CONTEXT_HW_ID is smaller by one, but
since we just use the upper 32 bits of the lrc_desc, it's guaranteed OA
will use the correct one.
Cc: Lionel Landwerlin
Signed-off-by: Michel Thierry
Sig
== Series Details ==
Series: drm/i915: Replace PIN_NONFAULT with calls to PIN_NOEVICT (rev3)
URL : https://patchwork.freedesktop.org/series/65222/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6754 -> Patchwork_14120
Summar
Hi all,
Just a rebase and a change added then reversed that puts us right back
to v3.
Cheers,
Lionel Landwerlin (2):
drm/i915: introduce a mechanism to extend execbuf2
drm/i915: add syncobj timeline support
.../gpu/drm/i915/gem/i915_gem_execbuffer.c| 346 +++---
drivers/gpu
We're planning to use this for a couple of new feature where we need
to provide additional parameters to execbuf.
v2: Check for invalid flags in execbuffer2 (Lionel)
v3: Rename I915_EXEC_EXT -> I915_EXEC_USE_EXTENSIONS (Chris)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Chris Wilson (v1)
---
Introduces a new parameters to execbuf so that we can specify syncobj
handles as well as timeline points.
v2: Reuse i915_user_extension_fn
v3: Check that the chained extension is only present once (Chris)
v4: Check that dma_fence_chain_find_seqno returns a non NULL fence (Lionel)
v5: Use BIT_UL
On Sat, 2019-08-17 at 02:38 -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza
>
> The same macro as for_each_new_connector_in_state() but it uses
> intel/i915 types instead of the drm ones.
>
> Signed-off-by: José Roberto de Souza
Reviewed-by: Mika Kahola
> ---
> drivers/gpu/drm/i
== Series Details ==
Series: series starting with [v8,1/3] drm/i915/psr: Make PSR registers relative
to transcoders
URL : https://patchwork.freedesktop.org/series/65507/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6750_full -> Patchwork_14112_full
==
On Wed, 2019-08-21 at 11:22 +, Kahola, Mika wrote:
> On Sat, 2019-08-17 at 02:38 -0700, Lucas De Marchi wrote:
> > From: José Roberto de Souza
> >
> > Same as for_each_oldnew_intel_crtc_in_state() but iterates in
> > reverse
> > order.
> >
> > v2: Fix additional blank line
> >
> > Cc: Rodri
There was a integer wraparound when mode_clock became too high,
and we didn't correct for the FEC overhead factor when dividing,
also the calculations would break at HBR3.
As a result our calculated bpp was way too high, and the link width
bpp limitation never came into effect.
Print out the resu
We are still looking at drm_crtc_state in a few places, convert those
to use intel_crtc_state instead. Look at uapi/hw where appropriate.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 22 ++--
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2
Some of the patches that support the big joiner configuration, without
actually enabling anything bigjoiner specific yet.
Big Joiner requires us to enable an additional pipe, which drives the
same port. The master pipe drives the left half of the display, the
slave the right half.
This is handled
We had this as an optimization to not do a plane update, but we killed
it off because there are so many reasons we may have to do a plane
update or fastset that it's best to just assume everything changed.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_atomic.c|
Instead of relying on the fourcc, use the drm fourcc helper
drm_format_info_is_yuv_semiplanar().
Signed-off-by: Maarten Lankhorst
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 10 +-
drivers/gpu/drm/i915/display/intel_display.h
We cannot switch between HQ and normal mode on GLK+, so only
add planes on platforms where it makes sense.
We could probably restrict it even more to only add when scaler
users toggles between 1 and 2, but lets just leave it for now.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/dis
Now that we separated everything into uapi and hw, it's
time to make the split definitive. Remove the union and
make a copy of the hw state on modeset and fastset.
Color blobs are copied in crtc atomic_check(), right
before color management is checked.
Signed-off-by: Maarten Lankhorst
---
drive
Even without bigjoiner I get a timeout when enabling FEC, the length of the
timeout
doesn't matter, still happens with 10s timeout.
It seems that DP-MST waits for ACT in enable_dp() so we
could postpone it in normal bringup in a similar way, just to be sure.
Signed-off-by: Maarten Lankhorst
---
This can all be done from the intel_update_crtc function. Split out the
pipe update into a separate function, just like is done for the planes.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/display/intel_display.c | 124 ---
1 file changed, 52 insertions(+), 72 deleti
Dump the DSC and FEC in i915_dpcd as well. This is useful when
debugging the link caps.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index
== Series Details ==
Series: drm/i915: timeline semaphore support (rev4)
URL : https://patchwork.freedesktop.org/series/61032/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
41f8e78e82c4 drm/i915: introduce a mechanism to extend execbuf2
-:141: CHECK:SPACING: spaces preferred ar
On Tue, Aug 20, 2019 at 01:57:44PM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 8/20/19 12:54 PM, Daniel Vetter wrote:
> > The cpu (de)tiler hw is gone, this stopped being useful. Plus it never
> > supported any of the fancy new tiling formats, which means userspace
> > also stopped using the ma
On Wed, Aug 21, 2019 at 2:47 PM Thomas Hellström (VMware)
wrote:
> On 8/21/19 2:40 PM, Thomas Hellström (VMware) wrote:
> > On 8/20/19 4:53 PM, Daniel Vetter wrote:
> >> With nouveau fixed all ttm-using drives have the correct nesting of
> >> mmap_sem vs dma_resv, and we can just lock the buffer.
On Wed, Aug 21, 2019 at 3:16 PM Thomas Hellström (VMware)
wrote:
>
> On 8/20/19 4:53 PM, Daniel Vetter wrote:
> > With nouveau fixed all ttm-using drives have the correct nesting of
> > mmap_sem vs dma_resv, and we can just lock the buffer.
> >
> > Assuming I didn't screw up anything with my audit
== Series Details ==
Series: drm/dp/dsc: Add Support for all BPCs supported by TGL (rev5)
URL : https://patchwork.freedesktop.org/series/63526/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6750_full -> Patchwork_14113_full
== Series Details ==
Series: drm/i915: timeline semaphore support (rev4)
URL : https://patchwork.freedesktop.org/series/61032/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6754 -> Patchwork_14121
Summary
---
**SUCCE
Since we now run process_csb() outside of the engine->active.lock, we
can process a CS-event immediately upon our ELSP write. As we currently
inspect the pending queue *after* the ELSP write, there is an
opportunity for a CS-event to update the pending queue before we can
read it, making ourselves
Quoting Chris Wilson (2019-08-21 15:23:36)
> Since we now run process_csb() outside of the engine->active.lock, we
> can process a CS-event immediately upon our ELSP write. As we currently
> inspect the pending queue *after* the ELSP write, there is an
> opportunity for a CS-event to update the pen
On Sat, 2019-08-17 at 02:38 -0700, Lucas De Marchi wrote:
> From: Dhinakaran Pandiyan
>
> Gen-12 has a new compression format, add a new modifier for userspace
> to
> indicate that.
>
> Cc: Ville Syrjälä
> Cc: Daniel Vetter
> Signed-off-by: Dhinakaran Pandiyan
> Signed-off-by: Lucas De Marchi
On Sat, 2019-08-17 at 02:39 -0700, Lucas De Marchi wrote:
> From: Dhinakaran Pandiyan
>
> Gen-12 display can decompress surfaces compressed by the media
> engine.
> Detect the modifier corresponding to media compression to enable
> decompression for YUV and ARGB packed formats. A new modifier is
On Sat, 2019-08-17 at 02:39 -0700, Lucas De Marchi wrote:
> From: Dhinakaran Pandiyan
>
> Gen-12 display can decompress surfaces compressed by the media
> engine, add
> a new modifier as the driver needs to know the surface was compressed
> by
> the media or render engine.
>
> Cc: Ville Syrjälä
== Series Details ==
Series: drm/i915: Bigjoiner preparations.
URL : https://patchwork.freedesktop.org/series/65543/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
bb9674943922 drm/i915/dp: Fix dsc bpp calculations.
0e2d405f7bbf drm/i915: Prepare to split crtc state in uapi and
On Sat, 2019-08-17 at 02:38 -0700, Lucas De Marchi wrote:
> From: Daniele Ceraolo Spurio
>
> Like Gen11, Gen12 has 11 available bits for the ctx id field.
> However,
> the last value (0x7FF) is reserved to indicate engine idle, so we
> need to reduce the maximum number of contexts by 1 compared t
On Wed, Aug 21, 2019 at 4:30 PM Thomas Hellström (VMware)
wrote:
>
> On 8/21/19 4:10 PM, Daniel Vetter wrote:
> > On Wed, Aug 21, 2019 at 3:16 PM Thomas Hellström (VMware)
> > wrote:
> >> On 8/20/19 4:53 PM, Daniel Vetter wrote:
> >>> With nouveau fixed all ttm-using drives have the correct nesti
On Wed, Aug 21, 2019 at 4:27 PM Thomas Hellström (VMware)
wrote:
> On 8/21/19 4:09 PM, Daniel Vetter wrote:
> > On Wed, Aug 21, 2019 at 2:47 PM Thomas Hellström (VMware)
> > wrote:
> >> On 8/21/19 2:40 PM, Thomas Hellström (VMware) wrote:
> >>> On 8/20/19 4:53 PM, Daniel Vetter wrote:
> With
On Sat, Aug 17, 2019 at 02:38:28AM -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza
>
> According to PSR2_CTL definition in BSpec there is only one instance of
> PSR2_CTL. Platforms gen < 12 with EDP transcoder only support PSR2 on
> TRANSCODER_EDP while on TGL PSR2 is only supported b
== Series Details ==
Series: drm/i915: Bigjoiner preparations.
URL : https://patchwork.freedesktop.org/series/65543/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6755 -> Patchwork_14122
Summary
---
**FAILURE**
Se
On 8/21/19 1:49 AM, Stephen Rothwell wrote:
> Hi all,
>
> Changes since 20190820:
>
on x86_64:
../drivers/gpu/drm/i915/i915_gem_gtt.c: In function ‘ggtt_restore_mappings’:
../drivers/gpu/drm/i915/i915_gem_gtt.c::3: error: implicit declaration of
function ‘wbinvd_on_all_cpus’; did you mean
Am 21.08.19 um 16:47 schrieb Daniel Vetter:
> On Wed, Aug 21, 2019 at 4:27 PM Thomas Hellström (VMware)
> wrote:
>> On 8/21/19 4:09 PM, Daniel Vetter wrote:
>>> On Wed, Aug 21, 2019 at 2:47 PM Thomas Hellström (VMware)
>>> wrote:
On 8/21/19 2:40 PM, Thomas Hellström (VMware) wrote:
> On
On Wed, Aug 21, 2019 at 5:03 PM Thomas Hellström (VMware)
wrote:
> On 8/21/19 4:47 PM, Daniel Vetter wrote:
> > On Wed, Aug 21, 2019 at 4:27 PM Thomas Hellström (VMware)
> > wrote:
> >> On 8/21/19 4:09 PM, Daniel Vetter wrote:
> >>> On Wed, Aug 21, 2019 at 2:47 PM Thomas Hellström (VMware)
> >>>
== Series Details ==
Series: Refactor to expand subslice mask (rev 2)
URL : https://patchwork.freedesktop.org/series/65509/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6750_full -> Patchwork_14114_full
Summary
---
On Wed, Aug 21, 2019 at 3:55 PM Ville Syrjälä
wrote:
>
> On Tue, Aug 20, 2019 at 01:57:44PM -0700, Daniele Ceraolo Spurio wrote:
> >
> >
> > On 8/20/19 12:54 PM, Daniel Vetter wrote:
> > > The cpu (de)tiler hw is gone, this stopped being useful. Plus it never
> > > supported any of the fancy new t
On Wed, Aug 21, 2019 at 5:19 PM Thomas Hellström (VMware)
wrote:
> On 8/21/19 5:14 PM, Daniel Vetter wrote:
> > On Wed, Aug 21, 2019 at 5:03 PM Thomas Hellström (VMware)
> > wrote:
> >> On 8/21/19 4:47 PM, Daniel Vetter wrote:
> >>> On Wed, Aug 21, 2019 at 4:27 PM Thomas Hellström (VMware)
> >>>
== Series Details ==
Series: drm/i915/execlists: Set priority hint prior to submission
URL : https://patchwork.freedesktop.org/series/65550/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6755 -> Patchwork_14123
Summary
With nouveau fixed all ttm-using drives have the correct nesting of
mmap_sem vs dma_resv, and we can just lock the buffer.
Assuming I didn't screw up anything with my audit of course.
v2:
- Dont forget wu_mutex (Christian König)
- Keep the mmap_sem-less wait optimization (Thomas)
- Use _lock_inte
On Tue, Aug 20, 2019 at 05:18:10PM +0200, Daniel Vetter wrote:
> On Tue, Aug 20, 2019 at 10:34:18AM -0300, Jason Gunthorpe wrote:
> > On Tue, Aug 20, 2019 at 10:19:02AM +0200, Daniel Vetter wrote:
> > > We need to make sure implementations don't cheat and don't have a
> > > possible schedule/blocki
On Tue, Aug 20, 2019 at 02:56:36PM +, Koenig, Christian wrote:
> Am 20.08.19 um 16:53 schrieb Daniel Vetter:
> > Full audit of everyone:
> >
> > - i915, radeon, amdgpu should be clean per their maintainers.
> >
> > - vram helpers should be fine, they don't do command submission, so
> >reall
We can reduce the locking for fence registers from the dev->struct_mutex
to a local mutex. We could introduce a mutex for the sole purpose of
tracking the fence acquisition, except there is a little bit of overlap
with the fault tracking, so use the i915_ggtt.mutex as it covers both.
Signed-off-by
These should have been validated in the upper layers, but for sanity's
sake, repeat them.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 16 +++-
1 file changed, 11 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/d
Since we now run process_csb() outside of the engine->active.lock, we
can process a CS-event immediately upon our ELSP write. As we currently
inspect the pending queue *after* the ELSP write, there is an
opportunity for a CS-event to update the pending queue before we can
read it, making ourselves
Avoid calling i915_vma_put_fence() by using our alternate paths that
bind a secondary vma avoiding the original fenced vma. For the few
instances where we need to release the fence (i.e. on binding when the
GGTT range becomes invalid), replace the put_fence with a revoke_fence.
Signed-off-by: Chri
Since we want to revoke the ggtt vma from only under the ggtt->mutex, we
need to move protection of the userfault tracking from the struct_mutex
to the ggtt->mutex.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 10 +++---
drivers/gpu/drm/i915/i915_debugfs.c
Chris Wilson writes:
> Since we now run process_csb() outside of the engine->active.lock, we
> can process a CS-event immediately upon our ELSP write. As we currently
> inspect the pending queue *after* the ELSP write, there is an
> opportunity for a CS-event to update the pending queue before we
== Series Details ==
Series: RFC/T: dma_resv vs. mmap_sem (rev2)
URL : https://patchwork.freedesktop.org/series/65488/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3166313498da dma_resv: prime lockdep annotations
-:65: WARNING:BAD_SIGN_OFF: email address '"VMware Graphics"
'
Chris Wilson writes:
> These should have been validated in the upper layers, but for sanity's
> sake, repeat them.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 16 +++-
> 1 file changed, 11 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/d
On Wed, Aug 21, 2019 at 05:54:27PM +0200, Thomas Hellström (VMware) wrote:
> On 8/20/19 4:53 PM, Daniel Vetter wrote:
> > Full audit of everyone:
> >
> > - i915, radeon, amdgpu should be clean per their maintainers.
> >
> > - vram helpers should be fine, they don't do command submission, so
> >
== Series Details ==
Series: RFC/T: dma_resv vs. mmap_sem (rev2)
URL : https://patchwork.freedesktop.org/series/65488/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6755 -> Patchwork_14124
Summary
---
**FAILURE**
Quoting Mika Kuoppala (2019-08-21 17:24:05)
> Chris Wilson writes:
>
> > These should have been validated in the upper layers, but for sanity's
> > sake, repeat them.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/i915_gem_gtt.c | 16 +++-
> > 1 file changed, 1
== Series Details ==
Series: series starting with [1/2] drm/i915: Don't deballoon unused ggtt
drm_mm_node in linux guest (rev2)
URL : https://patchwork.freedesktop.org/series/65450/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6750_full -> Patchwork_14115_full
==
On Wed, Aug 21, 2019 at 8:12 AM Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:
> Introduces a new parameters to execbuf so that we can specify syncobj
> handles as well as timeline points.
>
> v2: Reuse i915_user_extension_fn
>
> v3: Check that the chained extension is only present once
On Wed, Aug 21, 2019 at 03:32:12PM +0200, Maarten Lankhorst wrote:
> There was a integer wraparound when mode_clock became too high,
> and we didn't correct for the FEC overhead factor when dividing,
> also the calculations would break at HBR3.
But the mode_clock is obtained from the adusted_mode-
Quoting Zhenyu Wang (2019-08-21 04:35:56)
> On 2019.08.20 13:46:17 +0800, Xiong Zhang wrote:
> > The following call trace may exist in linux guest dmesg when guest i915
> > driver is unloaded.
> > [ 90.776610] [drm:vgt_deballoon_space.isra.0 [i915]] deballoon space:
> > range [0x0 - 0x0] 0 KiB.
From: Ville Syrjälä
We may need to eliminate the crtc->index == pipe assumptions from
the code to support arbitrary pipes being fused off. Start that by
switching some bitmasks over to using pipe instead of the crtc index.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdc
From: Ville Syrjälä
Replace all "int pipe"s with "enum pipe pipe"s to make it clear
what we're dealing with.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_display.c | 42 +--
.../drm/i915/display/intel_display_types.h| 2 +-
drivers/gpu/drm/i915/disp
From: Ville Syrjälä
Set a good example and talk about pipes rather than crtcs.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
i
From: Ville Syrjälä
Use hweight8() instead of hweight32() for 8bit masks. Doesn't actually
matter for us since the arch code will go for hweight32() anyway, but
maybe we stil want to do this for documentation purposes?
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 20 +
From: Ville Syrjälä
The "pipe" argument passed in by the vblank code is in fact the crtc
index. Don't assume that is the same as the pipe.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_irq.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/dr
On 2019-08-20 12:16 p.m., Ville Syrjala wrote:
> From: Ville Syrjälä
>
> We're not allowed to create new properties after device registration
> so for MST connectors we need to either create the max_bpc property
> earlier, or we reuse one we already have. Let's do the latter apporach
> since th
== Series Details ==
Series: drm/i915/gtt: Relax assertion for pt_used
URL : https://patchwork.freedesktop.org/series/65518/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6750_full -> Patchwork_14116_full
Summary
---
== Series Details ==
Series: series starting with [1/5] drm/i915/execlists: Set priority hint prior
to submission
URL : https://patchwork.freedesktop.org/series/65553/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6757 -> Patchwork_14125
==
Quoting Animesh Manna (2019-08-21 07:32:22)
> The function will internally get the gem buffer from global GTT
> which is mapped in cpu domain to feed the data + opcode for DSB engine.
>
> Cc: Imre Deak
> Cc: Michel Thierry
> Cc: Jani Nikula
> Cc: Rodrigo Vivi
> Signed-off-by: Animesh Manna
>
On Wed, Aug 21, 2019 at 7:06 PM Thomas Hellström (VMware)
wrote:
>
> On 8/21/19 6:34 PM, Daniel Vetter wrote:
> > On Wed, Aug 21, 2019 at 05:54:27PM +0200, Thomas Hellström (VMware) wrote:
> >> On 8/20/19 4:53 PM, Daniel Vetter wrote:
> >>> Full audit of everyone:
> >>>
> >>> - i915, radeon, amdgp
Quoting Animesh Manna (2019-08-21 07:32:25)
> DSB can program large set of data through indexed register write
> (opcode 0x9) in one shot. Will be using for bulk register programming
> e.g. gamma lut programming, HDR meta data programming.
>
> Cc: Shashank Sharma
> Cc: Imre Deak
> Cc: Jani Nikul
Quoting Animesh Manna (2019-08-21 07:32:26)
> Existing mmio-reg-write need intel_uncore handle which is part
> of dev_priv structure and the same design is followed by
> adding dsb handle in dev_priv for programming registers through DSB.
>
> I915_WRITE is modified to check for register capability
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