Quoting Michal Wajdeczko (2019-08-16 00:48:32)
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> index d056e1f4bd6d..ce828ae3ea03 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c
> @@ -206,
Quoting Patchwork (2019-08-16 00:52:20)
> Possible regressions
>
> * igt@i915_selftest@live_hangcheck:
> - fi-icl-u3: [PASS][1] -> [DMESG-FAIL][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6714/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
>[2]:
>
Quoting Daniele Ceraolo Spurio (2019-08-16 02:23:43)
> To reduce the number of explicit dev_priv->uncore calls in the display
> code ahead of the introduction of dev_priv->de_uncore, this patch
> introduces a wrapper for one of the main usages of it, the register
> waits. When we transition to the
On Thu, Aug 15, 2019 at 9:35 PM Tang, CQ wrote:
>
>
>
> > -Original Message-
> > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> > Of Daniel Vetter
> > Sent: Wednesday, August 14, 2019 12:25 PM
> > To: Intel Graphics Development
> > Cc: Daniel Vetter ; Vetter,
We really need to have separate NOT_SUPPORTED state (for
lack of hardware support) and DISABLED state (to indicate
user decision) as we will have to take special steps even
if GuC firmware is now disabled but hardware exists and
could have been previously used.
v2: fix logic (Chris/CI)
Signed-off
Move the active tracking for the frontbuffer operations out of the
i915_gem_object and into its own first class (refcounted) object. In the
process of detangling, we switch from low level request tracking to the
easier i915_active -- with the plan that this avoids any potential
atomic callbacks as
Chris Wilson writes:
> If we only call process_csb() from the tasklet, though we lose the
> ability to bypass ksoftirqd interrupt processing on direct submission
> paths, we can push it out of the irq-off spinlock.
>
> The penalty is that we then allow schedule_out to be called concurrently
> wit
Am 15.08.19 um 21:29 schrieb Chris Wilson:
> Quoting Chris Wilson (2019-08-15 20:03:13)
>> Quoting Daniel Vetter (2019-08-15 19:48:42)
>>> On Thu, Aug 15, 2019 at 8:46 PM Chris Wilson
>>> wrote:
Quoting Daniel Vetter (2019-08-14 18:20:53)
> On Sun, Aug 11, 2019 at 10:15:23AM +0100, Chris
From: José Roberto de Souza
No need to unmask PSR interrutpion if PSR is not enabled, better move
the call to intel_psr_enable_source().
Cc: Rodrigo Vivi
Cc: Dhinakaran Pandiyan
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_psr.c
On both A0 and A2 machines DDIC is not working. VBT reports the port as
being present. In BIOS configuration it seems to be disabled and can't
be enabled.
The symptom we have is while enabling the combo phy, PORT_COMP_DW*
return 0x, which is invalid per register definition.
During initial
After switching to smaller series and getting the patches applied, it's
time to go with a bigger series again to get a bigger context of patches
coming. If needed I can split the series or delegate to the original
author to handle the reviews.
This should also give a warning-free driver load, so w
From: José Roberto de Souza
Now that is allowed to have PSR enabled in any port from BDW+, lets
guard intel_psr_init_dpcd() against multiple eDP panels and warn about
it.
For now we will keep just one instance of PSR.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Sou
From: José Roberto de Souza
Tiger Lake has eDP-capable transcoders rather than a transcoder
dedicated to eDP. Transcoder A is the one where we have PSR2.
Actually transcoder B also supports PSR2 but only with software
tracking that is not implemented.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
S
From: José Roberto de Souza
According to PSR2_CTL definition on BSpec there is only one instance
of PSR2_CTL also ICL display overview state that PSR2 is only
supported in EDP transcoder, so now that is possible to have PSR in
any transcoder lets add this hardware restriction.
BSpec: 7713
BSpec:
From: José Roberto de Souza
PSR registers are a mess, some have the full address while others just
have the additional offset from psr_mmio_base.
For BDW+ psr_mmio_base is nothing more than TRANSCODER_EDP_OFFSET +
0x800 and using it makes more difficult for people with an PSR
register address or
From: José Roberto de Souza
It was enabling and checking PSR interruptions in every transcoder
while it should keep the interruptions on the non-used transcoders
masked.
This also already prepares for future when more the one PSR instance
will be allowed.
Cc: Dhinakaran Pandiyan
Signed-off-by:
From: José Roberto de Souza
This fix unclaimed access warnings:
[ 245.525788] [ cut here ]
[ 245.525884] Unclaimed read from register 0x62900
[ 245.526154] WARNING: CPU: 0 PID: 1234 at
drivers/gpu/drm/i915/intel_uncore.c:1100 __unclaimed_reg_debug+0x40/0x50 [i915]
[
From: José Roberto de Souza
According to BSpc if link standby is set on TGL+, PSR will not be
enabled. Vendors should not use panels that requires link standby and
even if they do, panel should assert a PSR error that will cause PSR to
be disabled.
BSpec: 50434
Signed-off-by: José Roberto de Sou
From: José Roberto de Souza
TGL PSR2 HW supports a bigger resolution, so lets add it
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_psr.c | 5 -
1 file changed, 4 insertions(+), 1 deleti
From: José Roberto de Souza
For older gens PSR IIR and IMR had a fixed address that was not
relative to anything, but from TGL those registers moved to each
transcoder offset.
So here adding a new macro and a new PSR irq handler with the
transcoder parameter.
Cc: Dhinakaran Pandiyan
Cc: Rodrig
From: José Roberto de Souza
From BDW+ the PSR registers moved from DDIA to transcoder, so any port
with a eDP panel connected can have PSR, so lets remove this limitation.
Cc: Dhinakaran Pandiyan
Cc: Rodrigo Vivi
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
driver
From: Michel Thierry
Enable Small PL for power benefit.
Signed-off-by: Michel Thierry
Signed-off-by: Lucas De Marchi
Reviewed-by: Stuart Summers
Reviewed-by: Radhakrishna Sripada
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++
drivers/gpu/drm/i915/
Add empty workaround hooks for Tiger Lake. The workarounds will be added
on separate patches. We were already applying
WaRsForcewakeAddDelayForAck, which is indeed still valid, so also update
the comment.
Cc: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
Reviewed-by: Radhakrishna Sripada
From: José Roberto de Souza
The same macro as for_each_new_connector_in_state() but it uses
intel/i915 types instead of the drm ones.
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/display/intel_display.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/dr
From: José Roberto de Souza
Same as for_each_oldnew_intel_crtc_in_state() but iterates in reverse
order.
Cc: Rodrigo Vivi
Cc: Ville Syrjälä
Signed-off-by: José Roberto de Souza
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/display/intel_display.h | 10 ++
1 file changed, 1
From: José Roberto de Souza
Disable CRTC/pipes in reverse order because some features (MST in
TGL+) requires master and slave relationship between pipes, so it
should always pick the lowest pipe as master as it will be enabled
first and disable in the reverse order so the master will be the last
From: José Roberto de Souza
Tiger Lake has up to 4 pipes so the mask would need to be 0xf instead of
0x7. Do not hardcode the mask so it allows the fake MST encoders to
connect to all pipes no matter how many the platform has.
Iterating over all pipes to keep consistent with intel_ddi_init().
C
From: José Roberto de Souza
On TGL the blending of all the streams have moved from DDI to
transcoder, so now every transcoder working over the same MST port must
send its stream to a master transcoder and master will send to DDI
respecting the time slots.
So here it is picking the lowest pipe/tr
From my tests this workaround is needed otherwise we read the wrong
number of slices later on. It's sent as a FIXME since I couldn't find
any documentation saying this applies to TGL. Fix the following warning:
[ 82.905527] WARN_ON_ONCE((mcr & mcr_slice_subslice_mask) != default_mcr_s_ss_
select
From: Michel Thierry
Workaround no longer needed (plus L3_LRA_1_GPGPU doesn't exist).
Cc: Daniele Ceraolo Spurio
Cc: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Signed-off-by: Michel Thierry
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
1 file changed, 1 in
From: Daniele Ceraolo Spurio
Gen12 uses a new indirect ctx offset.
Bspec: 11740
Cc: Joonas Lahtinen
Cc: Radhakrishna Sripada
Signed-off-by: Daniele Ceraolo Spurio
Reviewed-by: Lucas De Marchi
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 4
drivers/gpu/d
Gen 12 onwards moves the DP_TP_* registers to be transcoder-based rather
than port-based. This add the new register address and changes the
functions that are used with DDI on gen 12 to use the new registers. On
MST the master transcoder is the one to be used.
Cc: Rodrigo Vivi
Cc: Ville Syrjälä
From: Michel Thierry
HCP/MFX power gating is disabled by default, turn it on for the vd units
available. User space will also issue a MI_FORCE_WAKEUP properly to
wake up proper subwell.
During driver load, init_clock_gating happens after device_info_init_mmio
read the vdbox disable fuse register
From: Michel Thierry
Gen12 has subtle changes in the reg state context offsets (some fields
are gone, some are in a different location), compared to previous Gens.
The simplest approach seems to be keeping Gen12 (and future platform)
changes apart from the previous gens, while keeping the regist
From: José Roberto de Souza
On TGL some registers moved from DDI to transcoder and the
DisplayPort training sequence has a separate BSpec page.
I started adding 'ifs' to the original intel_ddi_pre_enable_dp() but
it was becoming really hard to follow, so a new and cleaner function
for TGL was ad
From: Daniele Ceraolo Spurio
Re-use Gen11 context size for now.
[ Lucas: add HACK since this is a temporary patch that needs to be
confirmed: we need to check BSpec 46255 and recompute ]
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_
From: Daniele Ceraolo Spurio
Like Gen11, Gen12 has 11 available bits for the ctx id field. However,
the last value (0x7FF) is reserved to indicate "invalid context", so
we need to reduce the maximum number of contexts by 1 compared to Gen11.
Cc: Joonas Lahtinen
Signed-off-by: Daniele Ceraolo Sp
From: Dhinakaran Pandiyan
Yf tiling was removed in gen-12, make the necessary to changes to not
expose the modifier to user space. Gen-12 display also is incompatible with
pre-gen12 Y-tiled compression, so do not expose
I915_FORMAT_MOD_Y_TILED_CCS.
Bspec: 29650
Cc: Daniel Vetter
Cc: Ville Syrj
From: Lionel Landwerlin
The design of the OA unit has been split into several units. We now
have a global unit (OAG) and a render specific unit (OAR). This leads
to some changes on how we program things. Some details :
OAR:
- has its own set of counter registers, they are per-context
saved
From: Michel Thierry
In Gen11, only even numbered "logical" VDBoxes are hooked up to a SFC
(Scaler & Format Converter) unit. This is not the case in Tigerlake,
where each VDBox can access a SFC.
We will use this information to decide when the SFC units need to be reset
and also pass it to the al
From: Lionel Landwerlin
The way our hardware is designed doesn't seem to let us use the
MI_RECORD_PERF_COUNT command without setting up a circular buffer.
In the case where the user didn't request OA reports to be available
through the i915 perf stream, we can set the OA buffer to the minimum
si
From: Michel Thierry
Compared to Icelake, Tigerlake's MAX_CONTEXT_HW_ID is smaller by one, but
since we just use the upper 32 bits of the lrc_desc, it's guaranteed OA
will use the correct one.
v2: rebase (Umesh)
Signed-off-by: Michel Thierry
Cc: Lionel Landwerlin
Reviewed-by: Lionel Landwerli
From: Dhinakaran Pandiyan
Gen-12 has a new compression format, add a new modifier for userspace to
indicate that.
Cc: Ville Syrjälä
Cc: Daniel Vetter
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Lucas De Marchi
---
include/uapi/drm/drm_fourcc.h | 10 ++
1 file changed, 10 inser
From: Dhinakaran Pandiyan
Gen-12 decompression is supported with Y-tiled main surface. The CCS is
linear and has 4 bits of data for each main surface cache line pair, a
ratio of 1:256. Gen-12 display decompression is incompatible with buffers
compressed by earlier GPUs, so make use of a new modif
== Series Details ==
Series: drm/i915/gtt: Fold gen8 insertions into one
URL : https://patchwork.freedesktop.org/series/65258/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6712_full -> Patchwork_14030_full
Summary
---
From: Michel Thierry
GAM registers located in the 0x4xxx range have been relocated to 0xCxxx;
this is to make space for global MOCS registers.
HSD: 399379
Cc: Daniele Ceraolo Spurio
Signed-off-by: Michel Thierry
Signed-off-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h |
From: Michel Thierry
Gen12 removes the target-cache and age fields from the private PAT
because MOCS now have the capability to set these itself. Only memory-type
field should be programmed in the ppat, the reminded bits are reserved.
Since now there are only 4 possible combinations, we could se
From: Dhinakaran Pandiyan
Gen-12 display can decompress surfaces compressed by the media engine, add
a new modifier as the driver needs to know the surface was compressed by
the media or render engine.
Cc: Ville Syrjälä
Signed-off-by: Dhinakaran Pandiyan
Signed-off-by: Lucas De Marchi
---
in
From: Dhinakaran Pandiyan
Gen-12 display can decompress surfaces compressed by the media engine.
Detect the modifier corresponding to media compression to enable
decompression for YUV and ARGB packed formats. A new modifier is added
so that the driver can distinguish between media and render comp
On Thu 15-08-19 17:13:23, Jason Gunthorpe wrote:
> On Thu, Aug 15, 2019 at 09:35:26PM +0200, Michal Hocko wrote:
>
> > > The last detail is I'm still unclear what a GFP flags a blockable
> > > invalidate_range_start() should use. Is GFP_KERNEL OK?
> >
> > I hope I will not make this muddy again ;
== Series Details ==
Series: drm/i915/uc: Add explicit DISABLED state for firmware (rev2)
URL : https://patchwork.freedesktop.org/series/65278/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6715 -> Patchwork_14044
Summary
-
On Thu 15-08-19 15:15:09, Andrew Morton wrote:
> On Thu, 15 Aug 2019 10:44:29 +0200 Michal Hocko wrote:
>
> > > I continue to struggle with this. It introduces a new kernel state
> > > "running preemptibly but must not call schedule()". How does this make
> > > any sense?
> > >
> > > Perhaps a
On Thu 15-08-19 22:16:43, Daniel Vetter wrote:
> On Thu, Aug 15, 2019 at 9:35 PM Michal Hocko wrote:
[...]
> > > The last detail is I'm still unclear what a GFP flags a blockable
> > > invalidate_range_start() should use. Is GFP_KERNEL OK?
> >
> > I hope I will not make this muddy again ;)
> > inv
We store the gt&uncoree to use in the address space, so use it!
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 208bd25163c
== Series Details ==
Series: drm/i915: Extract intel_frontbuffer active tracking
URL : https://patchwork.freedesktop.org/series/65289/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6715 -> Patchwork_14045
Summary
---
Quoting Mika Kuoppala (2019-08-16 08:50:29)
> Chris Wilson writes:
> > static inline struct i915_request *
> > execlists_schedule_in(struct i915_request *rq, int idx)
> > {
> > - struct intel_context *ce = rq->hw_context;
> > - int count;
> > + struct intel_context * const ce = rq->
== Series Details ==
Series: drm/i915/uc: Fini hw even if GuC is not running (rev2)
URL : https://patchwork.freedesktop.org/series/65140/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6712_full -> Patchwork_14033_full
Summa
If we only call process_csb() from the tasklet, though we lose the
ability to bypass ksoftirqd interrupt processing on direct submission
paths, we can push it out of the irq-off spinlock.
The penalty is that we then allow schedule_out to be called concurrently
with schedule_in requiring us to hand
We use timeline->mutex to protect modifications to
context->active_count, and the associated enable/disable callbacks.
Due to complications with engine-pm barrier there is a path where we used
a "superlock" to provide serialised protect and so could not
unconditionally assert with lockdep that it w
As every i915_active_request should be serialised by a dedicated lock,
i915_active consists of a tree of locks; one for each node. Markup up
the i915_active_request with what lock is supposed to be guarding it so
that we can verify that the serialised updated are indeed serialised.
Signed-off-by:
On Thu, 15 Aug 2019, Daniele Ceraolo Spurio
wrote:
> This is only required for a single platform so no need to reserve the
> memory on all of them.
>
> This removes the last direct dependency of i915_drv.h on i915_reg.h
> (apart from the i915_reg_t definition).
>
> Signed-off-by: Daniele Ceraolo
== Series Details ==
Series: Tiger Lake batch 3
URL : https://patchwork.freedesktop.org/series/65290/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2f6d4ad3eda1 drm/i915/tgl: do not use DDIC
c0c2c6e584ca drm/i915/psr: Make PSR registers relative to transcoders
-:427: WARNING:LO
Quoting Jani Nikula (2019-08-16 10:35:08)
> On Thu, 15 Aug 2019, Daniele Ceraolo Spurio
> wrote:
> > @@ -1622,7 +1560,7 @@ struct drm_i915_private {
> > u32 suspend_count;
> > bool power_domains_suspended;
> > struct i915_suspend_saved_registers regfile;
> > - struct vlv_s0i
On Fri, 16 Aug 2019 03:23:42 +0200, Daniele Ceraolo Spurio
wrote:
With the introduction of display uncore, we want to categorize registers
between display and non-display. To help us getting it right, it will
be useful to move the display registers to a new file that can be used
without inclu
As we give page directory pointer (lvl 3) structure
for pte insertion, we can fold both versions into
one function by teaching it to get pdp regardless
of top level.
v2: naming and asserts (Chris)
Cc: Chris Wilson
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 96 ++
Hello,
On Fri, Aug 16, 2019 at 08:23:54AM +0200, Daniel Vetter wrote:
> On Fri, Aug 16, 2019 at 6:48 AM Sam Ravnborg wrote:
> > > Hi all,
> > >
> > > After merging the drm-misc tree, today's linux-next build (x86_64
> > > allmodconfig) produced this warning:
> > >
> > > warning: same module names
== Series Details ==
Series: Tiger Lake batch 3
URL : https://patchwork.freedesktop.org/series/65290/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915/tgl: do not use DDIC
Okay!
Commit: drm/i915/psr: Make PSR registers relative to transcoders
O
Quoting Mika Kuoppala (2019-08-16 10:47:54)
> As we give page directory pointer (lvl 3) structure
> for pte insertion, we can fold both versions into
> one function by teaching it to get pdp regardless
> of top level.
>
> v2: naming and asserts (Chris)
>
> Cc: Chris Wilson
> Signed-off-by: Mika
To work around a DMC/Punit issue on ICL where the driver's
ICL_PORT_COMP_DW8/IREFGEN PHY setting is lost when entering/exiting DC6
state, make sure to reinit the PHY whenever disabling DC states.
Similarly the driver's PHY/DBUF/CDCLK settings should have been preserved
across DC5/6 transitions, so
== Series Details ==
Series: Tiger Lake batch 3
URL : https://patchwork.freedesktop.org/series/65290/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6716 -> Patchwork_14046
Summary
---
**SUCCESS**
No regressions fo
Hi Randy,
On Thu, Aug 15, 2019 at 08:10:03PM -0700, Randy Dunlap wrote:
> [adding mailing lists etc. with Nathaniel's test info]
>
> On 8/15/19 7:21 PM, Nathaniel Russell wrote:
> > Well i surpressed the uvcvideo driver and you are right Randy it
> > definitely is not the uvcvideo driver. There i
If we are leaking nodes don't hide it. Also stop trying to be
"defensive" and instead embrace Kasan et al.
Signed-off-by: Matthew Auld
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_buddy.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_buddy
On Fri, 16 Aug 2019 at 09:31, Chris Wilson wrote:
>
> We store the gt&uncoree to use in the address space, so use it!
>
> Signed-off-by: Chris Wilson
Reviewed-by: Matthew Auld
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.fre
Quoting Matthew Auld (2019-08-16 11:03:26)
> If we are leaking nodes don't hide it. Also stop trying to be
> "defensive" and instead embrace Kasan et al.
If you want to go even further, record the stacks of each allocator.
As we are using kmalloc of each node and operate like a cache, we can do
s
On Thu, 15 Aug 2019, Chris Wilson wrote:
> Looking around the GT initialisation, we have a few log messages we
> think are interesting enough present to the user (such as the amount of L4
> cache) and a few to inform them of the result of actions or conflicting
> HW restrictions (i.e. quirks). The
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Lucas
>De Marchi
>Sent: Thursday, August 15, 2019 5:25 AM
>To: intel-gfx@lists.freedesktop.org
>Subject: [Intel-gfx] [PATCH] drm/i915/tgl: disable DDIC
>
>The current SKUs added for Tiger
== Series Details ==
Series: Revert "ALSA: hda - Drop unsol event handler for Intel HDMI codecs"
URL : https://patchwork.freedesktop.org/series/65267/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6712_full -> Patchwork_14034_full
==
On Fri, 16 Aug 2019, Chris Wilson wrote:
> Quoting Jani Nikula (2019-08-16 10:35:08)
>> On Thu, 15 Aug 2019, Daniele Ceraolo Spurio
>> wrote:
>> > @@ -1622,7 +1560,7 @@ struct drm_i915_private {
>> > u32 suspend_count;
>> > bool power_domains_suspended;
>> > struct i915_suspend
Use a locked xchg to ensure that the global log message giving
instructions on how to send a bug report is emitted precisely once.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gpu_error.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915
== Series Details ==
Series: drm/i915: Use the associated uncore for the vm
URL : https://patchwork.freedesktop.org/series/65291/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6716 -> Patchwork_14047
Summary
---
**SU
Since nodes are cached in a free-list, and potentially marked as free
without actually being destroyed, thus allowing them to be
opportunistically re-allocated, we should apply kmemleak_update_trace
every time a node is given a new owner and marked as allocated, to aid
in debugging.
Suggested-by:
If we are leaking nodes don't hide it. Also stop trying to be
"defensive" and instead embrace Kasan et al.
Signed-off-by: Matthew Auld
Cc: Chris Wilson
---
drivers/gpu/drm/i915/i915_buddy.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_buddy
We can do WOPCM partitioning using rough estimates and limits
and perform detailed check as separate step.
v2: oops! s/max/min
v3: consolidate overflow checks (Daniele)
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_wopcm.c | 97
All WOPCM error messages are device specific, so use
device specific error functions.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_wopcm.c | 44 --
1 file changed, 24 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915
More WOPCM fixes
v3: consolidate overflow checks (Daniele)
Michal Wajdeczko (4):
drm/i915/wopcm: Check WOPCM layout separately from calculations
drm/i915/wopcm: Try to use already locked WOPCM layout
drm/i915/wopcm: Update error messages
drm/i915/wopmc: Fix SPDX tag location
Michał Winia
If WOPCM layout is already locked in HW we shouldn't continue
with our own partitioning as it could be likely different and
we will be unable to enforce it and fail. Instead we should try
to reuse what is already programmed, maybe there will be a fit.
This should enable us to reload driver with sl
From: Michał Winiarski
While we need to know WOPCM size to do this sanity check, it has more to
do with FW than with WOPCM. Let's move the check to fetch phase, it's
not like WOPCM is going to grow in the meantime.
v2: rebased
v3: use __intel_uc_fw_get_upload_size (Daniele)
Signed-off-by: Micha
Move SPDX tag to first line, and update year to 2019.
Signed-off-by: Michal Wajdeczko
Cc: Chris Wilson
---
drivers/gpu/drm/i915/intel_wopcm.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_wopcm.c
b/drivers/gpu/drm/i915/intel_wopcm.c
index e
Quoting Matthew Auld (2019-08-16 11:53:57)
> Since nodes are cached in a free-list, and potentially marked as free
> without actually being destroyed, thus allowing them to be
> opportunistically re-allocated, we should apply kmemleak_update_trace
> every time a node is given a new owner and marked
Quoting Matthew Auld (2019-08-16 11:53:56)
> If we are leaking nodes don't hide it. Also stop trying to be
> "defensive" and instead embrace Kasan et al.
>
> Signed-off-by: Matthew Auld
> Cc: Chris Wilson
> ---
> drivers/gpu/drm/i915/i915_buddy.c | 7 +--
> 1 file changed, 1 insertion(+), 6
== Series Details ==
Series: series starting with [1/3] drm/i915/execlists: Lift process_csb() out
of the irq-off spinlock
URL : https://patchwork.freedesktop.org/series/65294/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
03b058860a18 drm/i915/execlists: Lift process_csb() ou
Quoting Michal Wajdeczko (2019-08-16 11:55:00)
> All WOPCM error messages are device specific, so use
> device specific error functions.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Chris Wilson
Reviewed-by: Chris Wilson
-Chris
___
Intel-gfx mailing list
Quoting Michal Wajdeczko (2019-08-16 11:55:01)
> Move SPDX tag to first line, and update year to 2019.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Chris Wilson
Reviewed-by: Chris Wilson
Head, bury thyself in the sand.
-Chris
___
Intel-gfx mailing list
== Series Details ==
Series: Revert "ALSA: hda: Add codec on bus address table lately"
URL : https://patchwork.freedesktop.org/series/65271/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6712_full -> Patchwork_14036_full
Su
Quoting Michal Wajdeczko (2019-08-16 11:54:58)
> +static inline bool __check_layout(struct drm_i915_private *i915, u32
> wopcm_size,
> + u32 guc_wopcm_base, u32 guc_wopcm_size,
> + u32 guc_fw_size, u32 huc_fw_size)
> +{
> + cons
On Fri, 16 Aug 2019 13:21:03 +0200, Chris Wilson
wrote:
Quoting Michal Wajdeczko (2019-08-16 11:54:58)
+static inline bool __check_layout(struct drm_i915_private *i915, u32
wopcm_size,
+ u32 guc_wopcm_base, u32
guc_wopcm_size,
+
== Series Details ==
Series: series starting with [1/3] drm/i915/execlists: Lift process_csb() out
of the irq-off spinlock
URL : https://patchwork.freedesktop.org/series/65294/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6716 -> Patchwork_14048
=
Quoting Patchwork (2019-08-16 12:26:55)
> * igt@gem_sync@basic-store-each:
> - fi-cfl-8109u: [PASS][1] -> [INCOMPLETE][2]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6716/fi-cfl-8109u/igt@gem_s...@basic-store-each.html
>[2]:
> https://intel-gfx-ci.01.org/tree/drm-t
Hi Daniel, Dave,
Here's this week drm-misc-next PR.
Maxime
drm-misc-next-2019-08-16:
drm-misc-next for 5.4:
UAPI Changes:
Cross-subsystem Changes:
Core Changes:
- dma-buf: add reservation_object_fences helper, relax
reservation_object_add_shared_fence, remove
reser
Chris Wilson writes:
> If we only call process_csb() from the tasklet, though we lose the
> ability to bypass ksoftirqd interrupt processing on direct submission
> paths, we can push it out of the irq-off spinlock.
>
> The penalty is that we then allow schedule_out to be called concurrently
> wit
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