Re: [Intel-gfx] [PATCH] drm/i915: Replace hangcheck by heartbeats

> -Original Message- > From: Chris Wilson > Sent: Thursday, July 25, 2019 4:28 PM > To: Bloomfield, Jon ; intel- > g...@lists.freedesktop.org > Cc: Joonas Lahtinen ; Ursulin, Tvrtko > > Subject: RE: [PATCH] drm/i915: Replace hangcheck by heartbeats > > Quoting Bloomfield, Jon (2019-07-26

[Intel-gfx] [CI 1/3] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization

According to the spec when initializing the display in TGL we should not set PORT_CL_DW12 for the Aux channel of the combo PHYs. We will re-use the power well hooks from ICL so only set this register on gen < 12. v2: Generalize check for gen 12 (suggested by José) v3: Rebase after enum phy introdu

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Capture vma contents outside of spinlock (rev2)

== Series Details == Series: drm/i915: Capture vma contents outside of spinlock (rev2) URL : https://patchwork.freedesktop.org/series/64256/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Capture vma contents outside of spinlock -O:drivers/gp

[Intel-gfx] [PATCH 1/3] drm/i915/tgl: Add hpd interrupt handling

Add hotdplug detection for all ports on TGP. icp_hpd_detection_setup() is refactored to be shared with TGP. While we increase the number of pins, add a BUILD_BUG_ON() to avoid going over the number of bits allowed. v2: use BITS_PER_TYPE and correct type for BUILD_BUG_ON() check (requested by

[Intel-gfx] [PATCH 3/3] drm/i915/tgl: handle DP aux interrupts

For Tiger Lake the DE Port Interrupt Definition bits changed, so use the new bit definitions. Cc: Jose Souza Signed-off-by: Lucas De Marchi Reviewed-by: Anusha Srivatsa Link: https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-7-lucas.demar...@intel.com --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 2/3] drm/i915/tgl: Update north display hotplug detection to TGL connections

From: José Roberto de Souza TGL has 3 combophys and 6 TC/TBT ports, so it has 2 more TC/TBT ports than ICL and the PORT_C on TGL is a combophy. So here adding a new hpd north table and function to detect long pulse for TGL. Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De Marchi Re

[Intel-gfx] [PATCH 0/3] Tiger Lake: interrupts

North and south interrupts. Updated version of the patches extracted from https://patchwork.freedesktop.org/series/63670/ José Roberto de Souza (1): drm/i915/tgl: Update north display hotplug detection to TGL connections Lucas De Marchi (2): drm/i915/tgl: Add hpd interrupt handling drm/

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/uc: Reorder params in intel_uc_fw_fetch

== Series Details == Series: drm/i915/uc: Reorder params in intel_uc_fw_fetch URL : https://patchwork.freedesktop.org/series/64265/ State : success == Summary == CI Bug Log - changes from CI_DRM_6555 -> Patchwork_13758 Summary --- **

Re: [Intel-gfx] [PATCH] drm/i915: Replace hangcheck by heartbeats

Quoting Bloomfield, Jon (2019-07-26 00:41:49) > > -Original Message- > > From: Chris Wilson > > Sent: Thursday, July 25, 2019 4:28 PM > > To: Bloomfield, Jon ; intel- > > g...@lists.freedesktop.org > > Cc: Joonas Lahtinen ; Ursulin, Tvrtko > > > > Subject: RE: [PATCH] drm/i915: Replace ha

[Intel-gfx] [PATCH 5/5] drm/i915/tgl: Add support for dkl pll write

From: Vandita Kulkarni Add a new function to write to dkl phy pll registers. As per the spec all the registers are read modify write. Signed-off-by: Vandita Kulkarni Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 65 ++- 1 file changed, 64 i

[Intel-gfx] [PATCH 2/5] drm/i915/tgl: re-indent code to prepare for DKL changes

The final save operation into pll_state of the calculations done will be different for DKL PHY. Prepare for that by reindenting code so it's easier to check for correctness. This one has no change in behavior. Signed-off-by: Lucas De Marchi Reviewed-by: Matt Atwood Link: https://patchwork.freed

[Intel-gfx] [PATCH 4/5] drm/i915/tgl: start adding the DKL PLLs to use on TC ports

The disable function can be the same as for MG phy since the same registers are used. The others are different as registers change - prepare for that using an empty dkl_pll_write() to be implemented later. Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 98

[Intel-gfx] [PATCH 3/5] drm/i915/tgl: Add DKL phy pll state calculations

From: Vandita Kulkarni Reuse the existing calculate icl_calc_mg_pll_state() function. Since the pll variables are calculated differently for DKL phy, add support for the same. Signed-off-by: Vandita Kulkarni Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 59

[Intel-gfx] [PATCH 1/5] drm/i915/tgl: Add DKL phy pll registers

From: Vandita Kulkarni These are the registers needed to program Dekel PHY. Some register definitions reuse the MG PHY definitions. Add a comment on those so we don't need to duplicate the functions for programming them. Signed-off-by: Vandita Kulkarni Signed-off-by: Lucas De Marchi --- drive

[Intel-gfx] [PATCH 0/5] Tiger Lake: DKL phy PLLs

Mostly the same patches as https://patchwork.freedesktop.org/series/63670/. Rebased. Lucas De Marchi (2): drm/i915/tgl: re-indent code to prepare for DKL changes drm/i915/tgl: start adding the DKL PLLs to use on TC ports Vandita Kulkarni (3): drm/i915/tgl: Add DKL phy pll registers drm/i9

[Intel-gfx] [PATCH 0/3] Tiger Lake: add workarounds

Same patches as extracted from https://patchwork.freedesktop.org/series/63670/ and rebased. Michel Thierry (3): drm/i915/tgl: Introduce initial Tigerlake Workarounds drm/i915/tgl: Implement Wa_1604555607 drm/i915/tgl: Implement Wa_1406941453 drivers/gpu/drm/i915/gt/intel_lrc.c | 2

[Intel-gfx] [PATCH 1/3] drm/i915/tgl: Introduce initial Tigerlake Workarounds

From: Michel Thierry Inherit workarounds from previous platforms that are still valid for Tigerlake. WaPipelineFlushCoherentLines:tgl (changed register but has same name) WaSendPushConstantsFromMMIO:tgl WaAllowUMDToModifySamplerMode:tgl WaRsForcewakeAddDelayForAck:tgl Cc: Daniele Ceraol

[Intel-gfx] [PATCH 3/3] drm/i915/tgl: Implement Wa_1406941453

From: Michel Thierry Enable Small PL for power benefit. Signed-off-by: Michel Thierry Signed-off-by: Lucas De Marchi Reviewed-by: Stuart Summers Link: https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-18-lucas.demar...@intel.com --- drivers/gpu/drm/i915/gt/intel_workarounds

[Intel-gfx] [PATCH 2/3] drm/i915/tgl: Implement Wa_1604555607

From: Michel Thierry Implement Wa_1604555607 (set the DS pairing timer to 128 cycles). FF_MODE2 is part of the register state context, that's why it is implemented here. Signed-off-by: Michel Thierry Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++ d

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915: Capture vma contents outside of spinlock

== Series Details == Series: series starting with [1/5] drm/i915: Capture vma contents outside of spinlock URL : https://patchwork.freedesktop.org/series/64268/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7bdf4e249991 drm/i915: Capture vma contents outside of spinlock 4e2d37

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Capture vma contents outside of spinlock (rev2)

== Series Details == Series: drm/i915: Capture vma contents outside of spinlock (rev2) URL : https://patchwork.freedesktop.org/series/64256/ State : success == Summary == CI Bug Log - changes from CI_DRM_6555 -> Patchwork_13759 Summary

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915: Capture vma contents outside of spinlock

== Series Details == Series: series starting with [1/5] drm/i915: Capture vma contents outside of spinlock URL : https://patchwork.freedesktop.org/series/64268/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Capture vma contents outside of s

Re: [Intel-gfx] [PATCH 2/3] drm/i915/tgl: Implement Wa_1604555607

Quoting Lucas De Marchi (2019-07-26 01:02:25) > From: Michel Thierry > > Implement Wa_1604555607 (set the DS pairing timer to 128 cycles). > FF_MODE2 is part of the register state context, that's why it is > implemented here. > > Signed-off-by: Michel Thierry > Signed-off-by: Lucas De Marchi >

[Intel-gfx] [PATCH 3/4] drm/i915/tgl: Tigerlake only has global MOCS registers

From: Michel Thierry Until Icelake, each engine had its own set of 64 MOCS registers. In order to simplify, Tigerlake moves to only 64 Global MOCS registers, which are no longer part of the engine context. Since these registers are now global, they also only need to be initialized once. From Gen

[Intel-gfx] [PATCH 1/4] drm/i915/tgl: Move fault registers to their new offset

The fault registers moved to another offset. The old location is now taken by the global MOCS registers, to be added in a follow up change. Based on previous patches by Michel Thierry . Cc: Daniele Ceraolo Spurio Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/gt/intel_gt.c| 24 +++

[Intel-gfx] [PATCH 0/4] Tiger Lake: MOCS table handling

v2 of the MOCS patches originally at https://patchwork.freedesktop.org/series/63670/ handling the review comments received. This needs the accompanying IGT patches so it doesn't regress on Ice Lake: https://patchwork.freedesktop.org/series/64263/ Lucas De Marchi (1): drm/i915/tgl: Move fault re

[Intel-gfx] [PATCH 2/4] drm/i915/tgl: Define MOCS entries for Tigerlake

From: Tomasz Lis The MOCS table is published as part of bspec, and versioned. Entries are supposed to never be modified, but new ones can be added. Adding entries increases table version. The patch includes version 1 entries. Two of the 3 legacy entries used for gen9 are no longer expected to wo

[Intel-gfx] [PATCH 4/4] drm/i915: Move MOCS setup to intel_mocs.c

From: Tvrtko Ursulin Hide the details of MOCS setup from i915_gem by moving both current calls into one in intel_mocs_init. Cc: Stuart Summers Signed-off-by: Tvrtko Ursulin Signed-off-by: Lucas De Marchi Reviewed-by: Stuart Summers Link: https://patchwork.freedesktop.org/patch/msgid/2019071

[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/5] drm/i915: Capture vma contents outside of spinlock

== Series Details == Series: series starting with [1/5] drm/i915: Capture vma contents outside of spinlock URL : https://patchwork.freedesktop.org/series/64268/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6555 -> Patchwork_13760 =

Re: [Intel-gfx] [PATCH 4/4] drm/i915: Move MOCS setup to intel_mocs.c

Quoting Lucas De Marchi (2019-07-26 01:12:08) > From: Tvrtko Ursulin > > Hide the details of MOCS setup from i915_gem by moving both current calls > into one in intel_mocs_init. > > Cc: Stuart Summers > Signed-off-by: Tvrtko Ursulin > Signed-off-by: Lucas De Marchi > Reviewed-by: Stuart Summe

[Intel-gfx] [PATCH 3/3] drm/i915/tgl: add support for reading the timestamp frequency

From: Michel Thierry There are no changes with respect to GEN11, which Paulo wrote. This gets rid of the "Missing switch case in read_timestamp_frequency" message at boot for Tiger Lake. Cc: Paulo Zanoni Cc: Lionel Landwerlin Signed-off-by: Michel Thierry Signed-off-by: Lucas De Marchi ---

[Intel-gfx] [PATCH 2/3] drm/i915/tgl: allow the reg_read ioctl to read the RCS TIMESTAMP register

From: Jordan Justen This enables the Mesa driver to advertise support for ARB_timer_query, and thus an OpenGL version higher than 3.2. Based on the ICL patch by Paulo Zanoni and CNL patch by Nanley Chery. Cc: Joonas Lahtinen Cc: Rodrigo Vivi Signed-off-by: Jordan Justen Signed-off-by: Lucas

[Intel-gfx] [PATCH 1/3] drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers

From: José Roberto de Souza Tiger Lake has a new register offset for DC5 and DC6 residency counters. v2: - Rename registers since they are not in the CSR memory range (requested by Anshuman) - Fix type (requested by Matthew) Signed-off-by: José Roberto de Souza Signed-off-by: Lucas De

[Intel-gfx] [PATCH 0/3] Tiger Lake: register moves

Patches extracted from https://patchwork.freedesktop.org/series/63670/ and rebased. Jordan Justen (1): drm/i915/tgl: allow the reg_read ioctl to read the RCS TIMESTAMP register José Roberto de Souza (1): drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers Michel Thierry

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/uc: Reorder params in intel_uc_fw_fetch

Quoting Patchwork (2019-07-26 00:51:44) > == Series Details == > > Series: drm/i915/uc: Reorder params in intel_uc_fw_fetch > URL : https://patchwork.freedesktop.org/series/64265/ > State : success > > == Summary == > > CI Bug Log - changes from CI_DRM_6555 -> Patchwork_13758 > ===

[Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Replace hangcheck by heartbeats

== Series Details == Series: drm/i915: Replace hangcheck by heartbeats URL : https://patchwork.freedesktop.org/series/64269/ State : failure == Summary == Applying: drm/i915: Replace hangcheck by heartbeats Using index info to reconstruct a base tree... M drivers/gpu/drm/i915/Kconfig.pro

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [CI,1/3] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization

== Series Details == Series: series starting with [CI,1/3] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization URL : https://patchwork.freedesktop.org/series/64271/ State : warning == Summary == $ dim checkpatch origin/drm-tip 43f991ca3886 drm/i915/tgl: skip setting PORT_CL_DW12_* on

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [CI,1/3] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization

== Series Details == Series: series starting with [CI,1/3] drm/i915/tgl: skip setting PORT_CL_DW12_* on initialization URL : https://patchwork.freedesktop.org/series/64271/ State : success == Summary == CI Bug Log - changes from CI_DRM_6557 -> Patchwork_13762 =

[Intel-gfx] ✓ Fi.CI.BAT: success for Tiger Lake: interrupts

== Series Details == Series: Tiger Lake: interrupts URL : https://patchwork.freedesktop.org/series/64272/ State : success == Summary == CI Bug Log - changes from CI_DRM_6557 -> Patchwork_13763 Summary --- **SUCCESS** No regression

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Do not rely on for loop caching the mask

== Series Details == Series: drm/i915: Do not rely on for loop caching the mask URL : https://patchwork.freedesktop.org/series/64225/ State : success == Summary == CI Bug Log - changes from CI_DRM_6551_full -> Patchwork_13749_full Summary -

[Intel-gfx] ✓ Fi.CI.BAT: success for Tiger Lake: DKL phy PLLs

== Series Details == Series: Tiger Lake: DKL phy PLLs URL : https://patchwork.freedesktop.org/series/64273/ State : success == Summary == CI Bug Log - changes from CI_DRM_6557 -> Patchwork_13764 Summary --- **SUCCESS** No regressi

[Intel-gfx] ✓ Fi.CI.BAT: success for Tiger Lake: add workarounds

== Series Details == Series: Tiger Lake: add workarounds URL : https://patchwork.freedesktop.org/series/64274/ State : success == Summary == CI Bug Log - changes from CI_DRM_6557 -> Patchwork_13765 Summary --- **SUCCESS** No regre

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake: MOCS table handling

== Series Details == Series: Tiger Lake: MOCS table handling URL : https://patchwork.freedesktop.org/series/64275/ State : warning == Summary == $ dim checkpatch origin/drm-tip 80a9b7285063 drm/i915/tgl: Move fault registers to their new offset 9efbb1606638 drm/i915/tgl: Define MOCS entries fo

[Intel-gfx] ✓ Fi.CI.BAT: success for Tiger Lake: MOCS table handling

== Series Details == Series: Tiger Lake: MOCS table handling URL : https://patchwork.freedesktop.org/series/64275/ State : success == Summary == CI Bug Log - changes from CI_DRM_6557 -> Patchwork_13766 Summary --- **SUCCESS** No r

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/gt: Add to timeline requires the timeline mutex

== Series Details == Series: series starting with [1/2] drm/i915/gt: Add to timeline requires the timeline mutex URL : https://patchwork.freedesktop.org/series/64227/ State : success == Summary == CI Bug Log - changes from CI_DRM_6551_full -> Patchwork_13750_full =

[Intel-gfx] ✓ Fi.CI.BAT: success for Tiger Lake: register moves

== Series Details == Series: Tiger Lake: register moves URL : https://patchwork.freedesktop.org/series/64277/ State : success == Summary == CI Bug Log - changes from CI_DRM_6557 -> Patchwork_13767 Summary --- **SUCCESS** No regres

Re: [Intel-gfx] [PATCH 1/3] drm/i915/tgl: Add and use new DC5 and DC6 residency counter registers

On 7/26/2019 5:54 AM, Lucas De Marchi wrote: From: José Roberto de Souza Tiger Lake has a new register offset for DC5 and DC6 residency counters. v2: - Rename registers since they are not in the CSR memory range (requested by Anshuman) - Fix type (requested by Matthew) Signed-off

Re: [Intel-gfx] [PATCH] drm/i915/uc: Don't sanitize guc_log_level modparam

On Thu, 25 Jul 2019 23:44:08 +0200, Chris Wilson wrote: Quoting Michal Wajdeczko (2019-07-25 21:51:06) We are already storing runtime value of log level in private field, so there is no need to modify modparam. There is an aspect of communicating the clamped value back to the user. Does th

Re: [Intel-gfx] [PATCH] drm/i915/guc: init submission structures as part of guc_init

On Thu, 25 Jul 2019 19:46:55 +0200, Daniele Ceraolo Spurio wrote: guc->stage_desc_pool is required as part of the init parameters and there is no reason we have to init them after HuC. This fixes a NULL ptr dereference due to guc->stage_desc_pool not being set (no fixes tag since GuC submissi

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [v2,1/3] drm/i915: Fix GuC documentation links

== Series Details == Series: series starting with [v2,1/3] drm/i915: Fix GuC documentation links URL : https://patchwork.freedesktop.org/series/64237/ State : failure == Summary == CI Bug Log - changes from CI_DRM_6551_full -> Patchwork_13751_full ==

Re: [Intel-gfx] [PATCH v5 02/24] drm: Add drm_connector_init() variant with ddc

Hi Andrzej. On Wed, Jul 24, 2019 at 03:59:24PM +0200, Andrzej Pietrasiewicz wrote: > Allow passing ddc adapter pointer to the init function. Even if > drm_connector_init() sometime in the future decides to e.g. memset() all > connector fields to zeros, the newly added function ensures that at its

Re: [Intel-gfx] [PATCH v5 01/24] drm: Include ddc adapter pointer in struct drm_connector

Hi Andrzej. Patch looks good, but one kernel-doc detail. On Wed, Jul 24, 2019 at 03:59:23PM +0200, Andrzej Pietrasiewicz wrote: > Add generic code which creates symbolic links in sysfs, pointing to ddc > interface used by a particular video output. For example: > > ls -l /sys/class/drm/card0-HDM

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