[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for C: Revert "net/sch_generic: Shut up noise"

== Series Details == Series: C: Revert "net/sch_generic: Shut up noise" URL : https://patchwork.freedesktop.org/series/60758/ State : warning == Summary == $ dim checkpatch origin/drm-tip ca5680e2af43 C: Revert "net/sch_generic: Shut up noise" -:30: ERROR:MISSING_SIGN_OFF: Missing Signed-off-b

[Intel-gfx] ✓ Fi.CI.BAT: success for C: Revert "net/sch_generic: Shut up noise"

== Series Details == Series: C: Revert "net/sch_generic: Shut up noise" URL : https://patchwork.freedesktop.org/series/60758/ State : success == Summary == CI Bug Log - changes from CI_DRM_6091 -> Patchwork_13029 Summary --- **SUCCES

Re: [Intel-gfx] Shutdown hooks

On Thursday, May 16, 2019 8:20:18 AM CEST Janusz Krzysztofik wrote: > On Wednesday, May 15, 2019 5:00:40 PM CEST Chris Wilson wrote: > > Janus, some old patches that may be of use for shutdown prior to kexec. > > -Chris > > Hi Chris, > > Thanks for sharing. > > I'm only not sure why you mentione

Re: [Intel-gfx] [PATCH i-g-t] benchmarks/gem_wsim: Randomise random seed

On 16/05/2019 19:58, Chris Wilson wrote: To avoid hitting the same rut on each benchmark run, start with a new random seed. To allow hitting the same rut again, let it be specified by the user. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin --- benchmarks/gem_wsim.c | 6 +- 1 file chan

Re: [RFC 1/3] kbuild: add support for ensuring headers are self-contained

Quoting Jani Nikula (2019-05-16 20:48:16) > diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib > index 8a1f64f17740..c2839de06485 100644 > --- a/scripts/Makefile.lib > +++ b/scripts/Makefile.lib > @@ -66,6 +66,9 @@ extra-y += $(patsubst %.dtb,%.dt.yaml, $(dtb-y)) > extra-$(CONFIG_OF_ALL_DTBS

Re: [Intel-gfx] [PATCH i-g-t] benchmarks/gem_wsim: Randomise random seed

Quoting Tvrtko Ursulin (2019-05-17 09:28:46) > > On 16/05/2019 19:58, Chris Wilson wrote: > > To avoid hitting the same rut on each benchmark run, start with a new > > random seed. To allow hitting the same rut again, let it be specified > > by the user. > > > > Signed-off-by: Chris Wilson > > C

Re: [Intel-gfx] Shutdown hooks

Quoting Janusz Krzysztofik (2019-05-17 09:04:12) > On Thursday, May 16, 2019 8:20:18 AM CEST Janusz Krzysztofik wrote: > > On Wednesday, May 15, 2019 5:00:40 PM CEST Chris Wilson wrote: > > > Janus, some old patches that may be of use for shutdown prior to kexec. > > > -Chris > > > > Hi Chris, > >

[Intel-gfx] ✓ Fi.CI.IGT: success for C: Revert "net/sch_generic: Shut up noise"

== Series Details == Series: C: Revert "net/sch_generic: Shut up noise" URL : https://patchwork.freedesktop.org/series/60758/ State : success == Summary == CI Bug Log - changes from CI_DRM_6091_full -> Patchwork_13029_full Summary ---

[Intel-gfx] [RFT] igt/gem_fence_thrash, gem_mmap_gtt: Don't let the device sleep

These tests are not intended to exercise runtime pm, but the device going to sleep in the middle of these tests can significantly slow them down as the GTT mmapping is torn down and must be rebuilt. This can be a major nuisance if the device autosuspends many times a second. These tests differ fro

Re: [Intel-gfx] [PATCH v7 09/11] drm: uevent for connector status change

On Thu, 16 May 2019 14:24:55 +0200 Daniel Vetter wrote: > On Thu, May 16, 2019 at 11:22:11AM +0300, Pekka Paalanen wrote: > > On Wed, 15 May 2019 10:24:49 +0200 > > Daniel Vetter wrote: > > > > > On Wed, May 15, 2019 at 10:37:31AM +0300, Pekka Paalanen wrote: > > > > On Tue, 14 May 2019 16:

[Intel-gfx] [PATCH 1/3] drm/i915/gvt: Set return value for ppgtt_populate error path

Caught by smatch: drivers/gpu/drm/i915//gvt/gtt.c:1106 ppgtt_populate_spt_by_guest_entry() error: uninitialized symbol 'ret'. Signed-off-by: Chris Wilson Cc: Zhenyu Wang --- drivers/gpu/drm/i915/gvt/gtt.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i9

[Intel-gfx] [PATCH 2/3] drm/i915/dp: Initialise locals for static analysis

Just to squelch an smatch warning that doesn't see the with_() being taken unconditionally: drivers/gpu/drm/i915//intel_dp.c:230 intel_dp_get_fia_supported_lane_count() error: uninitialized symbol 'lane_info'. drivers/gpu/drm/i915//intel_dp.c:5338 intel_digital_port_connected() error: uninitializ

[Intel-gfx] [PATCH 3/3] drm/i915/hdcp: Use both bits for device_count

Smatch spotted: drivers/gpu/drm/i915//intel_hdcp.c:1406 hdcp2_authenticate_repeater_topology() warn: should this be a bitwise op? and indeed looks to be suspect that we do need to use a bitwise or to combine the two register fields into one counter. Signed-off-by: Chris Wilson Cc: Ramalingam C

Re: [Intel-gfx] [PATCH i-g-t] benchmarks/gem_wsim: Randomise random seed

On 17/05/2019 09:37, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-05-17 09:28:46) On 16/05/2019 19:58, Chris Wilson wrote: To avoid hitting the same rut on each benchmark run, start with a new random seed. To allow hitting the same rut again, let it be specified by the user. Signed-off-b

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] benchmarks/gem_wsim: Randomise random seed

On Thu, 2019-05-16 at 19:58 +0100, Chris Wilson wrote: > To avoid hitting the same rut on each benchmark run, start with a new > random seed. To allow hitting the same rut again, let it be specified > by the user. > > Signed-off-by: Chris Wilson > Cc: Tvrtko Ursulin > --- > benchmarks/gem_wsim.

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Add N & CTS values for 10/12 bit deep color

On Wed, May 15, 2019 at 05:40:10PM +0300, Jani Nikula wrote: > On Tue, 02 Apr 2019, Aditya Swarup wrote: > > Adding N & CTS values for 10/12 bit deep color from Appendix C > > table in HDMI 2.0 spec. The correct values for N is not chosen > > automatically by hardware for deep color modes. > > > >

[Intel-gfx] [PATCH i-g-t 02/25] trace.pl: Ignore signaling on non i915 fences

From: Tvrtko Ursulin gem_wsim uses the sw_fence timeline and confuses the script. Signed-off-by: Tvrtko Ursulin --- scripts/trace.pl | 1 + 1 file changed, 1 insertion(+) diff --git a/scripts/trace.pl b/scripts/trace.pl index b7bbabc79f68..930e502ad8eb 100755 --- a/scripts/trace.pl +++ b/scri

[Intel-gfx] [PATCH i-g-t 07/25] gem_wsim: Use IGT uapi headers

From: Tvrtko Ursulin We are moving towards bumping the uAPI headers more often instead of using too much local struct/ioctl/param definitions since the latter are more challenging for rebase and maintenance. Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson --- benchmarks/gem_wsim.c | 1

[Intel-gfx] [PATCH i-g-t 04/25] trace.pl: Virtual engine support

From: Tvrtko Ursulin Add virtual/queue timelines to both stdout and HTML output. A new timeline is created for each queue/virtual engine to display associated requests in queued and runnable states. Once requests are submitted to a real engine for executing they show up on the physical engine ti

[Intel-gfx] [PATCH i-g-t 01/25] scripts/trace.pl: Fix after intel_engine_notify removal

From: Tvrtko Ursulin After the removal of engine global seqnos and the corresponding intel_engine_notify tracepoints the script needs to be adjusted to cope with the new state of things. To keep working it switches over using the dma_fence:dma_fence_signaled: tracepoint and keeps one extra inter

[Intel-gfx] [PATCH i-g-t 05/25] trace.pl: Virtual engine preemption support

From: Tvrtko Ursulin Use the 'completed?' tracepoint field to detect more robustly when a request has been preempted and remove it from the engine database if so. Otherwise the script can hit a scenario where the same global seqno will be mentioned multiple times (on an engine seqno) which abort

[Intel-gfx] [PATCH i-g-t 06/25] wsim/media-bench: i915 balancing

From: Tvrtko Ursulin Support i915 virtual engine from gem_wsim (-b i915) and media-bench.pl v2: * Add vm_destroy. (Chris) * Remove unneeded braces. (Chris) Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson --- benchmarks/gem_wsim.c | 302 +++-- sc

[Intel-gfx] [PATCH i-g-t 03/25] headers: bump

From: Tvrtko Ursulin Catch up to drm-tip headers. Signed-off-by: Tvrtko Ursulin --- include/drm-uapi/amdgpu_drm.h | 52 +++- include/drm-uapi/drm.h | 36 ++ include/drm-uapi/drm_mode.h| 4 +- include/drm-uapi/i915_drm.h| 209 - inclu

[Intel-gfx] [PATCH i-g-t 09/25] gem_wsim: More wsim_err

From: Tvrtko Ursulin A few more opportunities to compact the code by using the error logging helper. Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson --- benchmarks/gem_wsim.c | 54 --- 1 file changed, 15 insertions(+), 39 deletions(-) diff --gi

[Intel-gfx] [PATCH i-g-t 10/25] gem_wsim: Submit fence support

From: Tvrtko Ursulin Add support for submit fences in a way similar to how normal input fences are handled. Eg: 1.RCS.500-1000.0.0 1.VCS1.3000.s-1.0 1.VCS2.3000.s-2.0 Submit fences are signalled when the originating request enters the submission backend. Signed-off-by: Tvrtko Ursulin Re

[Intel-gfx] [PATCH i-g-t 11/25] gem_wsim: Extract str to engine lookup

From: Tvrtko Ursulin v2: * Remove redundant check. (Chris) Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson --- benchmarks/gem_wsim.c | 34 +- 1 file changed, 21 insertions(+), 13 deletions(-) diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c

[Intel-gfx] [PATCH i-g-t 00/25] Media scalability tooling

From: Tvrtko Ursulin Review feedback and some new stuff - most notably removal of a lot of hardcoded assumptions by adding engine discovery and speculative support to run on Icelake. Tvrtko Ursulin (25): scripts/trace.pl: Fix after intel_engine_notify removal trace.pl: Ignore signaling on no

[Intel-gfx] [PATCH i-g-t 15/25] gem_wsim: Engine map load balance command

From: Tvrtko Ursulin A new workload command for enabling a load balanced context map (aka Virtual Engine). Example usage: B.1 This turns on load balancing for context one, assuming it has already been configured with an engine map. Only DEFAULT engine specifier can be used with load balanced

[Intel-gfx] [PATCH i-g-t 16/25] gem_wsim: Engine bond command

From: Tvrtko Ursulin Engine bonds are an i915 uAPI applicable to load balanced contexts with engine map. They allow expression rules of engine selection between two contexts when submissions are also tied with submit fences. Please refer to the README for a more detailed description. v2: * Use

[Intel-gfx] [PATCH i-g-t 17/25] gem_wsim: Some more example workloads

From: Tvrtko Ursulin A few additional workloads useful for experimenting with scheduling. Signed-off-by: Tvrtko Ursulin Acked-by: Chris Wilson --- benchmarks/wsim/frame-split-60fps.wsim | 16 benchmarks/wsim/high-composited-game.wsim | 11 +++ benchmarks/wsim/m

[Intel-gfx] [PATCH i-g-t 13/25] gem_wsim: Save some lines by changing to implicit NULL checking

From: Tvrtko Ursulin We can improve the parsing loop readability a bit more by avoiding some line breaks caused by explicit NULL checks. Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson --- benchmarks/gem_wsim.c | 39 +++ 1 file changed, 15 insertion

[Intel-gfx] [PATCH i-g-t 18/25] gem_wsim: Infinite batch support

From: Tvrtko Ursulin For simulating frame split workloads it is useful to express a batch which ends at the same time as the parallel submission on the respective bonded engine. For this we add support for infinite batch durations and the batch terminate command ('T'). Syntax looks like this:

[Intel-gfx] [PATCH i-g-t 25/25] gem_wsim: Support Icelake parts

From: Tvrtko Ursulin On Icelake second vcs engine is vcs2 instead of vcs1 so add some logical to physical instance remapping based on engine discovery to support it. Signed-off-by: Tvrtko Ursulin --- benchmarks/gem_wsim.c | 30 -- 1 file changed, 24 insertions(+), 6

[Intel-gfx] [PATCH i-g-t 23/25] gem_wsim: Consolidate engine assignments into helpers

From: Tvrtko Ursulin This will allow applying the discovered engine configuration from a single place. Signed-off-by: Tvrtko Ursulin --- benchmarks/gem_wsim.c | 145 +- 1 file changed, 87 insertions(+), 58 deletions(-) diff --git a/benchmarks/gem_wsim.c

[Intel-gfx] [PATCH i-g-t 19/25] gem_wsim: Command line switch for specifying low slice count workloads

From: Tvrtko Ursulin A new command line switch ('-s') is added which toggles the low slice count mode for workloads following on the command line. This enables easy benchmarking of the effect of running the existing media workloads in parallel against another client. For example: ./gem_wsim -

[Intel-gfx] [PATCH i-g-t 14/25] gem_wsim: Compact int command parsing with a macro

From: Tvrtko Ursulin Parsing an integer workload descriptor field is a common pattern which we can extract to a helper macro and by doing so further improve the readability of the main parsing loop. Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson --- benchmarks/gem_wsim.c | 80 +++

[Intel-gfx] [PATCH i-g-t 12/25] gem_wsim: Engine map support

From: Tvrtko Ursulin Support new i915 uAPI for configuring contexts with engine maps. Please refer to the README file for more detailed explanation. v2: * Allow defining engine maps by class. Signed-off-by: Tvrtko Ursulin --- benchmarks/gem_wsim.c | 211 +++-

[Intel-gfx] [PATCH i-g-t 24/25] gem_wsim: Discover engines

From: Tvrtko Ursulin Instead of hardcoding the VCS balancing engines, discover, both with the new engines query, or with the legacy get_param in the fallback case, so class based addressing always works. Signed-off-by: Tvrtko Ursulin --- benchmarks/gem_wsim.c | 180

[Intel-gfx] [PATCH i-g-t 08/25] gem_wsim: Factor out common error handling

From: Tvrtko Ursulin There is a repeated pattern with error handling which can be moved to a macro to for better readability in the command parsing loop. Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson --- benchmarks/gem_wsim.c | 244 +++--- 1 file

[Intel-gfx] [PATCH i-g-t 21/25] gem_wsim: Allow RCS virtual engine with SSEU control

From: Tvrtko Ursulin To allow exercising the SSEU configuration in combination with Virtual Engine, allow RCS to be specified in the engine map and use appropriate index based addressing when applying SSEU configuration to it. Signed-off-by: Tvrtko Ursulin --- benchmarks/gem_wsim.c | 51 ++

[Intel-gfx] [PATCH i-g-t 22/25] tests/i915_query: Engine discovery tests

From: Tvrtko Ursulin Test the new engine discovery query. Signed-off-by: Tvrtko Ursulin --- tests/i915/i915_query.c | 247 1 file changed, 247 insertions(+) diff --git a/tests/i915/i915_query.c b/tests/i915/i915_query.c index 7d0c0e3a061c..ecbec3ae141d

[Intel-gfx] [PATCH i-g-t 20/25] gem_wsim: Per context SSEU control

From: Tvrtko Ursulin A new workload command ('S') is added which allows per context slice (re-)configuration. v2: * Only query device SSEU on first use. (Chris) Signed-off-by: Tvrtko Ursulin --- benchmarks/gem_wsim.c | 83 -- benchmarks/wsim/README |

Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: Add N & CTS values for 10/12 bit deep color

On Fri, 17 May 2019, Aditya Swarup wrote: > On Wed, May 15, 2019 at 05:40:10PM +0300, Jani Nikula wrote: >> On Tue, 02 Apr 2019, Aditya Swarup wrote: >> > Adding N & CTS values for 10/12 bit deep color from Appendix C >> > table in HDMI 2.0 spec. The correct values for N is not chosen >> > automa

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 15/25] gem_wsim: Engine map load balance command

Quoting Tvrtko Ursulin (2019-05-17 12:25:16) > @@ -184,3 +186,19 @@ Example: > M.1.VCS > > This sets up the engine map to all available VCS class engines. > + > +Context load balancing > +-- > + > +Context load balancing (aka Virtual Engine) is an i915 feature where the > d

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 24/25] gem_wsim: Discover engines

Hi Tvrtko, > +static int > +__i915_query(int i915, struct drm_i915_query *q) > +{ > + if (igt_ioctl(i915, DRM_IOCTL_I915_QUERY, q)) > + return -errno; > + return 0; > +} > + > +static int > +__i915_query_items(int i915, struct drm_i915_query_item *items, uint32_t > n_items) >

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 24/25] gem_wsim: Discover engines

On 17/05/2019 12:39, Andi Shyti wrote: Hi Tvrtko, +static int +__i915_query(int i915, struct drm_i915_query *q) +{ + if (igt_ioctl(i915, DRM_IOCTL_I915_QUERY, q)) + return -errno; + return 0; +} + +static int +__i915_query_items(int i915, struct drm_i915_query_item *i

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 15/25] gem_wsim: Engine map load balance command

On 17/05/2019 12:38, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-05-17 12:25:16) @@ -184,3 +186,19 @@ Example: M.1.VCS This sets up the engine map to all available VCS class engines. + +Context load balancing +-- + +Context load balancing (aka Virtual Engine) is

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 24/25] gem_wsim: Discover engines

Hi Tvrtko, > > > +static int > > > +__i915_query(int i915, struct drm_i915_query *q) > > > +{ > > > + if (igt_ioctl(i915, DRM_IOCTL_I915_QUERY, q)) > > > + return -errno; > > > + return 0; > > > +} > > > + > > > +static int > > > +__i915_query_items(int i915, struct drm_i915_query_item *i

Re: [Intel-gfx] [PATCH 2/3] drm/i915/dp: Initialise locals for static analysis

On Fri, May 17, 2019 at 11:22:24AM +0100, Chris Wilson wrote: > Just to squelch an smatch warning that doesn't see the with_() being > taken unconditionally: > drivers/gpu/drm/i915//intel_dp.c:230 intel_dp_get_fia_supported_lane_count() > error: uninitialized symbol 'lane_info'. > drivers/gpu/drm/

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 24/25] gem_wsim: Discover engines

On Fri, May 17, 2019 at 12:25:25PM +0100, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin > > Instead of hardcoding the VCS balancing engines, discover, both with the > new engines query, or with the legacy get_param in the fallback case, so > class based addressing always works. > > Signed-off-by:

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 24/25] gem_wsim: Discover engines

On 17/05/2019 13:10, Andi Shyti wrote: On Fri, May 17, 2019 at 12:25:25PM +0100, Tvrtko Ursulin wrote: From: Tvrtko Ursulin Instead of hardcoding the VCS balancing engines, discover, both with the new engines query, or with the legacy get_param in the fallback case, so class based addressing

Re: [Intel-gfx] [PATCH 1/5] drm/i915: Mark semaphores as complete on unsubmit out if payload was started

On 15/05/2019 14:00, Chris Wilson wrote: Avoid charging us for the presumed busywait if the request was preempted after successfully using semaphores to reduce inter-engine latency. v2: Bump the priority to reflect the lack of semaphores now required. References: ca6e56f654e7 ("drm/i915: Disab

Re: [Intel-gfx] [PATCH 2/5] drm/i915: Truly bump ready tasks ahead of busywaits

On 15/05/2019 14:00, Chris Wilson wrote: In commit b7404c7ecb38 ("drm/i915: Bump ready tasks ahead of busywaits"), I tried cutting a corner in order to not install a signal for each of our dependencies, and only listened to requests on which we were intending to busywait. The compromise that was

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/gvt: Set return value for ppgtt_populate error path

== Series Details == Series: series starting with [1/3] drm/i915/gvt: Set return value for ppgtt_populate error path URL : https://patchwork.freedesktop.org/series/60769/ State : warning == Summary == $ dim checkpatch origin/drm-tip 06cf16cbe5f5 drm/i915/gvt: Set return value for ppgtt_popula

Re: [Intel-gfx] [PATCH 3/3] drm/i915/hdcp: Use both bits for device_count

On 2019-05-17 at 11:22:25 +0100, Chris Wilson wrote: > Smatch spotted: > drivers/gpu/drm/i915//intel_hdcp.c:1406 > hdcp2_authenticate_repeater_topology() warn: should this be a bitwise op? > > and indeed looks to be suspect that we do need to use a bitwise or to > combine the two register fields

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Downgrade NEWCLIENT to non-preemptive

On 15/05/2019 14:00, Chris Wilson wrote: Commit 1413b2bc0717 ("drm/i915: Trim NEWCLIENT boosting") had the intended consequence of not allowing a sequence of work that merely crossed into a new engine the privilege to be promoted to NEWCLIENT What do you mean with crossed into a new engine? At

Re: [Intel-gfx] [PATCH 1/3] drm/i915/gvt: Set return value for ppgtt_populate error path

On 2019-05-17 at 11:22:23 +0100, Chris Wilson wrote: > Caught by smatch: > drivers/gpu/drm/i915//gvt/gtt.c:1106 ppgtt_populate_spt_by_guest_entry() > error: uninitialized symbol 'ret'. > > Signed-off-by: Chris Wilson > Cc: Zhenyu Wang > --- > drivers/gpu/drm/i915/gvt/gtt.c | 4 +++- > 1 file c

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] benchmarks/gem_wsim: Randomise random seed

On 17/05/2019 11:55, Ser, Simon wrote: On Thu, 2019-05-16 at 19:58 +0100, Chris Wilson wrote: To avoid hitting the same rut on each benchmark run, start with a new random seed. To allow hitting the same rut again, let it be specified by the user. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 24/25] gem_wsim: Discover engines

> > > +static void query_engines(void) > > > +{ > > > + struct i915_engine_class_instance *engines; > > > + unsigned int num; > > > + > > > + if (__engines_queried) > > > + return; > > > + > > > + __engines_queried = true; > > > + > > > + if (!has_query(fd) || !has_engine_query(fd)) { [...

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Add HDR Metadata Parsing and handling in DRM layer (rev10)

On Thu, May 16, 2019 at 01:18:15PM +, Shankar, Uma wrote: > > > >> > >> >-Original Message- > >> >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > >> >Sent: Thursday, May 16, 2019 1:02 AM > >> >To: Shankar, Uma > >> >Cc: intel-gfx@lists.freedesktop.org > >> >Subject: Re:

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 24/25] gem_wsim: Discover engines

On 17/05/2019 14:02, Andi Shyti wrote: +static void query_engines(void) +{ + struct i915_engine_class_instance *engines; + unsigned int num; + + if (__engines_queried) + return; + + __engines_queried = true; + + if (!has_query(fd) || !has_engine_query(

Re: [Intel-gfx] [PATCH 1/3] drm/i915/gvt: Set return value for ppgtt_populate error path

On 2019-05-17 at 18:31:42 +0530, Ramalingam C wrote: > On 2019-05-17 at 11:22:23 +0100, Chris Wilson wrote: > > Caught by smatch: > > drivers/gpu/drm/i915//gvt/gtt.c:1106 ppgtt_populate_spt_by_guest_entry() > > error: uninitialized symbol 'ret'. > > > > Signed-off-by: Chris Wilson > > Cc: Zhenyu

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Add HDR Metadata Parsing and handling in DRM layer (rev10)

On 17/05/2019 16:04, Ville Syrjälä wrote: > On Thu, May 16, 2019 at 01:18:15PM +, Shankar, Uma wrote: >> >> > -Original Message- > From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] > Sent: Thursday, May 16, 2019 1:02 AM > To: Shankar, Uma > Cc: intel-g

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Add HDR Metadata Parsing and handling in DRM layer (rev10)

>-Original Message- >From: Peres, Martin >Sent: Friday, May 17, 2019 6:39 PM >To: Ville Syrjälä ; Shankar, Uma > >Cc: intel-gfx@lists.freedesktop.org >Subject: Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Add HDR Metadata Parsing and >handling >in DRM layer (rev10) > >On 17/05/2019 16:04, Vi

Re: [Intel-gfx] [igt-dev] [PATCH i-g-t 15/25] gem_wsim: Engine map load balance command

Quoting Tvrtko Ursulin (2019-05-17 12:52:36) > > On 17/05/2019 12:38, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2019-05-17 12:25:16) > >> @@ -184,3 +186,19 @@ Example: > >> M.1.VCS > >> > >> This sets up the engine map to all available VCS class engines. > >> + > >> +Context load bala

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Add HDR Metadata Parsing and handling in DRM layer (rev10)

On Fri, May 17, 2019 at 01:17:05PM +, Shankar, Uma wrote: > > > >-Original Message- > >From: Peres, Martin > >Sent: Friday, May 17, 2019 6:39 PM > >To: Ville Syrjälä ; Shankar, Uma > > > >Cc: intel-gfx@lists.freedesktop.org > >Subject: Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Add HDR

Re: [Intel-gfx] [PATCH v7 3/6] drm/i915/dp: Program VSC Header and DB for Pixel Encoding/Colorimetry Format

Op 10-05-2019 om 03:53 schreef Gwan-gyeong Mun: > Function intel_pixel_encoding_setup_vsc handles vsc header and data block > setup for pixel encoding / colorimetry format. > > Setup VSC header and data block in function intel_pixel_encoding_setup_vsc > for pixel encoding / colorimetry format as pe

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Downgrade NEWCLIENT to non-preemptive

Quoting Tvrtko Ursulin (2019-05-17 13:55:48) > > On 15/05/2019 14:00, Chris Wilson wrote: > > Commit 1413b2bc0717 ("drm/i915: Trim NEWCLIENT boosting") had the > > intended consequence of not allowing a sequence of work that merely > > crossed into a new engine the privilege to be promoted to NEWC

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Add HDR Metadata Parsing and handling in DRM layer (rev10)

>-Original Message- >From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com] >Sent: Friday, May 17, 2019 6:54 PM >To: Shankar, Uma >Cc: Peres, Martin ; intel-gfx@lists.freedesktop.org >Subject: Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for Add HDR Metadata Parsing and >handling >in DRM la

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gvt: Set return value for ppgtt_populate error path

== Series Details == Series: series starting with [1/3] drm/i915/gvt: Set return value for ppgtt_populate error path URL : https://patchwork.freedesktop.org/series/60769/ State : success == Summary == CI Bug Log - changes from CI_DRM_6093 -> Patchwork_13030 ===

Re: [Intel-gfx] [PATCH xf86-video-intel v2 2/2] sna: Support 10bpc gamma via the GAMMA_LUT crtc property

On Thu, May 16, 2019 at 09:54:55PM +0200, Mario Kleiner wrote: > On Fri, Apr 26, 2019 at 6:32 PM Ville Syrjala > wrote: > > > > From: Ville Syrjälä > > > > Probe the GAMMA_LUT/GAMMA_LUT_SIZE props and utilize them when > > the running with > 8bpc. > > > > v2: s/sna_crtc_id/__sna_crtc_id/ in DBG s

[Intel-gfx] [PATCH xf86-video-intel v3 2/2] sna: Support 10bpc gamma via the GAMMA_LUT crtc property

From: Ville Syrjälä Probe the GAMMA_LUT/GAMMA_LUT_SIZE props and utilize them when the running with > 8bpc. v2: s/sna_crtc_id/__sna_crtc_id/ in DBG since we have a sna_crtc v3: Fix the vg "bluered" typo (Mario) This time I even build tested with vg support Cc: Mario Kleiner Signed-off-by:

Re: [Intel-gfx] [v11 08/12] drm/i915: Enable infoframes on GLK+ for HDR

On Thu, May 16, 2019 at 07:40:13PM +0530, Uma Shankar wrote: > From: Ville Syrjälä > > This patch enables infoframes on GLK+ to be > used to send HDR metadata to HDMI sink. > > v2: Addressed Shashank's review comment. > > v3: Addressed Shashank's review comment. > > v4: Added Shashank's RB. >

Re: [Intel-gfx] [v11 06/12] drm/i915: Write HDR infoframe and send to panel

On Thu, May 16, 2019 at 07:40:11PM +0530, Uma Shankar wrote: > Enable writing of HDR metadata infoframe to panel. > The data will be provid by usersapace compositors, based > on blending policies and passsed to driver through a blob > property. > > v2: Rebase > > v3: Fixed a warning message > >

[Intel-gfx] [RFC PATCH] drm/i915: Tolerate file owned GEM contexts on hot unbind

From: Janusz Krzysztofik During i915_driver_unload(), GEM contexts are verified restrictively inside i915_gem_fini() if they don't consume shared resources which should be cleaned up before the driver is released. If those checks don't result in kernel panic, one more check is performed at the e

Re: [Intel-gfx] [v11 05/12] drm/i915: Attach HDR metadata property to connector

On Thu, May 16, 2019 at 07:40:10PM +0530, Uma Shankar wrote: > Attach HDR metadata property to connector object. > > v2: Rebase > > v3: Updated the property name as per updated name > while creating hdr metadata property > > Signed-off-by: Uma Shankar > Reviewed-by: Shashank Sharma > --- > dr

Re: [Intel-gfx] [PATCH 4/5] drm/i915: Downgrade NEWCLIENT to non-preemptive

On 17/05/2019 14:30, Chris Wilson wrote: Quoting Tvrtko Ursulin (2019-05-17 13:55:48) On 15/05/2019 14:00, Chris Wilson wrote: Commit 1413b2bc0717 ("drm/i915: Trim NEWCLIENT boosting") had the intended consequence of not allowing a sequence of work that merely crossed into a new engine the pr

Re: [Intel-gfx] [PATCH 5/5] drm/i915/execlists: Drop promotion on unsubmit

On 15/05/2019 14:00, Chris Wilson wrote: With the disappearance of NEWCLIENT, we no longer need to provide the priority boost on preemption in order to prevent repeated gazumping, and we can remove the dead code. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin --- drivers/gpu/drm/i915/gt/int

Re: [Intel-gfx] [RFC PATCH] drm/i915: Tolerate file owned GEM contexts on hot unbind

Quoting Janusz Krzysztofik (2019-05-17 15:06:17) > From: Janusz Krzysztofik > > During i915_driver_unload(), GEM contexts are verified restrictively > inside i915_gem_fini() if they don't consume shared resources which > should be cleaned up before the driver is released. If those checks > don't

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Tolerate file owned GEM contexts on hot unbind

== Series Details == Series: drm/i915: Tolerate file owned GEM contexts on hot unbind URL : https://patchwork.freedesktop.org/series/60782/ State : success == Summary == CI Bug Log - changes from CI_DRM_6095 -> Patchwork_13031 Summary -

Re: [Intel-gfx] [PATCH 3/5] drm/i915: Bump signaler priority on adding a waiter

On 15/05/2019 14:00, Chris Wilson wrote: The handling of the no-preemption priority level imposes the restriction that we need to maintain the implied ordering even though preemption is disabled. Otherwise we may end up with an AB-BA deadlock across multiple engine due to a real preemption event

Re: [Intel-gfx] [RFC 4/7] drm/i915: move and rename i915_runtime_pm

On 5/16/19 3:42 PM, Chris Wilson wrote: Quoting Chris Wilson (2019-05-16 23:10:10) Quoting Chris Wilson (2019-05-16 23:07:43) Quoting Daniele Ceraolo Spurio (2019-05-16 22:56:31) diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.h b/drivers/gpu/drm/i915/intel_runtime_pm.h index b964ca7af9c

Re: [Intel-gfx] [RFC 4/7] drm/i915: move and rename i915_runtime_pm

Quoting Daniele Ceraolo Spurio (2019-05-17 16:27:26) > > > On 5/16/19 3:42 PM, Chris Wilson wrote: > > Quoting Chris Wilson (2019-05-16 23:10:10) > >> Quoting Chris Wilson (2019-05-16 23:07:43) > >>> Quoting Daniele Ceraolo Spurio (2019-05-16 22:56:31) > diff --git a/drivers/gpu/drm/i915/int

[Intel-gfx] [v12 05/12] drm/i915: Attach HDR metadata property to connector

Attach HDR metadata property to connector object. v2: Rebase v3: Updated the property name as per updated name while creating hdr metadata property v4: Added platform check as suggested by Ville. Signed-off-by: Uma Shankar Reviewed-by: Shashank Sharma --- drivers/gpu/drm/i915/intel_hdmi.c |

[Intel-gfx] [v12 06/12] drm/i915: Write HDR infoframe and send to panel

Enable writing of HDR metadata infoframe to panel. The data will be provid by usersapace compositors, based on blending policies and passsed to driver through a blob property. v2: Rebase v3: Fixed a warning message v4: Addressed Shashank's review comments v5: Rebase. Added infoframe calculation

[Intel-gfx] [v12 08/12] drm/i915: Enable infoframes on GLK+ for HDR

From: Ville Syrjälä This patch enables infoframes on GLK+ to be used to send HDR metadata to HDMI sink. v2: Addressed Shashank's review comment. v3: Addressed Shashank's review comment. v4: Added Shashank's RB. v5: Dropped hdr_metadata_change check while modeset, as per Ville's suggestion. v

[Intel-gfx] [v3 0/3] Extend BT2020 support in iCSC and fixes

This series adds support for BT2020 YCbCr to RGB conversion using input CSC. This also fixes issues with BT601 and BT709 coefficients. v2: Fixed Ville's review comments. v3: Rebase. Uma Shankar (3): drm/i915/icl: Handle YCbCr to RGB conversion for BT2020 case drm/i915/icl: Fix Y pre-offset f

[Intel-gfx] [v3 2/3] drm/i915/icl: Fix Y pre-offset for Full Range YCbCr

Fixed Y Pre-offset in case of Full Range YCbCr. Reviewed-by: Ville Syrjälä Suggested-by: Ville Syrjälä Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/intel_sprite.c | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gp

[Intel-gfx] [v3 1/3] drm/i915/icl: Handle YCbCr to RGB conversion for BT2020 case

Currently input csc for YCbCR to RGB conversion handles only BT601 and Bt709. Extending it to support BT2020 as well. v2: Fixed the co-efficients for LR to FR conversion, as suggested by Ville. v3: Fixed Y Pre-offset in case of Full Range YCbCr as suggested by Ville. v4: Split the v2 and v3 chan

[Intel-gfx] [v3 3/3] drm/i915/icl: Fixed Input CSC Co-efficients for BT601/709

Input CSC Co-efficients for BT601 and BT709 YCbCR to RGB conversion were slightly off. Fixed the same. v2: Fixed the co-eficients as there was issue with reference matrix, spotted by Ville. Signed-off-by: Uma Shankar --- drivers/gpu/drm/i915/intel_sprite.c | 24 1 file

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add HDR Metadata Parsing and handling in DRM layer (rev14)

== Series Details == Series: Add HDR Metadata Parsing and handling in DRM layer (rev14) URL : https://patchwork.freedesktop.org/series/25091/ State : warning == Summary == $ dim checkpatch origin/drm-tip 7c0463e5827f drm: Add HDR source metadata property -:62: CHECK:PARENTHESIS_ALIGNMENT: Alig

Re: [Intel-gfx] [PATCH 1/2] drm/i915: Re-add enable_rc6 modparam

On Thu, May 16, 2019 at 03:49:19PM +, Summers, Stuart wrote: > On Thu, 2019-05-16 at 18:42 +0300, Jani Nikula wrote: > > On Thu, 16 May 2019, "Summers, Stuart" > > wrote: > > > On Thu, 2019-05-16 at 12:59 +0300, Jani Nikula wrote: > > > > On Tue, 14 May 2019, Rodrigo Vivi wrote: > > > > > One

[Intel-gfx] [PATCH] drm/i915: added i2c symlink to hdmi connector

Currently, the i2c adapter was available only under DP connectors. This patch adds i2c adapter symlink to hdmi connector in order to make this behaviour consistent. The initial motivation of this patch was to make igt i2c subtest patch [1] work on all connectors. [1]: https://patchwork.freedeskt

[Intel-gfx] [PATCH 7/7] drm/i915/uc: Don't forget to prepare GuC for the reset

When we reset engines using ALL_ENGINES mask, we will do full GPU reset and GuC will be also affected. Let GuC be prepared for upcoming reset. Signed-off-by: Michal Wajdeczko Cc: Chris Wilson Cc: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/gt/intel_reset.c | 4 1 file changed, 4 inser

[Intel-gfx] [PATCH 5/7] drm/i915/uc: Skip reset preparation if GuC is already dead

We may skip reset preparation steps if GuC is already sanitized. Signed-off-by: Michal Wajdeczko Cc: Chris Wilson Cc: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/intel_uc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_u

[Intel-gfx] [PATCH 2/7] drm/i915/uc: Explicitly sanitize GuC/HuC on failure and finish

Explicitly sanitize GuC/HuC on load failure and when we finish using them to make sure our fw state tracking is always correct. While around, use new helper in uc_reset_prepare. Signed-off-by: Michal Wajdeczko Cc: Chris Wilson Cc: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/intel_uc.c | 1

[Intel-gfx] [PATCH 6/7] drm/i915/uc: Stop GuC submission during reset prepare

Knowing that GuC will be reset soon, perform only minimal cleanup actions (ie. doorbells) without talking with GuC. Signed-off-by: Michal Wajdeczko Cc: Chris Wilson Cc: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/intel_guc_submission.c | 25 + drivers/gpu/drm/i915/intel

[Intel-gfx] [PATCH 0/7] GuC fixes

Misc GuC fixes for upcoming 32.0.3 Michal Wajdeczko (7): drm/i915/uc: Use GuC firmware status helper drm/i915/uc: Explicitly sanitize GuC/HuC on failure and finish drm/i915/uc: Skip GuC HW unwinding if GuC is already dead drm/i915/uc: Stop talking with GuC when resetting drm/i915/uc: Ski

[Intel-gfx] [PATCH 1/7] drm/i915/uc: Use GuC firmware status helper

We already have helper function for checking GuC firmware load status. Replace existing open-coded checks. Signed-off-by: Michal Wajdeczko Cc: Chris Wilson --- drivers/gpu/drm/i915/intel_uc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_uc

[Intel-gfx] [PATCH 4/7] drm/i915/uc: Stop talking with GuC when resetting

Knowing that GuC will be reset soon, we may stop all communication immediately without doing graceful cleanup as it is not needed. Signed-off-by: Michal Wajdeczko Cc: Chris Wilson Cc: Daniele Ceraolo Spurio --- drivers/gpu/drm/i915/intel_guc_ct.h | 5 + drivers/gpu/drm/i915/intel_uc.c

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