On Tue, Apr 09, 2019 at 04:08:49PM +1000, Stephen Rothwell wrote:
> Hi all,
>
> After merging the drm-misc tree, today's linux-next build (powerpc
> allyesconfig) failed like this:
>
> drivers/gpu/drm/cirrus/cirrus.c: In function 'cirrus_fb_blit_rect':
> drivers/gpu/drm/cirrus/cirrus.c:310:25: er
On Tue, Apr 09, 2019 at 11:34:10AM +1000, Stephen Rothwell wrote:
> Hi all,
>
> Today's linux-next merge of the drm-misc tree got conflicts in:
>
> drivers/gpu/drm/cirrus/cirrus_drv.h
> drivers/gpu/drm/cirrus/cirrus_ttm.c
>
> between commits:
>
> aa8e2435b3d4 ("drm/ttm: Define a single DR
== Series Details ==
Series: IRQ initialization debloat and conversion to uncore
URL : https://patchwork.freedesktop.org/series/59202/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5891_full -> Patchwork_12734_full
Summary
== Series Details ==
Series: Core-for-CI:ICL_only Disable ACPI idle driver (rev2)
URL : https://patchwork.freedesktop.org/series/59170/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5892 -> Patchwork_12735
Summary
---
Hi Gerd,
On Tue, 9 Apr 2019 09:22:18 +0200 Gerd Hoffmann wrote:
>
> On Tue, Apr 09, 2019 at 04:08:49PM +1000, Stephen Rothwell wrote:
> > Hi all,
> >
> > After merging the drm-misc tree, today's linux-next build (powerpc
> > allyesconfig) failed like this:
> >
> > drivers/gpu/drm/cirrus/cirrus.
On Tue, Apr 09, 2019 at 06:08:55PM +1000, Stephen Rothwell wrote:
> Hi Gerd,
>
> > >drm_fb_memcpy_dstclip(__io_virt(cirrus->vram),
> > > ^
> > > __do_irq
> >
> > Probably just a missing arm/io.h include.
>
> I assume you meant asm/i
VBT version 212 defined HDMI max. bit-rate 2.97Gbps is 0x02 and 1.65Gbps
is 0x04, so changed HDMI_MAX_DATA_RATE_297/HDMI_MAX_DATA_RATE_165 to map
correct values
Per VBT BSpec definition in HDMI max. data rate, Bits7-5 is HDMI max. data
rate 000=Default, 001=2.97Gbps, 010=1.65Gbps, so HDMI_MAX_DA
== Series Details ==
Series: drm/i915: Update HDMI max TMDS data rate definition for VBT
URL : https://patchwork.freedesktop.org/series/59220/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5895 -> Patchwork_12736
Summary
--
Generated using make headers_install from the drm-next
tree - git://anongit.freedesktop.org/drm/drm
branch - drm-next
commit - 14d2bd53a47a7e1cb3e03d00a6b952734cf90f3f
The changes were as follows :-
core: (drm.h, drm_fourcc.h, drm_mode.h)
- Added 'struct drm_syncobj_transfer', 'struct drm_syncobj
On Tuesday, 2019-04-09 11:35:14 +, Ayan Halder wrote:
> Generated using make headers_install from the drm-next
> tree - git://anongit.freedesktop.org/drm/drm
> branch - drm-next
> commit - 14d2bd53a47a7e1cb3e03d00a6b952734cf90f3f
>
> The changes were as follows :-
>
> core: (drm.h, drm_fourcc
On Tuesday, 2019-04-09 12:59:13 +0100, Eric Engestrom wrote:
> On Tuesday, 2019-04-09 11:35:14 +, Ayan Halder wrote:
> > Generated using make headers_install from the drm-next
> > tree - git://anongit.freedesktop.org/drm/drm
> > branch - drm-next
> > commit - 14d2bd53a47a7e1cb3e03d00a6b952734cf
On Tue, Apr 09, 2019 at 06:07:08PM +0800, Chiou, Cooper wrote:
> VBT version 212 defined HDMI max. bit-rate 2.97Gbps is 0x02 and 1.65Gbps
> is 0x04, so changed HDMI_MAX_DATA_RATE_297/HDMI_MAX_DATA_RATE_165 to map
> correct values
Eh what? Did someone just change the interpretation of these bits?
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/intel_color.c | 7 +++
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4af815c..861db
Thanks to Jani N, Matt and Ville for the review comments. Hopefully
I have addressed all the current review comments and ready to receive more :)
In this patch series, added state checker to validate gamma_lut values. This
reads hardware state, and compares the originally requested
state to the st
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_reg.h| 3 +++
drivers/gpu/drm/i915/intel_color.c | 39 ++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6e1fe5e..415b90d 100
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_reg.h| 3 +++
drivers/gpu/drm/i915/intel_color.c | 51 ++
2 files changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 00e0356..c86cbc1 100
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_reg.h| 3 +++
drivers/gpu/drm/i915/intel_color.c | 49 +-
2 files changed, 51 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 415b9
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_reg.h| 3 +++
drivers/gpu/drm/i915/intel_color.c | 39 ++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c86cbc1..6e1fe5e 100
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/intel_color.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index e398a60..e18388e 100644
--- a/drivers/gpu/drm/i915/intel_color.c
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 7ecfb7d..3282bc7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/intel_color.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 0fdbae3..e398a60 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_reg.h| 3 +++
drivers/gpu/drm/i915/intel_color.c | 42 --
2 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c424
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/intel_color.c | 50 --
1 file changed, 48 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index e18388e..0352ca5 100644
--- a/drivers/gpu/d
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/intel_color.c | 49
drivers/gpu/drm/i915/intel_display.c | 10
drivers/gpu/drm/i915/intel_drv.h | 3 +++
3 files changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/
Thanks to Jani N, Matt and Ville for the review comments. Hopefully
I have addressed all the current review comments and ready to receive more :)
In this patch series, added state checker to validate gamma_lut values. This
reads hardware state, and compares the originally requested
state to the st
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_reg.h| 3 +++
drivers/gpu/drm/i915/intel_color.c | 49 +-
2 files changed, 51 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 415b9
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/intel_color.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 0fdbae3..e398a60 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/intel_color.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index e398a60..e18388e 100644
--- a/drivers/gpu/drm/i915/intel_color.c
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_reg.h| 3 +++
drivers/gpu/drm/i915/intel_color.c | 42 --
2 files changed, 43 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c424
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_reg.h| 3 +++
drivers/gpu/drm/i915/intel_color.c | 51 ++
2 files changed, 54 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 00e0356..c86cbc1 100
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/intel_color.c | 7 +++
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 4af815c..861db
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_reg.h| 3 +++
drivers/gpu/drm/i915/intel_color.c | 39 ++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c86cbc1..6e1fe5e 100
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/intel_color.c | 49
drivers/gpu/drm/i915/intel_display.c | 10
drivers/gpu/drm/i915/intel_drv.h | 3 +++
3 files changed, 62 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/i915_reg.h| 3 +++
drivers/gpu/drm/i915/intel_color.c | 39 ++
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6e1fe5e..415b90d 100
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/intel_color.c | 50 --
1 file changed, 48 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index e18388e..0352ca5 100644
--- a/drivers/gpu/d
Signed-off-by: Swati Sharma
---
drivers/gpu/drm/i915/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 7ecfb7d..3282bc7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i
On Tue, Apr 09, 2019 at 01:29:41PM +, Jim Zhang wrote:
> Villie:
>
> What is Intel's plan for the colorkey patch? Does Intel have any plan to
> review and release?
There is no real plan at this time. But if you have a use case
for it I can try to harass people until someone reviews it :)
If we have two tasks running on xcs0 and xcs1 independently, but who
queue subsequent work onto rcs, we may insert semaphores before the rcs
work and pick unwisely which task to run first. To maximise throughput,
we want to run on rcs whichever task is ready first. Conversely, if we
pick wrongly th
On Tue, Apr 09, 2019 at 04:46:24PM +0300, Ville Syrjälä wrote:
> On Tue, Apr 09, 2019 at 01:29:41PM +, Jim Zhang wrote:
> > Villie:
> >
> > What is Intel's plan for the colorkey patch? Does Intel have any plan to
> > review and release?
>
> There is no real plan at this time. But if you ha
On Tue, Apr 09, 2019 at 01:59:21PM +, Jim Zhang wrote:
> Nice, do you have any sample code for it?
https://cgit.freedesktop.org/xorg/driver/xf86-video-intel/tree/src/sna/sna_video_sprite.c
is the only userspace code we have that uses the colorkey.
>
> Thanks,
>
> Jim
>
>
> Caterpillar: Co
On Tue, Apr 09, 2019 at 02:14:49PM +, Jim Zhang wrote:
> Once I pre-configure the colorkey, am I able to enable and disable it? If
> colorkey can be enabled/disabled after that might meet my requirement
Not atomically with other updates.
>
> Thanks,
>
> Jim
>
>
> Caterpillar: Confidentia
Consider two tasks that are running in parallel on a pair of engines
(vcs0, vcs1), but then must complete on a shared engine (rcs0). To
maximise throughput, we want to run the first ready task on rcs0 (i.e.
the first task that completes on either of vcs0 or vcs1). When using
semaphores, however, we
From: Ville Syrjälä
Our SDVO audio support is pretty bogus. We can't push audio over the
SDVO bus, so trying to enable audio in the SDVO control register doesn't
do anything. In fact it looks like the SDVO encoder will always mix in
the audio coming over HDA, and there's no (at least documented)
From: Ville Syrjälä
It's much easier to figure out why the SDVO encoder refuses to cooperate
if we can see what status we got back.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_sdvo.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i
From: Ville Syrjälä
Pass the length returned by intel_sdvo_read_infoframe() to
hdmi_infoframe_unpack() so that we don't try to unpack any
leftover stack garbage.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_sdvo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Ville Syrjälä
Before we go writing the infoframe let's make sure we have
the space for it. Not that it really matters since the write
loop would just terminate early in that case.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_sdvo.c | 3 +++
1 file changed, 3 insertions(+)
From: Ville Syrjälä
Here's a series to fix SDVO HDMI audio handling which got broken
quite a while ago. I also tossed in a few extra cleanups.
Ville Syrjälä (7):
drm/i915/sdvo: Fix AVI infoframe TX rate readout
drm/i915/sdvo: Implement proper HDMI audio support for SDVO
drm/i915: Rename SD
From: Ville Syrjälä
The AVI infoframe readout code currently issues a
SDVO_CMD_GET_HBUF_TXRATE before SDVO_CMD_SET_HBUF_INDEX, which is
not the correct order for these two operations. So far this wasn't
a problem since we left the index pointing at the AVI infoframe
buffer at the end of the modes
From: Ville Syrjälä
Pass the length returned by hdmi_infoframe_pack_only() to
intel_sdvo_write_infoframe() so that we don't end up writing
stack garbage into the hbuf.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_sdvo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: Ville Syrjälä
The "audio enable" bit on the SDVO/HDMI control register is only meant
for HDMI. Audio is never delivered over the SDVO bus. Rename the define
to reflect this fact.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_reg.h | 2 +-
drivers/gpu/drm/i915/intel_hdmi.c
On Tue, Apr 09, 2019 at 02:24:03PM +, Jim Zhang wrote:
> What about if I disable interrupt when changing the colorkey? This will
> solve the atomic issue. I think we only change colorkey or enable/disable
> colorkey once a while. If disabling interrupt work, I will disable interrupt
> and
Consider two tasks that are running in parallel on a pair of engines
(vcs0, vcs1), but then must complete on a shared engine (rcs0). To
maximise throughput, we want to run the first ready task on rcs0 (i.e.
the first task that completes on either of vcs0 or vcs1). When using
semaphores, however, we
== Series Details ==
Series: drm/i915: Update HDMI max TMDS data rate definition for VBT
URL : https://patchwork.freedesktop.org/series/59220/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5895_full -> Patchwork_12736_full
On 09/04/2019 16:29, Chris Wilson wrote:
Consider two tasks that are running in parallel on a pair of engines
(vcs0, vcs1), but then must complete on a shared engine (rcs0). To
maximise throughput, we want to run the first ready task on rcs0 (i.e.
the first task that completes on either of vcs0
On 09/04/2019 14:56, Chris Wilson wrote:
If we have two tasks running on xcs0 and xcs1 independently, but who
queue subsequent work onto rcs, we may insert semaphores before the rcs
work and pick unwisely which task to run first. To maximise throughput,
we want to run on rcs whichever task is re
Quoting Tvrtko Ursulin (2019-04-09 16:38:37)
>
> On 09/04/2019 16:29, Chris Wilson wrote:
> > Consider two tasks that are running in parallel on a pair of engines
> > (vcs0, vcs1), but then must complete on a shared engine (rcs0). To
> > maximise throughput, we want to run the first ready task on
Hi Ville,
The bits is 5-7 means it’s 001x for 2.97Gbps, and 010x for 1.65Gbps.
So correct value should be 2 not 1 for HDMI_MAX_DATA_RATE_297.
And HDMI_MAX_DATA_RATE_165 is 4 not 2.
I checked kernel i915 log and modified VBT to limit HDMI 1.4 from HDMI 2.0 then
found this error. And I r
On 4/9/2019 8:29 AM, Anshuman Gupta wrote:
There were few system hung observed while running i915_pm_rpm igt test.
FDO https://bugs.freedesktop.org/show_bug.cgi?id=108840
Root cause is believed to due to page fault in ACPI idle driver.
(FDO comment 18).
It has been suggested by Daniel Vetter to d
== Series Details ==
Series: adding state checker for gamma lut values
URL : https://patchwork.freedesktop.org/series/59226/
State : failure
== Summary ==
Applying: drm/i915: Introduce vfunc intel_get_color_config to create hw lut
Using index info to reconstruct a base tree...
M drivers/
== Series Details ==
Series: drm/i915: adding state checker for gamma lut values (rev3)
URL : https://patchwork.freedesktop.org/series/58039/
State : failure
== Summary ==
Applying: drm/i915: Introduce vfunc intel_get_color_config to create hw lut
Using index info to reconstruct a base tree...
On Tue, Apr 09, 2019 at 03:46:20PM +, Chiou, Cooper wrote:
> Hi Ville,
>
> The bits is 5-7 means it’s 001x for 2.97Gbps, and 010x for 1.65Gbps.
> So correct value should be 2 not 1 for HDMI_MAX_DATA_RATE_297.
No. The bitfield is defined as something:3.
> And HDMI_MAX_DATA_RATE_165
On gen11 the recommended rc6 threshold differs from previous
gens, apply it.
References: bspec#52070
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_p
Enable media sampler powergate as recommended.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++--
drivers/gpu/drm/i915/intel_pm.c | 4 +++-
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
in
In order not to inflate gen9 rc6 enabling sequence with
gen11 specifics, use a separate function for it.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_pm.c | 72 +
1 file changed, 72 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drive
There is no video turbo mode for gen11, so don't set it.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_pm.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 47f98e064de5..d6abba5c0b32 100
Use a recommended idle hysteresis for media and render powergates.
References: bspec#52070
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_pm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
in
Unlike previous gens, we already hold the irq_lock on
entering the rps handler so we can't use it as it is.
Make a gen11 specific rps interrupt handler without
locking.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_irq.c | 18 +-
1 file changed, 17 insertions(+), 1
With gen11 the interrupt registers are shared between 2 engines,
with Engine1 instance being upper word and Engine0 instance being
lower. Annoyingly gen11 selected the pm interrupts to be in the
Engine1 instance.
Rectify the situation by shifting the access accordingly,
based on gen.
Bugzilla: ht
Quoting Mika Kuoppala (2019-04-09 17:13:06)
> Use a recommended idle hysteresis for media and render powergates.
>
> References: bspec#52070
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/intel_pm.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/driver
>-Original Message-
>From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
>Jonas
>Karlman
>Sent: Monday, April 8, 2019 3:51 PM
>To: Shankar, Uma ; intel-gfx@lists.freedesktop.org; dri-
>de...@lists.freedesktop.org
>Cc: seanp...@chromium.org; emil.l.veli...@gmail.
Enable writing of HDR metadata infoframe to panel.
The data will be provid by usersapace compositors, based
on blending policies and passsed to driver through a blob
property.
v2: Rebase
v3: Fixed a warning message
v4: Addressed Shashank's review comments
v5: Rebase. Added infoframe calculation
This patch adds a blob property to get HDR metadata
information from userspace. This will be send as part
of AVI Infoframe to panel.
It also implements get() and set() functions for HDR output
metadata property.The blob data is received from userspace and
saved in connector state, the same is retu
From: Ville Syrjälä
ADD HLG EOTF to the list of EOTF transfer functions supported.
Hybrid Log-Gamma (HLG) is a high dynamic range (HDR) standard.
HLG defines a nonlinear transfer function in which the lower
half of the signal values use a gamma curve and the upper half
of the signal values use a
This patch series enables HDR support in drm. It basically defines
HDR metadata structures, property to pass content (after blending)
metadata from user space compositors to driver.
Dynamic Range and Mastering infoframe creation and sending.
ToDo:
1. We need to get the color framework in place fo
This patch enables modeset whenever HDR metadata
needs to be updated to sink.
v2: Addressed Shashank's review comments.
v3: Added Shashank's RB.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/i915/intel_atomic.c | 14 +-
d
From: Ville Syrjälä
This patch enables infoframes on GLK+ to be
used to send HDR metadata to HDMI sink.
v2: Addressed Shashank's review comment.
v3: Addressed Shashank's review comment.
v4: Added Shashank's RB.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
Reviewed-by: Shashank Sh
Attach HDR metadata property to connector object.
v2: Rebase
v3: Updated the property name as per updated name
while creating hdr metadata property
Signed-off-by: Uma Shankar
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/i915/intel_hdmi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
Enable Dynamic Range and Mastering Infoframe for HDR
content, which is defined in CEA 861.3 spec.
The metadata will be computed based on blending
policy in userspace compositors and passed as a connector
property blob to driver. The same will be sent as infoframe
to panel which support HDR.
Added
HDR metadata block is introduced in CEA-861.3 spec.
Parsing the same to get the panel's HDR metadata.
v2: Rebase and added Ville's POC changes to the patch.
v3: No Change
v4: Addressed Shashank's review comments
v5: Addressed Shashank's comment and added his RB.
v6: Addressed Jonas Karlman rev
HDR metadata requires a infoframe to be set. Due to fastset,
full modeset is not performed hence adding it to update_pipe
to handle that.
Signed-off-by: Uma Shankar
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/i915/intel_ddi.c | 13 +
drivers/gpu/drm/i915/intel_hdmi.c | 7
BYT/CHT doesn't support DRM Infoframe. This caused
a WARN_ON due to a missing CASE while executing
intel_hdmi_infoframes_enabled function. This patch
fixes the same.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_hdmi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu
Quoting Mika Kuoppala (2019-04-09 17:13:09)
> Unlike previous gens, we already hold the irq_lock on
> entering the rps handler so we can't use it as it is.
>
> Make a gen11 specific rps interrupt handler without
> locking.
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_irq.c
== Series Details ==
Series: drm/i915: Fix SDVO HDMI audio
URL : https://patchwork.freedesktop.org/series/59233/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5897 -> Patchwork_12739
Summary
---
**SUCCESS**
No reg
Quoting Mika Kuoppala (2019-04-09 17:13:10)
> With gen11 the interrupt registers are shared between 2 engines,
> with Engine1 instance being upper word and Engine0 instance being
> lower. Annoyingly gen11 selected the pm interrupts to be in the
> Engine1 instance.
Sounds weird, but I can't fault t
Quoting Mika Kuoppala (2019-04-09 17:13:04)
> In order not to inflate gen9 rc6 enabling sequence with
> gen11 specifics, use a separate function for it.
And disable_rc6 remains as simple as before.
> Signed-off-by: Mika Kuoppala
Reviewed-by: Chris Wilson
-Chris
Quoting Mika Kuoppala (2019-04-09 17:13:08)
> There is no video turbo mode for gen11, so don't set it.
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/intel_pm.c | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/
Quoting Mika Kuoppala (2019-04-09 17:13:07)
> Enable media sampler powergate as recommended.
>
> Signed-off-by: Mika Kuoppala
> ---
> drivers/gpu/drm/i915/i915_reg.h | 5 +++--
> drivers/gpu/drm/i915/intel_pm.c | 4 +++-
> 2 files changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/driver
On Tue, 09 Apr 2019 18:13:05 +0200, Mika Kuoppala
wrote:
On gen11 the recommended rc6 threshold differs from previous
gens, apply it.
References: bspec#52070
Is this correct number? I found it at 33149
And note that we are using different tag:
Bspec: 33149
Signed-off-by: Mika Kuoppala
On Tue, 09 Apr 2019 18:13:04 +0200, Mika Kuoppala
wrote:
[snip]
+
+ /*
+* 2c: Program Coarse Power Gating Policies.
+*
+* Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we
+* use instead is a more conservative estimate for the maximum ti
Quoting Michal Wajdeczko (2019-04-09 17:57:58)
> On Tue, 09 Apr 2019 18:13:04 +0200, Mika Kuoppala
> wrote:
>
> [snip]
>
> > +
> > + /*
> > + * 2c: Program Coarse Power Gating Policies.
> > + *
> > + * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we
> > +
== Series Details ==
Series: drm/i915: Bump ready tasks ahead of busywaits (rev2)
URL : https://patchwork.freedesktop.org/series/59232/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5897 -> Patchwork_12740
Summary
---
== Series Details ==
Series: drm/i915: Update HDMI max TMDS data rate definition for VBT (rev2)
URL : https://patchwork.freedesktop.org/series/59220/
State : failure
== Summary ==
Applying: drm/i915: Update HDMI max TMDS data rate definition for VBT
error: corrupt patch at line 13
error: could
== Series Details ==
Series: series starting with [1/7] drm/i915: Use dedicated rc6 enabling
sequence for gen11
URL : https://patchwork.freedesktop.org/series/59237/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
18e95bd1432c drm/i915: Use dedicated rc6 enabling sequence for ge
Em ter, 2019-04-09 às 00:44 +, Patchwork escreveu:
> == Series Details ==
>
> Series: IRQ initialization debloat and conversion to uncore
> URL : https://patchwork.freedesktop.org/series/59202/
> State : warning
>
> == Summary ==
>
> $ dim checkpatch origin/drm-tip
> 7f73d1fe31bb drm/i915:
As intel_runtime_pm_get/_put may be called from any blockable context,
we need to avoid allowing reclaim from our mallocs, as we need to
avoid tainting any mutexes held by the callers (as they may themselves
not allow for allocations as they are taken in the shrinker).
<4> [435.339331] WARNING: po
== Series Details ==
Series: series starting with [1/7] drm/i915: Use dedicated rc6 enabling
sequence for gen11
URL : https://patchwork.freedesktop.org/series/59237/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5897 -> Patchwork_12742
== Series Details ==
Series: Add HDR Metadata Parsing and handling in DRM layer (rev8)
URL : https://patchwork.freedesktop.org/series/25091/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6f71d6db5493 drm: Add HDR source metadata property
-:67: CHECK:PARENTHESIS_ALIGNMENT: Align
On Mon, Apr 08, 2019 at 05:37:27PM -0700, Paulo Zanoni wrote:
> The whole point of having macros here is for the token pasting
> necessary to automatically have IMR, IIR and IER selected. We don't
> really need or want all the inlining that happens as a consequence.
> The good thing about the curre
On Tue, Apr 09, 2019 at 10:34:22AM -0700, Paulo Zanoni wrote:
> Em ter, 2019-04-09 às 00:44 +, Patchwork escreveu:
> > == Series Details ==
> >
> > Series: IRQ initialization debloat and conversion to uncore
> > URL : https://patchwork.freedesktop.org/series/59202/
> > State : warning
> >
>
== Series Details ==
Series: Add HDR Metadata Parsing and handling in DRM layer (rev8)
URL : https://patchwork.freedesktop.org/series/25091/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5897 -> Patchwork_12743
Summary
1 - 100 of 154 matches
Mail list logo
