== Series Details ==
Series: drm/i915: add immutable zpos plane properties
URL : https://patchwork.freedesktop.org/series/58761/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5840 -> Patchwork_12638
Summary
---
**SUC
On Tue, Apr 02, 2019 at 01:55:03PM +0800, Qiang Yu wrote:
> Thanks, patch is:
> Reviewed-by: Qiang Yu
Good time to get started with committing patches? In general it's kinda
confusing if the maintainer r-bs a patch, but doesn't say whether/when/how
it gets merged. Big chance the patch will get lo
On Fri, Mar 29, 2019 at 10:20:27AM +0100, Daniel Vetter wrote:
> Interpreting it as a 0.16 fixed point means we can't accurately
> represent 1.0. Which is one of the values we really should be able to
> represent.
>
> Since most (all?) luts have lower precision this will only affect
> rounding of
On Mon, Apr 01, 2019 at 04:39:24PM +0200, Guillaume Tucker wrote:
> The MIPS architecture doesn't provide the hardware atomics that are
> required for the "create-clear" sub-test such as
> __sync_add_and_fetch(). As a simple and pragmatic solution, disable
> this sub-test when building for MIPS.
On Tue, Apr 2, 2019 at 3:57 PM Daniel Vetter wrote:
>
> On Tue, Apr 02, 2019 at 01:55:03PM +0800, Qiang Yu wrote:
> > Thanks, patch is:
> > Reviewed-by: Qiang Yu
>
> Good time to get started with committing patches? In general it's kinda
> confusing if the maintainer r-bs a patch, but doesn't say
On Tue, Apr 02, 2019 at 04:59:37PM +0800, Qiang Yu wrote:
> On Tue, Apr 2, 2019 at 3:57 PM Daniel Vetter wrote:
> >
> > On Tue, Apr 02, 2019 at 01:55:03PM +0800, Qiang Yu wrote:
> > > Thanks, patch is:
> > > Reviewed-by: Qiang Yu
> >
> > Good time to get started with committing patches? In genera
Hi,
Here's gvt-fixes for 5.1-rc4 which includes misc fixes for
vGPU display plane size calculation, shadow mm pin count,
error recovery path for workload create and one kerneldoc
fix which I missed to include before.
Thanks.
--
The following changes since commit 26cdaac4793c49357d2c731f2190632ce
== Series Details ==
Series: drm/i915: Prefault before locking pages in shmem_pwrite
URL : https://patchwork.freedesktop.org/series/58832/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5854 -> Patchwork_12647
Summary
--
== Series Details ==
Series: drm/i915: Only emit one semaphore per request
URL : https://patchwork.freedesktop.org/series/58836/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5854 -> Patchwork_12648
Summary
---
**SUC
== Series Details ==
Series: series starting with [1/2] drm/i915: Move intel_engine_mask_t around
for use by i915_request_types.h
URL : https://patchwork.freedesktop.org/series/58840/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
17162f9150fe drm/i915: Move intel_engine_mask_t
== Series Details ==
Series: series starting with [1/2] drm/i915: Move intel_engine_mask_t around
for use by i915_request_types.h
URL : https://patchwork.freedesktop.org/series/58840/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Move intel
On Tue, Apr 02, 2019 at 10:50:06AM +1100, Stephen Rothwell wrote:
> +++ b/drivers/gpu/drm/lima/lima_ctx.c
> @@ -23,7 +23,7 @@ int lima_ctx_create(struct lima_device *dev, struct
> lima_ctx_mgr *mgr, u32 *id)
> goto err_out0;
> }
>
> - err = xa_alloc(&mgr->handles,
On Tue, Apr 02, 2019 at 01:55:03PM +0800, Qiang Yu wrote:
> Thanks, patch is:
> Reviewed-by: Qiang Yu
This looks like a fairly naive conversion from the old IDR API to the
XArray API. You should be able to remove mgr->lock entirely, relying on
the xa_lock for synchronising free and get. If you
== Series Details ==
Series: series starting with [1/2] drm/i915: Move intel_engine_mask_t around
for use by i915_request_types.h
URL : https://patchwork.freedesktop.org/series/58840/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5854 -> Patchwork_12649
==
== Series Details ==
Series: series starting with [1/3] drm/i915: Move intel_engine_mask_t around
for use by i915_request_types.h
URL : https://patchwork.freedesktop.org/series/58842/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
632e3b34f6b5 drm/i915: Move intel_engine_mask_t
== Series Details ==
Series: series starting with [1/3] drm/i915: Move intel_engine_mask_t around
for use by i915_request_types.h
URL : https://patchwork.freedesktop.org/series/58842/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Move intel
== Series Details ==
Series: drm/i915: add immutable zpos plane properties
URL : https://patchwork.freedesktop.org/series/58761/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5840_full -> Patchwork_12638_full
Summary
--
== Series Details ==
Series: series starting with [1/3] drm/i915: Move intel_engine_mask_t around
for use by i915_request_types.h
URL : https://patchwork.freedesktop.org/series/58842/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5854 -> Patchwork_12650
==
Quoting Lionel Landwerlin (2019-03-25 12:34:44)
> Ping?
The last patch should be squashed, I think we want to minimize the
amount of versions. Or do you intend to backport only portion of
the series somewhere?
Can you link to the userspace side changes?
Regards, Joonas
>
> On 26/02/2019 14:29,
== Series Details ==
Series: drm/i915: FBC needs vblank before enable / disable.
URL : https://patchwork.freedesktop.org/series/58843/
State : failure
== Summary ==
Applying: drm/i915: FBC needs vblank before enable / disable.
error: sha1 information is lacking or useless
(drivers/gpu/drm/i91
From: Clinton Taylor
v2: Fix commit msg to reflect why issue occurs(Jani)
Set GCP_COLOR_INDICATION only when we set 10/12 bit deep color.
Changing settings from 10/12 bit deep color to 8 bit(& vice versa)
doesn't work correctly using xrandr max bpc property. When we
connect a monitor which suppo
Adding N & CTS values for 10/12 bit deep color from Appendix C
table in HDMI 2.0 spec. The correct values for N is not chosen
automatically by hardware for deep color modes.
v2: Remove redundant code and make it generic.(Jani)
Signed-off-by: Aditya Swarup
Cc: Clint Taylor
Cc: Ville Syrjälä
Cc:
== Series Details ==
Series: gpu:drm: Remove duplicate headers (rev2)
URL : https://patchwork.freedesktop.org/series/58844/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d36613f503ec gpu:drm: Remove duplicate headers
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit
On Fri, 29 Mar 2019, Randy Dunlap wrote:
> On 3/28/19 8:18 PM, Stephen Rothwell wrote:
>> Hi all,
>>
>> Changes since 20190328:
>>
>> The pidfd tree lost its build failures.
>>
>
> on x86_64, when # CONFIG_ACPI is not set/enabled:
>
> ld: drivers/gpu/drm/i915/intel_panel.o: in function
> `inte
On Mon, Apr 01, 2019 at 08:18:13PM +, Jim Zhang wrote:
> Hi Sir/Madam:
>
> I am using the open source Baytrail gpu drm driver.
>
> Linux kernel version 3.10.61:
> Libdrm package: 2.4.97
>
> When calling function
> properties = drmModeObjectGetProperties(drmfd, plane_id,
> DRM_MODE_OBJECT_P
On 01/04/2019 16:57, Chris Wilson wrote:
We want to use intel_engine_mask_t inside i915_request.h, which means
extracting it from the general header file mess and placing it inside a
types.h. A knock on effect is that the compiler wants to warn about
type-contraction of ALL_ENGINES into intel_en
Quoting Simon Ser (2019-03-30 00:19:25)
> From: emersion
Please fix your From: field.
> This adds basic immutable support for the zpos property. The zpos increases
> from bottom to top: primary, sprites, cursor.
>
> Signed-off-by: Simon Ser
This is just Ville's patch rebased, so it's incorrec
On 01/04/2019 16:57, Chris Wilson wrote:
Ideally we only need one semaphore per ring to accommodate waiting on
multiple engines in parallel. However, since we do not know which fences
we will finally be waiting on, we emit a semaphore for every fence. It
turns out to be quite easy to trick ourse
Quoting Tvrtko Ursulin (2019-04-02 13:36:02)
>
> On 01/04/2019 16:57, Chris Wilson wrote:
> > diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h
> > b/drivers/gpu/drm/i915/i915_scheduler_types.h
> > index 5c94b3eb5c81..aa3aeae5404a 100644
> > --- a/drivers/gpu/drm/i915/i915_scheduler_types.
On Mon, 1 Apr 2019 at 14:39, Chris Wilson wrote:
>
> If the user passes in a pointer to a GGTT mmaping of the same buffer
> being written to, we can hit a deadlock in acquiring the shmemfs page
> (once as the write destination and then as the read source).
And also shmem_fault, so cpu mmaping?
>
== Series Details ==
Series: Add Multi Segment Gamma Support (rev2)
URL : https://patchwork.freedesktop.org/series/58169/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
75ad704a2b21 drm: Add gamma mode caps property
659fe8427470 drm/i915: Define color lut range structure
-:61: E
On Mon, 1 Apr 2019 at 13:46, Chris Wilson wrote:
>
> If we caused a fault on a GEM buffer while in the middle of trying to
> write/read into that buffer, we could conceivably deadlock (e.g.
> recursing on struct_mutex if we are not careful). Exercise these cases
> by supplying a fresh mmap to prea
On Tue, Apr 02, 2019 at 05:14:39AM -0700, Aditya Swarup wrote:
> From: Clinton Taylor
>
> v2: Fix commit msg to reflect why issue occurs(Jani)
> Set GCP_COLOR_INDICATION only when we set 10/12 bit deep color.
>
> Changing settings from 10/12 bit deep color to 8 bit(& vice versa)
> doesn't work c
Quoting Matthew Auld (2019-04-02 13:39:20)
> On Mon, 1 Apr 2019 at 14:39, Chris Wilson wrote:
> >
> > If the user passes in a pointer to a GGTT mmaping of the same buffer
> > being written to, we can hit a deadlock in acquiring the shmemfs page
> > (once as the write destination and then as the re
== Series Details ==
Series: gpu:drm: Remove duplicate headers (rev2)
URL : https://patchwork.freedesktop.org/series/58844/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5854 -> Patchwork_12652
Summary
---
**SUCCESS*
Quoting Chris Wilson (2019-04-02 13:54:11)
> Quoting Matthew Auld (2019-04-02 13:39:20)
> > On Mon, 1 Apr 2019 at 14:39, Chris Wilson wrote:
> > >
> > > If the user passes in a pointer to a GGTT mmaping of the same buffer
> > > being written to, we can hit a deadlock in acquiring the shmemfs page
== Series Details ==
Series: Add Multi Segment Gamma Support (rev2)
URL : https://patchwork.freedesktop.org/series/58169/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5854 -> Patchwork_12653
Summary
---
**FAILURE**
On 25/03/2019 09:03, Chris Wilson wrote:
Start acquiring the logical intel_context and using that as our primary
means for request allocation. This is the initial step to allow us to
avoid requiring struct_mutex for request allocation along the
perma-pinned kernel context, but it also provides a
On Tue, Apr 2, 2019 at 7:21 PM Matthew Wilcox wrote:
>
> On Tue, Apr 02, 2019 at 10:50:06AM +1100, Stephen Rothwell wrote:
> > +++ b/drivers/gpu/drm/lima/lima_ctx.c
> > @@ -23,7 +23,7 @@ int lima_ctx_create(struct lima_device *dev, struct
> > lima_ctx_mgr *mgr, u32 *id)
> >
Cc: Stephen Rothwell
Cc: Matthew Wilcox
Cc: Daniel Vetter
Signed-off-by: Qiang Yu
---
drivers/gpu/drm/lima/lima_ctx.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/lima/lima_ctx.c b/drivers/gpu/drm/lima/lima_ctx.c
index c8d12f7c6894..22fff6caa961 100644
--
On Tue, Apr 2, 2019 at 7:26 PM Matthew Wilcox wrote:
>
> On Tue, Apr 02, 2019 at 01:55:03PM +0800, Qiang Yu wrote:
> > Thanks, patch is:
> > Reviewed-by: Qiang Yu
>
> This looks like a fairly naive conversion from the old IDR API to the
> XArray API. You should be able to remove mgr->lock entire
On Tue, Apr 02, 2019 at 09:56:08PM +0800, Qiang Yu wrote:
> On Tue, Apr 2, 2019 at 7:26 PM Matthew Wilcox wrote:
> >
> > On Tue, Apr 02, 2019 at 01:55:03PM +0800, Qiang Yu wrote:
> > > Thanks, patch is:
> > > Reviewed-by: Qiang Yu
> >
> > This looks like a fairly naive conversion from the old IDR
On Tuesday, April 2, 2019 3:35 PM, Joonas Lahtinen
wrote:
> Quoting Simon Ser (2019-03-30 00:19:25)
>
> > From: emersion cont...@emersion.fr
>
> Please fix your From: field.
Gah.
> > This adds basic immutable support for the zpos property. The zpos increases
> > from bottom to top: primary, spr
On 01/04/2019 17:26, Chris Wilson wrote:
For more intel_engine_mask_t detangling. This time so that we can use
intel_engine_mask_t inside the scheduling structs.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/i915_priolist_types.h
Quoting Tvrtko Ursulin (2019-04-02 15:47:34)
>
> On 01/04/2019 17:26, Chris Wilson wrote:
> > For more intel_engine_mask_t detangling. This time so that we can use
> > intel_engine_mask_t inside the scheduling structs.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/Makefi
On 25/03/2019 09:03, Chris Wilson wrote:
In order to separate the reservation phase of building a request from
its emission phase, we need to pull some of the request alloc activities
from deep inside i915_request to the surface, GEM_EXECBUFFER.
Signed-off-by: Chris Wilson
---
drivers/gpu/dr
>-Original Message-
>From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
>Ville
>Syrjälä
>Sent: Friday, March 29, 2019 7:35 PM
>To: Shankar, Uma
>Cc: Syrjala, Ville ; liviu.du...@arm.com; intel-
>g...@lists.freedesktop.org; emil.l.veli...@gmail.com; dri-
>de...
On 02/04/2019 14:49, Joonas Lahtinen wrote:
Quoting Lionel Landwerlin (2019-03-25 12:34:44)
Ping?
The last patch should be squashed, I think we want to minimize the
amount of versions. Or do you intend to backport only portion of
the series somewhere?
No backport intended :)
Can you link
On 4/2/19 5:53 AM, Ville Syrjälä wrote:
On Tue, Apr 02, 2019 at 05:14:39AM -0700, Aditya Swarup wrote:
From: Clinton Taylor
v2: Fix commit msg to reflect why issue occurs(Jani)
Set GCP_COLOR_INDICATION only when we set 10/12 bit deep color.
Changing settings from 10/12 bit deep color to 8 bi
On 4/2/19 8:54 AM, Clinton Taylor wrote:
On 4/2/19 5:53 AM, Ville Syrjälä wrote:
On Tue, Apr 02, 2019 at 05:14:39AM -0700, Aditya Swarup wrote:
From: Clinton Taylor
v2: Fix commit msg to reflect why issue occurs(Jani)
Set GCP_COLOR_INDICATION only when we set 10/12 bit deep color.
Changing
== Series Details ==
Series: drm/i915: Prefault before locking pages in shmem_pwrite
URL : https://patchwork.freedesktop.org/series/58832/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5854_full -> Patchwork_12647_full
Summ
== Series Details ==
Series: drm/i915: Finish the GAMMA_LUT stuff (rev3)
URL : https://patchwork.freedesktop.org/series/58698/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5856 -> Patchwork_12654
Summary
---
**SUCCE
On Tue, Apr 02, 2019 at 09:25:58AM -0700, Clinton Taylor wrote:
>
> On 4/2/19 8:54 AM, Clinton Taylor wrote:
> >
> > On 4/2/19 5:53 AM, Ville Syrjälä wrote:
> >> On Tue, Apr 02, 2019 at 05:14:39AM -0700, Aditya Swarup wrote:
> >>> From: Clinton Taylor
> >>>
> >>> v2: Fix commit msg to reflect why
== Series Details ==
Series: drm/i915: initialize uncore->lock in uncore_init (rev2)
URL : https://patchwork.freedesktop.org/series/58853/
State : failure
== Summary ==
Applying: drm/i915: initialize uncore->lock in uncore_init
error: sha1 information is lacking or useless (drivers/gpu/drm/i91
== Series Details ==
Series: drm/i915: Only emit one semaphore per request
URL : https://patchwork.freedesktop.org/series/58836/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5854_full -> Patchwork_12648_full
Summary
--
== Series Details ==
Series: series starting with [v3,1/2] drm/i915/icl: Ungate ddi clocks before IO
enable (rev3)
URL : https://patchwork.freedesktop.org/series/58527/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5856 -> Patchwork_12656
=
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/icl: Set GCP_COLOR_INDICATION
only for 10/12 bit deep color
URL : https://patchwork.freedesktop.org/series/58870/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
925957d2a043 drm/i915/icl: Set GCP_COLOR_INDICATI
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/icl: Set GCP_COLOR_INDICATION
only for 10/12 bit deep color
URL : https://patchwork.freedesktop.org/series/58870/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5856 -> Patchwork_12657
== Series Details ==
Series: series starting with [1/2] drm/i915: Move intel_engine_mask_t around
for use by i915_request_types.h
URL : https://patchwork.freedesktop.org/series/58840/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5854_full -> Patchwork_12649_full
== Series Details ==
Series: linux-next: build failure after merge of the drm-misc tree (rev2)
URL : https://patchwork.freedesktop.org/series/58857/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5856 -> Patchwork_12658
Summ
Enable Dynamic Range and Mastering Infoframe for HDR
content, which is defined in CEA 861.3 spec.
The metadata will be computed based on blending
policy in userspace compositors and passed as a connector
property blob to driver. The same will be sent as infoframe
to panel which support HDR.
Added
This patch enables modeset whenever HDR metadata
needs to be updated to sink.
v2: Addressed Shashank's review comments.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_atomic.c | 14 +-
drivers/gpu/drm/i915/intel_hdmi.c | 9 +
2 fil
HDR metadata requires a infoframe to be set. Due to fastset,
full modeset is not performed hence adding it to update_pipe
to handle that.
Signed-off-by: Uma Shankar
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/i915/intel_ddi.c | 13 +
1 file changed, 13 insertions(+)
diff --git
This patch adds a blob property to get HDR metadata
information from userspace. This will be send as part
of AVI Infoframe to panel.
It also implements get() and set() functions for HDR output
metadata property.The blob data is received from userspace and
saved in connector state, the same is retu
From: Ville Syrjälä
This patch enables infoframes on GLK+ to be
used to send HDR metadata to HDMI sink.
v2: Addressed Shashank's review comment.
v3: Addressed Shashank's review comment.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 4
Enable writing of HDR metadata infoframe to panel.
The data will be provid by usersapace compositors, based
on blending policies and passsed to driver through a blob
property.
v2: Rebase
v3: Fixed a warning message
v4: Addressed Shashank's review comments
v5: Rebase. Added infoframe calculation
This patch series enables HDR support in drm. It basically defines
HDR metadata structures, property to pass content (after blending)
metadata from user space compositors to driver.
Dynamic Range and Mastering infoframe creation and sending.
ToDo:
1. We need to get the color framework in place fo
HDR metadata block is introduced in CEA-861.3 spec.
Parsing the same to get the panel's HDR metadata.
v2: Rebase and added Ville's POC changes to the patch.
v3: No Change
v4: Addressed Shashank's review comments
v5: Addressed Shashank's comment and added his RB.
Signed-off-by: Uma Shankar
Rev
From: Ville Syrjälä
ADD HLG EOTF to the list of EOTF transfer functions supported.
Hybrid Log-Gamma (HLG) is a high dynamic range (HDR) standard.
HLG defines a nonlinear transfer function in which the lower
half of the signal values use a gamma curve and the upper half
of the signal values use a
Attach HDR metadata property to connector object.
v2: Rebase
v3: Updated the property name as per updated name
while creating hdr metadata property
Signed-off-by: Uma Shankar
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/i915/intel_hdmi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
Encapsulate the uncore early init and be consistent with the
"_early" naming.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Chris Wilson
Cc: Paulo Zanoni
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 3 ++-
drivers/gpu/drm/i915/intel_uncore.c | 4
drivers/gpu/drm/i915/i
Add "_mmio" postfix to be consistent from the init/fini phase they're
called from.
Signed-off-by: Daniele Ceraolo Spurio
Suggested-by: Chris Wilson
Cc: Chris Wilson
Cc: Paulo Zanoni
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.c | 8
drivers/gpu/drm/i915/intel_unc
== Series Details ==
Series: Add HDR Metadata Parsing and handling in DRM layer (rev7)
URL : https://patchwork.freedesktop.org/series/25091/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2d47c2744ec3 drm: Add HDR source metadata property
-:62: CHECK:PARENTHESIS_ALIGNMENT: Align
== Series Details ==
Series: Add HDR Metadata Parsing and handling in DRM layer (rev7)
URL : https://patchwork.freedesktop.org/series/25091/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm: Add HDR source metadata property
Okay!
Commit: drm: Parse
Hi Uma.
Noticed a kerneldoc nit while browsign the code.
Maybe try to let kernel doc tell you if there are more.
Sam
>
> /**
> + * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI AVI infoframe with
> + * HDR metadata from userspace
> + * @f
Hi Uma.
Some kerneldoc nits below.
Sam
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -599,6 +599,13 @@ struct drm_connector_state {
>* and the connector bpc limitations obtained from edid.
>*/
> u8 max_bpc;
> +
> + /**
> + * @
Looks good.
Reviewed-by: Clint Taylor
On 3/27/19 3:13 AM, Imre Deak wrote:
From: Ville Syrjälä
If we have only a single active pipe and the cdclk change only requires
the cd2x divider to be updated bxt+ can do the update with forcing a full
modeset on the pipe. Try to hook that up.
v2:
- W
== Series Details ==
Series: Add HDR Metadata Parsing and handling in DRM layer (rev7)
URL : https://patchwork.freedesktop.org/series/25091/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5856 -> Patchwork_12659
Summary
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: add intel_uncore_init_early
URL : https://patchwork.freedesktop.org/series/58891/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5856 -> Patchwork_12660
Su
For certain eDP 1.4 panels, we need to use max lane count for the
link training to succeed.
This patch adds a EDID quirk for such eDP panels using
their vendor ID and product ID to force using max lane count in the driver.
Cc: Clint Taylor
Cc: Ville Syrjälä
Tested-by: Albert Astals Cid
Tested-
Some eDP 1.4 panels cannot use the optimized fast and narrow pipe
config approach, but they need to use th maximum supported lane count
for the link training to succeed.
There is a DRM EDID quirk for such panels that gets set after reading
their corresponding EDID.
So if it is set, this patch force
On 4/2/19 2:52 PM, Manasi Navare wrote:
For certain eDP 1.4 panels, we need to use max lane count for the
link training to succeed.
This patch adds a EDID quirk for such eDP panels using
their vendor ID and product ID to force using max lane count in the driver.
Cc: Clint Taylor
Cc: Ville Syr
On 4/2/19 2:52 PM, Manasi Navare wrote:
Some eDP 1.4 panels cannot use the optimized fast and narrow pipe
config approach, but they need to use th maximum supported lane count
for the link training to succeed.
There is a DRM EDID quirk for such panels that gets set after reading
their correspond
On Wed, Mar 20, 2019 at 2:20 PM Souza, Jose wrote:
>
> On Wed, 2019-03-20 at 14:15 -0700, Bob Paauwe wrote:
> > Unlike ICL, all of the output ports are combo phys so just return
> > true in intel_port_is_combophy for all EHL ports to indicate that.
> >
> > v2: Return false in intel_port_is_tc sinc
No reason to stick to u32 for platform mask if we can just use more bits
on 64 bit platforms.
$ size drivers/gpu/drm/i915/i915.ko*
textdata bss dec hex filename
1884779 413345408 1931521 1d7901 drivers/gpu/drm/i915/i915.ko
1886693 413585408 1933459 1d8093 drivers/g
== Series Details ==
Series: series starting with [1/2] drm/edid: Add a EDID edp panel quirk for
forcing max lane count
URL : https://patchwork.freedesktop.org/series/58893/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5857 -> Patchwork_12661
== Series Details ==
Series: drm/i915: use unsigned long for platform_mask
URL : https://patchwork.freedesktop.org/series/58895/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c2596d9afed6 drm/i915: use unsigned long for platform_mask
-:61: CHECK:OPEN_ENDED_LINE: Lines should no
== Series Details ==
Series: drm/i915: use unsigned long for platform_mask
URL : https://patchwork.freedesktop.org/series/58895/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: use unsigned long for platform_mask
+drivers/gpu/drm/i915/i915_drv
From: John Harrison
ATS has lots of extra media engines. This series adds support for them.
Note, a recent GuC FW is required - 32.0.3 is known to be good.
Version 31.0.1 causes a hang when i915 initialised the fifth VCS
engine.
v2: Clean up the I915_MAX_ENGINES define. Make assumptions about A
On Tue, Apr 02, 2019 at 11:16:23PM +, Patchwork wrote:
== Series Details ==
Series: drm/i915: use unsigned long for platform_mask
URL : https://patchwork.freedesktop.org/series/58895/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: use u
From: John Harrison
ATS has lots of extra media engines. This patch adds the interrupt
handler support for them.
v2: Changed debugfs to assume ATS always has VCSx8 + VECSx4
irrespective of fusings. [Tvrtko Ursulin]
v3: Changed interrupt masking to check for the presence of each pair
of engines
From: John Harrison
The current GuC FW release (31.0.1) dies when presented with too many
media engines. The issue was fixed by 32.0.3 (which is the next FW the
driver is intending to switch to). It is desirable to merge the the
patches which allow use of the new engines before the new GuC FW
pat
== Series Details ==
Series: drm/i915: use unsigned long for platform_mask
URL : https://patchwork.freedesktop.org/series/58895/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5858 -> Patchwork_12662
Summary
---
**FAI
On Thu, 31 Jan 2019 08:17:17 -0800, Chris Wilson wrote:
>
> How much energy does spinning on a semaphore consume relative to plain
> old spinning?
>
> Signed-off-by: Chris Wilson
> ---
> tests/i915/gem_exec_schedule.c | 72 +-
> 1 file changed, 71 insertions(+),
No reason to stick to u32 for platform mask if we can just use more bits
on 64 bit platforms.
$ size drivers/gpu/drm/i915/i915.ko*
textdata bss dec hex filename
1884779 413345408 1931521 1d7901 drivers/gpu/drm/i915/i915.ko
1886693 413585408 1933459 1d8093 drivers/g
== Series Details ==
Series: drm/i915: use unsigned long for platform_mask (rev2)
URL : https://patchwork.freedesktop.org/series/58895/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: use unsigned long for platform_mask
-drivers/gpu/drm/i915/s
== Series Details ==
Series: drm/i915: use unsigned long for platform_mask (rev2)
URL : https://patchwork.freedesktop.org/series/58895/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5858 -> Patchwork_12663
Summary
---
From: Kiran Kumar S
As per the display workaround #1200, FBC needs wait for vblank before
enabling and before disabling FBC.
In some cases, depending on whether FBC was compressing in that frame,
several control signals in the compression engine also will fail to properly
recognize the final seg
== Series Details ==
Series: drm/i915: FBC needs vblank before enable / disable. (rev2)
URL : https://patchwork.freedesktop.org/series/58843/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a7eb63398cfa drm/i915: FBC needs vblank before enable / disable.
-:10: WARNING:COMMIT_LOG_
From: Kiran Kumar S
As per the display workaround #1200, FBC needs wait for vblank before
enabling and before disabling FBC.
In some cases, depending on whether FBC was compressing in that frame,
several control signals in the compression engine also will fail to
properly recognize the final seg
1 - 100 of 116 matches
Mail list logo
