Define GuC firmware version for Icelake.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Rodrigo Vivi
Cc: Anusha Srivatsa
---
drivers/gpu/drm/i915/intel_guc_fw.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_guc
GuC firmware changed its release version numbering schema and now it
also includes patch version. Update our GuC firmware path definitions
to match new pattern:
_guc_...bin
While here, reorder platform checks and start from the latest.
Signed-off-by: Michal Wajdeczko
Cc: Joonas Lahtinen
Cc
This patch adds the support to load HuC on ICL.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: Anusha Srivatsa
Cc: Tony Ye
---
drivers/gpu/drm/i915/intel_huc_fw.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_
Gen11 defines new more flexible Host-to-GuC interrupt register.
Now the host can write any 32-bit payload to trigger an interrupt
and GuC can additionally read this payload from the register.
Current GuC firmware ignores the payload so we just write 0.
Bspec: 21043
Signed-off-by: Michal Wajdeczko
From: Oscar Mateo
Current GuC firmwares identify response message in a different way.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Kelvin Gardiner
Cc: John Spotswood
---
drivers/gpu/drm/i915/intel_guc_ct.c | 2 +-
drivers/gpu/drm/i915/intel_guc_fwif.h | 2 ++
2 files cha
Gen11 GuC firmware expects H2G command messages to be sent over CTB
(command transport buffers).
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
Cc: John Spotswood
---
drivers/gpu/drm/i915/i915_pci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gp
Gen11 adds new set of scratch registers that can be used for MMIO
based Host-to-Guc communication. Due to limited number of these
registers it is expected that host will use them only for command
transport buffers (CTB) communication setup if one is available.
Bspec: 21044
Signed-off-by: Michal W
GuC sends ENGINE_RESET_COMPLETE message as an follow-up answer
to earlier ENGINE_RESET request from the host. Once this message
is received, clear engine reset flag to unblock our reset process.
Credits-to: Michel Thierry
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Vinay Belg
From: Oscar Mateo
The new context descriptor format contains two assignable fields:
the SW Context ID (technically 11 bits, but practically limited to 2032
entries due to some being reserved for future use by the GuC) and the
SW Counter (6 bits).
We don't want to limit ourselves too much in the
From: Daniele Ceraolo Spurio
Starting from Gen11, the ID to be provided to GuC needs to contain
the engine class in bits [0..2] and the instance in bits [3..6].
NOTE: this patch breaks pointer dereferences in some existing GuC
functions that use the guc_id to dereference arrays but these functio
From: Oscar Mateo
The GuC interrupts now get their own interrupt vector (instead of
sharing a register with the PM interrupts) so handle appropriately.
Signed-off-by: Oscar Mateo
Signed-off-by: Michal Wajdeczko
Cc: Tvrtko Ursulin
Cc: Daniele Ceraolo Spurio
Cc: Joonas Lahtinen
---
drivers/g
Since fw version 25.161, GuC lets us know when an engine had to be reset
due to a hang in another dependent engine, by setting BIT(engine_class) in
the queue_engine_error field. GuC will ignore any other wq item until this
flag is cleared.
To restart the workqueue processing for that engine, we mu
From: Oscar Mateo
With the new interrupt re-partitioning in Gen11, GuC controls by itself
the interrupts it receives, so steering bits and registers have been
defeatured. Being this the case, when the GuC is in control of
submissions we won't know what to do with the ctx switch interrupt
in the d
From: Oscar Mateo
Controlling and handling of the GuC interrupts is Gen specific.
Create virtual functions to avoid redundant runtime Gen checks.
Gen-specific versions of these functions will follow.
Signed-off-by: Oscar Mateo
Signed-off-by: Michal Wajdeczko
Cc: Rodrigo Vivi
Cc: Tvrtko Ursuli
From: emersion
This adds basic immutable support for the zpos property. The zpos increases
from bottom to top: primary, sprites, cursor.
Signed-off-by: Simon Ser
---
This is based on a previous patch by Ville [1] that I wanted to review.
Unfortunately the patch no longer applies, so here is a
Quoting Michal Wajdeczko (2019-03-29 22:11:08)
> From: Oscar Mateo
>
> The new context descriptor format contains two assignable fields:
> the SW Context ID (technically 11 bits, but practically limited to 2032
> entries due to some being reserved for future use by the GuC) and the
> SW Counter (
Quoting Michal Wajdeczko (2019-03-29 22:11:16)
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 3dd971c09d52..c1b4fbd5f496 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -573,6 +573,44 @@ static void gen9_disable_g
On Fri, 2019-03-29 at 20:39 +0200, Ville Syrjälä wrote:
> On Thu, Mar 28, 2019 at 10:35:19AM -0700, Radhakrishna Sripada wrote:
> > Fixes the clock-gating issue when pipe scaling is enabled.
> > (Lineage #2006604312)
> >
> > V2: Fix typo in headline(Chris)
> > Handle the non double buffered na
Currently we only retry to load GuC firmware if the load fails due to
timeout. On Gen9 GuC loading may fail for different reasons, not just
hang/timeout. Direction from the GuC team is to retry for all cases of
GuC load failure on Gen9, not just for timeout.
Bugzilla: https://bugs.freedesktop.org/
== Series Details ==
Series: GuC 32.0.3
URL : https://patchwork.freedesktop.org/series/58760/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
07625b512895 drm/i915/guc: Don't allow GuC submission on pre-Gen11
a79bbfbbcaeb drm/i915/guc: Simplify preparation of GuC parameter block
== Series Details ==
Series: GuC 32.0.3
URL : https://patchwork.freedesktop.org/series/58760/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/guc: Don't allow GuC submission on pre-Gen11
Okay!
Commit: drm/i915/guc: Simplify preparation of GuC
From: John Harrison
With virtual engines, it is no longer possible to know which specific
physical engine a given request will be executed on at the time that
request is generated. This means that the request itself must be engine
agnostic - any direct register writes must be relative to the engi
== Series Details ==
Series: drm/i915: add immutable zpos plane properties
URL : https://patchwork.freedesktop.org/series/58761/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a8460dd85471 drm/i915: add immutable zpos plane properties
-:75: WARNING:NO_AUTHOR_SIGN_OFF: Missing Si
== Series Details ==
Series: GuC 32.0.3
URL : https://patchwork.freedesktop.org/series/58760/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5840 -> Patchwork_12637
Summary
---
**FAILURE**
Serious unknown changes c
== Series Details ==
Series: drm/i915: add immutable zpos plane properties
URL : https://patchwork.freedesktop.org/series/58761/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5840 -> Patchwork_12638
Summary
---
**FAI
Quoting Patchwork (2019-03-30 00:34:48)
> Suppressed
>
> The following results come from untrusted machines, tests, or statuses.
> They do not affect the overall result.
>
> * igt@gem_exec_gttfill@basic:
> - {fi-icl-guc}: NOTRUN -> SKIP
What CI doesn't say is that in th
== Series Details ==
Series: drm/i915/guc: Retry GuC load for all load failures (rev2)
URL : https://patchwork.freedesktop.org/series/58758/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5840 -> Patchwork_12639
Summary
== Series Details ==
Series: drm/i915: Engine relative MMIO (rev3)
URL : https://patchwork.freedesktop.org/series/57117/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
a3f3b4a23cc5 drm/i915: Engine relative MMIO
-:89: ERROR:SPACING: space prohibited after that open parenthesis '
Fixes the clock-gating issue when pipe scaling is enabled.
(Lineage #2006604312)
V2: Fix typo in headline(Chris)
Handle the non double buffered nature of the register(Ville)
V3: Fix checkpatch warning. BAT failure for V2 on gen3 looks unrelated.
V4: Split the icl and skl wa's(Ville)
V5: Split
RMW is used only in the disable path. Using it in enable path
for consistency.
Suggested-by: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/intel_display.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c
No functional change. Renaming the function to reflect the specific WA.
Suggested-by: Ville Syrjala
Cc: Anusha Srivatsa
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/intel_display.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/in
== Series Details ==
Series: drm/i915: Engine relative MMIO (rev3)
URL : https://patchwork.freedesktop.org/series/57117/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5840 -> Patchwork_12640
Summary
---
**SUCCESS**
== Series Details ==
Series: drm/i915/guc: Retry GuC load for all load failures
URL : https://patchwork.freedesktop.org/series/58758/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5839_full -> Patchwork_12636_full
Summary
-
== Series Details ==
Series: drm/i915/icl: Fix clockgating issue when using scalars (rev5)
URL : https://patchwork.freedesktop.org/series/58081/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5840 -> Patchwork_12641
Summary
== Series Details ==
Series: drm/i915/guc: Retry GuC load for all load failures (rev2)
URL : https://patchwork.freedesktop.org/series/58758/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5840_full -> Patchwork_12639_full
Su
== Series Details ==
Series: drm/i915: Engine relative MMIO (rev3)
URL : https://patchwork.freedesktop.org/series/57117/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5840_full -> Patchwork_12640_full
Summary
---
**S
== Series Details ==
Series: drm/i915/icl: Fix clockgating issue when using scalars (rev5)
URL : https://patchwork.freedesktop.org/series/58081/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5840_full -> Patchwork_12641_full
Quoting Xiaolin Zhang (2019-03-29 13:32:40)
> It is performance optimization to override the actual submisison backend
> in order to eliminate execlists csb process and reduce mmio trap numbers
> for workload submission without contextswith interrupt by talking with
> GVT via PV submisison notifica
== Series Details ==
Series: drm/i915: Finish the GAMMA_LUT stuff
URL : https://patchwork.freedesktop.org/series/58698/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5832_full -> Patchwork_12623_full
Summary
---
**FA
== Series Details ==
Series: drm/i915: Move intel_engine_mask_t around for use by
i915_request_types.h (rev5)
URL : https://patchwork.freedesktop.org/series/58052/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5832_full -> Patchwork_12624_full
On Thu, 28 Mar 2019, Matt Roper wrote:
> I agree with Jani's feedback and have a couple other comments inline below.
Thanks Matt, good stuff here. One naming note below.
> What does the "internal" in this name refer to? I think just something
> like i9xx_get_gamma_config() would be sufficient
>
On 28/03/2019 09:39, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-03-28 09:23:24)
On 26/03/2019 07:40, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Series removes device id checks from i915_drv.h macros and consolidates them to
i915_pciids.h as the main "database", while making intel_devi
Interpreting it as a 0.16 fixed point means we can't accurately
represent 1.0. Which is one of the values we really should be able to
represent.
Since most (all?) luts have lower precision this will only affect
rounding of 0x.
Cc: Uma Shankar
Cc: Ville Syrjälä
Cc: Shashank Sharma
Cc: "Kuma
On Wed, 27 Mar 2019, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin
>
> Concept of a sub-platform already exist in our code (like ULX and ULT
> platform variants and similar),implemented via the macros which check a
> list of device ids to determine a match.
>
> With this patch we consolidate devic
We may use HW semaphores to schedule nearly-ready work such that they
are already spinning on the GPU waiting for the completion on another
engine. However, we don't want for that spinning task to actually block
any real work should it be scheduled.
v2: No typeof autos
v3: Don't cheat, check gen8
Op 28-03-2019 om 22:05 schreef Ville Syrjala:
> From: Ville Syrjälä
>
> Plop in support for 10bit LUT on ilk/snb.
>
> There is no split gamma mode on these platforms, so we have
> to choose between degamma and gamma. That could be a runtime choice
> but for now let's just advertize the gamma as ha
== Series Details ==
Series: drm/gamma: Clarify gamma lut uapi
URL : https://patchwork.freedesktop.org/series/58718/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5835 -> Patchwork_12626
Summary
---
**SUCCESS**
No
On Thu, Mar 28, 2019 at 05:16:03PM -0700, Matt Roper wrote:
> On Thu, Mar 28, 2019 at 11:05:01PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Using the split gamma mode when we don't have to has the annoying
> > requirement of loading a linear LUT to the unused half. Instead
> > le
On Thu, 28 Mar 2019, Manasi Navare wrote:
> On Thu, Mar 28, 2019 at 11:18:56AM +0200, Jani Nikula wrote:
>> On Fri, 22 Mar 2019, Manasi Navare wrote:
>> > On Fri, Mar 22, 2019 at 09:28:01PM +0200, Jani Nikula wrote:
>> >> On Fri, 22 Mar 2019, Ville Syrjälä wrote:
>> >> > On Fri, Mar 22, 2019 at
On Fri, Mar 29, 2019 at 08:34:03AM -, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Finish the GAMMA_LUT stuff
> URL : https://patchwork.freedesktop.org/series/58698/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5832_full -> Patchwork_12623_full
On 3/20/2019 4:18 PM, Uma Shankar wrote:
HDR metadata block is introduced in CEA-861.3 spec.
Parsing the same to get the panel's HDR metadata.
v2: Rebase and added Ville's POC changes to the patch.
v3: No Change
v4: Addressed Shashank's review comments
Signed-off-by: Uma Shankar
---
drive
Currently, the Kbuild core manipulates header search paths in a crazy
way [1].
To fix this mess, I want all Makefiles to add explicit $(srctree)/ to
the search paths in the srctree. Some Makefiles are already written in
that way, but not all. The goal of this work is to make the notation
consisten
On 3/20/2019 4:18 PM, Uma Shankar wrote:
Enable writing of HDR metadata infoframe to panel.
The data will be provid by usersapace compositors, based
on blending policies and passsed to driver through a blob
property.
v2: Rebase
v3: Fixed a warning message
v4: Addressed Shashank's review comme
On Fri, Mar 29, 2019 at 08:32:41PM +0900, Masahiro Yamada wrote:
> Currently, the Kbuild core manipulates header search paths in a crazy
> way [1].
>
> To fix this mess, I want all Makefiles to add explicit $(srctree)/ to
> the search paths in the srctree. Some Makefiles are already written in
> t
On 29/03/2019 09:54, Jani Nikula wrote:
On Wed, 27 Mar 2019, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Concept of a sub-platform already exist in our code (like ULX and ULT
platform variants and similar),implemented via the macros which check a
list of device ids to determine a match.
With
On 3/20/2019 4:18 PM, Uma Shankar wrote:
HDR metadata requires a infoframe to be set. Due to fastset,
full modeset is not performed hence adding it to update_pipe
to handle that.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_ddi.c | 13 +
1 file changed, 13 insertions
== Series Details ==
Series: drm: prefix header search paths with $(srctree)/ (rev2)
URL : https://patchwork.freedesktop.org/series/56020/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm: prefix header search paths with $(srctree)/
-
+./arch/x86/inc
Quoting Patchwork (2019-03-29 05:40:25)
> == Series Details ==
>
> Series: drm/i915: move the edram detection out of uncore init
> URL : https://patchwork.freedesktop.org/series/58684/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5831_full -> Patchwork_12621_full
>
On 3/20/2019 4:18 PM, Uma Shankar wrote:
Added the const version of infoframe for DRM metadata
for HDR.
Signed-off-by: Uma Shankar
---
drivers/video/hdmi.c | 63 ++--
include/linux/hdmi.h | 5 +
2 files changed, 66 insertions(+), 2 delet
GC MAX register is used to program values from 1.0 to
less than 3.0. A different register was used instead of
the intended one. Fixed the same.
Currently limiting it to 1.0 due to ABI limitations.
Reported-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 22
Register offsets used to program GC max were not correct. This series
fixes the same, also limits the values to accurately clamp at 1.0.
Also added support to program EXT2 GC Max needed for values from 3.0
to 7.0. Limiting it again to 1.0 due to ABI limitations.
Uma Shankar (2):
drm/i915: Fix GC
EXT2 GC MAX registers are introduced from Gen10+ to
program values from 3.0 to 7.0. Enabled the same, but
currently limiting it to 1.0 as userspace ABI is limited
at that currently.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h| 1 +
drivers/gpu/drm/i915/intel_color.c | 28
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, March 29, 2019 4:17 PM
>To: Roper, Matthew D
>Cc: intel-gfx@lists.freedesktop.org; Shankar, Uma
>Subject: Re: [PATCH 2/6] drm/i915: Don't use split gamma when we don't have to
>
>On Thu, Mar 2
On 3/20/2019 4:18 PM, Uma Shankar wrote:
From: Ville Syrjälä
This patch enables infoframes on GLK+ to be
used to send HDR metadata to HDMI sink.
v2: Addressed Shashank's review comment.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 4 +++
== Series Details ==
Series: drm/gamma: Clarify gamma lut uapi
URL : https://patchwork.freedesktop.org/series/58718/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5835_full -> Patchwork_12626_full
Summary
---
**SUCCE
== Series Details ==
Series: Fixed GC MAX register programming for gamma luts
URL : https://patchwork.freedesktop.org/series/58734/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ecab4c425422 drm/i915: Fix GCMAX color register programming
ca881c02da68 drm/i915: Program EXT2 GC M
== Series Details ==
Series: drm: prefix header search paths with $(srctree)/ (rev2)
URL : https://patchwork.freedesktop.org/series/56020/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5837 -> Patchwork_12627
Summary
--
On 3/20/2019 4:18 PM, Uma Shankar wrote:
This patch enables modeset whenever HDR metadata
needs to be updated to sink.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_atomic.c | 15 ++-
drivers/gpu/drm/i915/intel_hdmi.c | 4
2 fil
== Series Details ==
Series: Fixed GC MAX register programming for gamma luts
URL : https://patchwork.freedesktop.org/series/58734/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5837 -> Patchwork_12628
Summary
---
**
On Fri, 29 Mar 2019, Tvrtko Ursulin wrote:
> On 29/03/2019 09:54, Jani Nikula wrote:
>> On Wed, 27 Mar 2019, Tvrtko Ursulin wrote:
>>> From: Tvrtko Ursulin
>>>
>>> Concept of a sub-platform already exist in our code (like ULX and ULT
>>> platform variants and similar),implemented via the macros
On Fri, Mar 29, 2019 at 06:19:18PM +0530, Uma Shankar wrote:
> GC MAX register is used to program values from 1.0 to
> less than 3.0. A different register was used instead of
> the intended one. Fixed the same.
>
> Currently limiting it to 1.0 due to ABI limitations.
>
> Reported-by: Ville Syrjäl
On Fri, Mar 29, 2019 at 06:19:19PM +0530, Uma Shankar wrote:
> EXT2 GC MAX registers are introduced from Gen10+ to
> program values from 3.0 to 7.0. Enabled the same, but
> currently limiting it to 1.0 as userspace ABI is limited
> at that currently.
>
> Signed-off-by: Uma Shankar
> ---
> driver
When we introduced preemption, we chose to keep it disabled for gen8 as
supporting preemption inside GPGPU user batches required various w/a in
userspace. Since then, the desire to preempt long queues of requests
between batches (e.g. within busywaiting semaphores) has grown. So allow
arbitration w
On Fri, Mar 29, 2019 at 12:47:02PM +0200, Ville Syrjälä wrote:
> On Thu, Mar 28, 2019 at 05:16:03PM -0700, Matt Roper wrote:
> > On Thu, Mar 28, 2019 at 11:05:01PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > Using the split gamma mode when we don't have to has the annoying
>
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, March 29, 2019 6:40 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville ;
>Lankhorst,
>Maarten
>Subject: Re: [Intel-gfx] [PATCH 1/2] drm/i915: Fix GCMAX color register
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Friday, March 29, 2019 6:41 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville ;
>Lankhorst,
>Maarten
>Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915: Program EXT2 GC MAX regist
== Series Details ==
Series: drm/i915/execlists: Enable coarse preemption boundaries for gen8
URL : https://patchwork.freedesktop.org/series/58738/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
678a3d72d2b3 drm/i915/execlists: Enable coarse preemption boundaries for gen8
-:21:
== Series Details ==
Series: drm/i915/execlists: Enable coarse preemption boundaries for gen8
URL : https://patchwork.freedesktop.org/series/58738/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/execlists: Enable coarse preemption boundaries f
GC MAX register is used to program values from 1.0 to
less than 3.0. A different register was used instead of
the intended one. Fixed the same.
Currently limiting it to 1.0 due to ABI limitations.
v2: Updated the 1.0 programming and aligned as per GLK, based
on Ville's feedback.
Reported-by: Vil
EXT2 GC MAX registers are introduced from Gen10+ to
program values from 3.0 to 7.0. Enabled the same, but
currently limiting it to 1.0 as userspace ABI is limited
at that currently.
v2: Updated the 1.0 programming and aligned as per GLK, also added
GLK along with GEN10+ check, as per Ville's feedb
Register offsets used to program GC max were not correct. This series
fixes the same, also limits the values to accurately clamp at 1.0.
Also added support to program EXT2 GC Max needed for values from 3.0
to 7.0. Limiting it again to 1.0 due to ABI limitations.
v2: Addressed Ville's review commen
On Wed, Mar 20, 2019 at 04:18:25PM +0530, Uma Shankar wrote:
> HDR metadata requires a infoframe to be set. Due to fastset,
> full modeset is not performed hence adding it to update_pipe
> to handle that.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 13 +
From: Ville Syrjälä
Using the split gamma mode when we don't have to has the annoying
requirement of loading a linear LUT to the unused half. Instead
let's make life simpler by switching to the 10bit gamma mode
and duplicating each entry.
This also allows us to load the software gamma LUT into t
== Series Details ==
Series: drm/i915/execlists: Enable coarse preemption boundaries for gen8
URL : https://patchwork.freedesktop.org/series/58738/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5837 -> Patchwork_12629
Summa
Quoting Patchwork (2019-03-29 14:16:21)
> == Series Details ==
>
> Series: drm/i915/execlists: Enable coarse preemption boundaries for gen8
> URL : https://patchwork.freedesktop.org/series/58738/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5837 -> Patchwork_12629
>
On Fri, Mar 29, 2019 at 08:32:41PM +0900, Masahiro Yamada wrote:
> Currently, the Kbuild core manipulates header search paths in a crazy
> way [1].
>
> To fix this mess, I want all Makefiles to add explicit $(srctree)/ to
> the search paths in the srctree. Some Makefiles are already written in
> t
On Fri, Mar 29, 2019 at 10:20:27AM +0100, Daniel Vetter wrote:
> Interpreting it as a 0.16 fixed point means we can't accurately
> represent 1.0. Which is one of the values we really should be able to
> represent.
>
> Since most (all?) luts have lower precision this will only affect
> rounding of
On 29/03/2019 09:20, Daniel Vetter wrote:
Interpreting it as a 0.16 fixed point means we can't accurately
represent 1.0. Which is one of the values we really should be able to
represent.
Since most (all?) luts have lower precision this will only affect
rounding of 0x.
Cc: Uma Shankar
Cc: V
On 29/03/2019 14:29, Uma Shankar wrote:
Register offsets used to program GC max were not correct. This series
fixes the same, also limits the values to accurately clamp at 1.0.
Also added support to program EXT2 GC Max needed for values from 3.0
to 7.0. Limiting it again to 1.0 due to ABI limitat
On Fri, Mar 29, 2019 at 10:20:27AM +0100, Daniel Vetter wrote:
> Interpreting it as a 0.16 fixed point means we can't accurately
> represent 1.0. Which is one of the values we really should be able to
> represent.
>
> Since most (all?) luts have lower precision this will only affect
> rounding of
== Series Details ==
Series: Fixed GC MAX register programming for gamma luts (rev2)
URL : https://patchwork.freedesktop.org/series/58734/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
88164253880f drm/i915: Fix GCMAX color register programming
cad25ef86aee drm/i915: Program EX
>-Original Message-
>From: Landwerlin, Lionel G
>Sent: Friday, March 29, 2019 8:00 PM
>To: Shankar, Uma ; intel-gfx@lists.freedesktop.org
>Cc: Syrjala, Ville ; Lankhorst, Maarten
>
>Subject: Re: [Intel-gfx] [v2 0/2] Fixed GC MAX register programming for gamma
>luts
>
>On 29/03/2019 14:29
== Series Details ==
Series: Fixed GC MAX register programming for gamma luts (rev2)
URL : https://patchwork.freedesktop.org/series/58734/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5837 -> Patchwork_12630
Summary
--
On 3/28/19 8:18 PM, Stephen Rothwell wrote:
> Hi all,
>
> Changes since 20190328:
>
> The pidfd tree lost its build failures.
>
on x86_64, when # CONFIG_ACPI is not set/enabled:
ld: drivers/gpu/drm/i915/intel_panel.o: in function
`intel_backlight_device_register':
intel_panel.c:(.text+0x2c49)
On Fri, Mar 29, 2019 at 10:20:27AM +0100, Daniel Vetter wrote:
> Interpreting it as a 0.16 fixed point means we can't accurately
> represent 1.0. Which is one of the values we really should be able to
> represent.
>
> Since most (all?) luts have lower precision this will only affect
> rounding of
== Series Details ==
Series: drm/i915: Finish the GAMMA_LUT stuff (rev2)
URL : https://patchwork.freedesktop.org/series/58698/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5837 -> Patchwork_12631
Summary
---
**SUCCE
Quoting Xiaolin Zhang (2019-03-29 13:32:40)
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 2f78829..28e8ee0 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -37,6 +37,7 @@
> #include "i915_drv.h"
> #include "i915
Use the engine->flags to store whether we want to kick the submission
tasklet on receipt of a breadcrumb interrupt, so that this decision can
be made by the submission backend and not dependent on a limited feature
test within the interrupt handler. This should make it easier to adapt
different sub
On 3/29/19 10:20 AM, Daniel Vetter wrote:
> Interpreting it as a 0.16 fixed point means we can't accurately
> represent 1.0. Which is one of the values we really should be able to
> represent.
>
> Since most (all?) luts have lower precision this will only affect
> rounding of 0x.
>
> Cc: Um
Quoting Xiaolin Zhang (2019-03-29 13:32:36)
> To improve vgpu performance, it could implement some PV optimization
> such as to reduce the mmio access trap numbers or eliminate certain piece
> of HW emulation within guest driver to reduce vm exit/vm enter cost.
Where's the CI for this patchset? Th
1 - 100 of 147 matches
Mail list logo
