>-Original Message-
>From: Sharma, Shashank
>Sent: Friday, March 15, 2019 1:01 PM
>To: Shankar, Uma ; intel-gfx@lists.freedesktop.org; dri-
>de...@lists.freedesktop.org
>Cc: Lankhorst, Maarten ; Syrjala, Ville
>; emil.l.veli...@gmail.com; brian.star...@arm.com;
>liviu.du...@arm.com
>Subje
On 19/03/2019 14:23, Ville Syrjala wrote:
From: Ville Syrjälä
Make the code self-documenting by introducing i9xx_has_pfit().
Also make PNV an exceptional case so that we can unset
.is_mobile for the desktop variant.
v2: s/gen4/gen>=4/ (Tvrtko)
Cc: Tvrtko Ursulin
Signed-off-by: Ville Syrjälä
>-Original Message-
>From: Sharma, Shashank
>Sent: Friday, March 15, 2019 1:06 PM
>To: Shankar, Uma ; intel-gfx@lists.freedesktop.org; dri-
>de...@lists.freedesktop.org
>Cc: Lankhorst, Maarten ; Syrjala, Ville
>; emil.l.veli...@gmail.com; brian.star...@arm.com;
>liviu.du...@arm.com
>Subje
From: Daniele Ceraolo Spurio
Exercise acquiring and releasing forcewake around register reads. In
order to read a register behind a GT powerwell, we need to instruct that
powerwell to wake up using a forcewake. When we no longer require the GT
powerwell, we tell the GT to release our forcewake. I
On 3/20/2019 12:47 PM, Shankar, Uma wrote:
-Original Message-
From: Sharma, Shashank
Sent: Friday, March 15, 2019 1:01 PM
To: Shankar, Uma ; intel-gfx@lists.freedesktop.org; dri-
de...@lists.freedesktop.org
Cc: Lankhorst, Maarten ; Syrjala, Ville
; emil.l.veli...@gmail.com; brian.star.
Chris Wilson writes:
> If a test fails, we quite often mark the device as wedged. Provide the
> stub functions so that we can wedge the mock device, and avoid exploding
> on test failures.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109981
> Signed-off-by: Chris Wilson
> Cc: Mika
>On 3/20/2019 12:47 PM, Shankar, Uma wrote:
>>
>>> -Original Message-
>>> From: Sharma, Shashank
>>> Sent: Friday, March 15, 2019 1:01 PM
>>> To: Shankar, Uma ;
>>> intel-gfx@lists.freedesktop.org; dri- de...@lists.freedesktop.org
>>> Cc: Lankhorst, Maarten ; Syrjala, Ville
>>> ; emil.l.vel
On Tue, 19 Mar 2019, Manasi Navare wrote:
> This patch fixes the PORT_SYNC_MODE_MASTER_SELECT macro
> to correctly do the left shifting to set the port sync
> master select correctly.
> I have tested this fix on ICL.
>
> Fixes: 49edbd49786e ("drm/i915/icl: Define TRANS_DDI_FUNC_CTL DSI registers")
== Series Details ==
Series: drm/i915/icl: Fix the TRANS_DDI_FUNC_CTL2 bitfield macro
URL : https://patchwork.freedesktop.org/series/58204/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5775_full -> Patchwork_12520_full
Sum
From: Ville Syrjälä
If we have only a single active pipe and the cdclk change only requires
the cd2x divider to be updated bxt+ can do the update with forcing a full
modeset on the pipe. Try to hook that up.
v2:
- Wait for vblank after an optimized CDCLK change.
- Avoid optimization if the pipe
The old state will be needed by an upcoming patch to determine if the
commit increases or decreases CDCLK, so move the old state to the atomic
state (while keeping the new one in dev_priv). cdclk.logical and
cdclk.actual in the atomic state isn't used atm anywhere after the
atomic check phase, so t
>-Original Message-
>From: Sharma, Shashank
>Sent: Friday, March 15, 2019 1:54 PM
>To: Shankar, Uma ; intel-gfx@lists.freedesktop.org; dri-
>de...@lists.freedesktop.org
>Cc: Lankhorst, Maarten ; Syrjala, Ville
>; emil.l.veli...@gmail.com; brian.star...@arm.com;
>liviu.du...@arm.com; Ville
Use the igt_live_test framework for detecting whether an unwanted hang
occurred during test execution, and report failure if it does.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/intel_lrc.c | 38 --
1 file changed, 35 insertions(+), 3 deletions(-)
diff --g
>-Original Message-
>From: Sharma, Shashank
>Sent: Friday, March 15, 2019 4:38 PM
>To: Shankar, Uma ; intel-gfx@lists.freedesktop.org; dri-
>de...@lists.freedesktop.org
>Cc: Lankhorst, Maarten ; Syrjala, Ville
>; emil.l.veli...@gmail.com; brian.star...@arm.com;
>liviu.du...@arm.com
>Subje
Hi Imre,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on next-20190320]
[cannot apply to v5.1-rc1]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url
HDR metadata block is introduced in CEA-861.3 spec.
Parsing the same to get the panel's HDR metadata.
v2: Rebase and added Ville's POC changes to the patch.
v3: No Change
v4: Addressed Shashank's review comments
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 49 ++
This patch series enables HDR support in drm. It basically defines
HDR metadata structures, property to pass content (after blending)
metadata from user space compositors to driver.
Dynamic Range and Mastering infoframe creation and sending.
ToDo:
1. We need to get the color framework in place fo
CEA 861.3 spec adds colorimetry data block for HDMI.
Parsing the block to get the colorimetry data from
panel.
v2: Rebase
v3: No Change
v4: Addressed Shashank's review comments. Updated
colorimetry field to 16 bit as DCI-P3 got added
in CEA 861-G spec, as pointed out by Shashank.
v5: Fixed chec
This patch adds a blob property to get HDR metadata
information from userspace. This will be send as part
of AVI Infoframe to panel.
v2: Rebase and modified the metadata structure elements
as per Ville's POC changes.
v3: No Change
v4: Addressed Shashank's review comments
v5: Rebase.
Signed-off
Attach HDR metadata property to connector object.
v2: Rebase
v3: Updated the property name as per updated name
while creating hdr metadata property
Signed-off-by: Uma Shankar
Reviewed-by: Shashank Sharma
---
drivers/gpu/drm/i915/intel_hdmi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
HDR metadata requires a infoframe to be set. Due to fastset,
full modeset is not performed hence adding it to update_pipe
to handle that.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_ddi.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_
This patch implements get() and set() functions for HDR output
metadata property.The blob data is received from userspace and
saved in connector state, the same is returned as blob in get
property call to userspace.
v2: Rebase and added Ville's POC changes
v3: No Change
v4: Addressed Shashank's
Enable writing of HDR metadata infoframe to panel.
The data will be provid by usersapace compositors, based
on blending policies and passsed to driver through a blob
property.
v2: Rebase
v3: Fixed a warning message
v4: Addressed Shashank's review comments
v5: Rebase. Added infoframe calculation
From: Ville Syrjälä
ADD HLG EOTF to the list of EOTF transfer functions supported.
Hybrid Log-Gamma (HLG) is a high dynamic range (HDR) standard.
HLG defines a nonlinear transfer function in which the lower
half of the signal values use a gamma curve and the upper half
of the signal values use a
From: Ville Syrjälä
This is to limit PORT C on GLK to drive only
HDMI. Not sure if this is mandatory, this is just
to test HDR on GLK HDMI.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_bios.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/
Added the const version of infoframe for DRM metadata
for HDR.
Signed-off-by: Uma Shankar
---
drivers/video/hdmi.c | 63 ++--
include/linux/hdmi.h | 5 +
2 files changed, 66 insertions(+), 2 deletions(-)
diff --git a/drivers/video/hdmi.c b/dr
Enable Dynamic Range and Mastering Infoframe for HDR
content, which is defined in CEA 861.3 spec.
The metadata will be computed based on blending
policy in userspace compositors and passed as a connector
property blob to driver. The same will be sent as infoframe
to panel which support HDR.
v2: R
From: Ville Syrjälä
This patch enables infoframes on GLK+ to be
used to send HDR metadata to HDMI sink.
v2: Addressed Shashank's review comment.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 4
drivers/gpu/drm/i915/intel_hdmi.c | 18 +++
This patch enables modeset whenever HDR metadata
needs to be updated to sink.
Signed-off-by: Ville Syrjälä
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_atomic.c | 15 ++-
drivers/gpu/drm/i915/intel_hdmi.c | 4
2 files changed, 18 insertions(+), 1 deletion(-)
di
Op 19-03-2019 om 17:18 schreef Ville Syrjälä:
> On Tue, Mar 19, 2019 at 05:06:36PM +0100, Maarten Lankhorst wrote:
>> Op 19-03-2019 om 14:02 schreef Ville Syrjälä:
>>> On Tue, Mar 19, 2019 at 01:17:02PM +0100, Maarten Lankhorst wrote:
There has unfortunately been a conflict with the following
Re-enable clock gating of DDI clocks.
Fixes: 1026bea00381 (drm/i915/icl: Ungate DSI clocks)
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/icl_dsi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i915/icl_dsi.c
index
IO enable sequencing needs ddi clocks enabled.
These clocks will be gated at the later point in
the enable sequence.
Signed-off-by: Vandita Kulkarni
---
drivers/gpu/drm/i915/icl_dsi.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl_dsi.c b/drivers/gpu/drm/i91
On 19/03/2019 11:57, Chris Wilson wrote:
Define a mutex for the exclusive use of interacting with the per-file
context-idr, that was previously guarded by struct_mutex. This allows us
to reduce the coverage of struct_mutex, with a view to removing the last
bits coordinating GEM context later. (I
On 19/03/2019 12:58, Chris Wilson wrote:
The user_handle need only be known by userspace for it to lookup the
context via the idr; internally we have no use for it.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 ++--
drivers/gpu/drm/i915/i915_gem_context
== Series Details ==
Series: series starting with [v2] drm/i915/selftests: add test to verify
get/put fw domains (rev5)
URL : https://patchwork.freedesktop.org/series/58202/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7b3b753c99d3 drm/i915/selftests: add test to verify get/p
On Wed, Mar 20, 2019 at 03:38:59PM +0530, Vandita Kulkarni wrote:
> Re-enable clock gating of DDI clocks.
>
> Fixes: 1026bea00381 (drm/i915/icl: Ungate DSI clocks)
> Signed-off-by: Vandita Kulkarni
> ---
> drivers/gpu/drm/i915/icl_dsi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
== Series Details ==
Series: series starting with [v2] drm/i915/selftests: add test to verify
get/put fw domains (rev5)
URL : https://patchwork.freedesktop.org/series/58202/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5778 -> Patchwork_12525
Quoting Chris Wilson (2019-03-19 18:59:04)
> Quoting Daniele Ceraolo Spurio (2019-03-19 18:35:33)
> > Compared to v1 [1], there is a new patch for further simplification of
> > low-level fw get/put by always using the bitmasks since the upper bits
> > of the fw reg are reserved on gen6 and I couldn
Hi,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20190320]
[cannot apply to v5.1-rc1]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https
On Tue, 19 Mar 2019 at 11:58, Chris Wilson wrote:
>
> When we return pages to the system, we ensure that they are marked as
> being in the CPU domain since any external access is uncontrolled and we
> must assume the worst. This means that we need to always flush the pages
> on acquisition if we n
Quoting Matthew Auld (2019-03-20 11:41:52)
> On Tue, 19 Mar 2019 at 11:58, Chris Wilson wrote:
> > @@ -2534,6 +2522,14 @@ void __i915_gem_object_set_pages(struct
> > drm_i915_gem_object *obj,
> >
> > lockdep_assert_held(&obj->mm.lock);
> >
> > + /* Make the pages coherent with the G
>-Original Message-
>From: Kulkarni, Vandita
>Sent: Wednesday, March 20, 2019 3:39 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Nikula, Jani ; Shankar, Uma ;
>Chauhan, Madhav ; Kulkarni, Vandita
>
>Subject: [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated
You can drop dsi from commit
>-Original Message-
>From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
>Imre
>Deak
>Sent: Wednesday, March 20, 2019 4:38 PM
>To: Kulkarni, Vandita
>Cc: Nikula, Jani ; intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH 2/2] drm/i915/icl/dsi: Fix
On Wed, 20 Mar 2019 at 11:48, Chris Wilson wrote:
>
> Quoting Matthew Auld (2019-03-20 11:41:52)
> > On Tue, 19 Mar 2019 at 11:58, Chris Wilson wrote:
> > > @@ -2534,6 +2522,14 @@ void __i915_gem_object_set_pages(struct
> > > drm_i915_gem_object *obj,
> > >
> > > lockdep_assert_held(&obj
From: Daniele Ceraolo Spurio
Upper bits are reserved on gen6, so no issue if we write them. Note that
we're already doing this in the non-MT case of IVB, which uses the same
register.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Cc: Chris Wilson
Reviewed-by: Paulo Zanoni
Reviewed-b
Quoting Matthew Auld (2019-03-20 12:26:00)
> On Wed, 20 Mar 2019 at 11:48, Chris Wilson wrote:
> >
> > Quoting Matthew Auld (2019-03-20 11:41:52)
> > > On Tue, 19 Mar 2019 at 11:58, Chris Wilson
> > > wrote:
> > > > @@ -2534,6 +2522,14 @@ void __i915_gem_object_set_pages(struct
> > > > drm_i915
On 19/03/2019 11:57, Chris Wilson wrote:
The timeline->name is only used for convenience in pretty printing the
i915_request.fence->ops->get_timeline_name() and it is just as
convenient to pull it from the gem_context directly. The few instances
of its use inside GEM_TRACE() has proven more of a
On 19/03/2019 11:57, Chris Wilson wrote:
In preparation to making the ppGTT binding for a context explicit (to
facilitate reusing the same ppGTT between different contexts), allow the
user to create and destroy named ppGTT.
v2: Replace global barrier for swapping over the ppgtt and tlbs with a
On 19/03/2019 11:57, Chris Wilson wrote:
A usecase arose out of handling context recovery in mesa, whereby they
wish to recreate a context with fresh logical state but preserving all
other details of the original. Currently, they create a new context and
iterate over which bits they want to copy
On 19/03/2019 11:57, Chris Wilson wrote:
Over the last few years, we have debated how to extend the user API to
support an increase in the number of engines, that may be sparse and
even be heterogeneous within a class (not all video decoders created
equal). We settled on using (class, instance)
On 19/03/2019 11:57, Chris Wilson wrote:
Allow the user to specify a local engine index (as opposed to
class:index) that they can use to refer to a preset engine inside the
ctx->engine[] array defined by an earlier I915_CONTEXT_PARAM_ENGINES.
This will be useful for setting SSEU parameters on vi
== Series Details ==
Series: drm/i915: Ensure minimum CDCLK requirement for audio (rev4)
URL : https://patchwork.freedesktop.org/series/58132/
State : failure
== Summary ==
Applying: drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabled
Applying: drm/i915: Skip modeset for cdcl
== Series Details ==
Series: drm/i915/selftests: Mark up preemption tests for hang detection
URL : https://patchwork.freedesktop.org/series/58236/
State : failure
== Summary ==
Applying: drm/i915/selftests: Mark up preemption tests for hang detection
Using index info to reconstruct a base tree
== Series Details ==
Series: Add HDR Metadata Parsing and handling in DRM layer (rev6)
URL : https://patchwork.freedesktop.org/series/25091/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3ffebb6ddcbf drm: Add HDR source metadata property
6d0a7b41e79c drm: Parse HDR metadata inf
From: Ville Syrjälä
CDCLK has to be at least twice the BLCK regardless of audio. Audio
driver has to probe using this hook and increase the clock even in
absence of any display.
v2: Use atomic refcount for get_power, put_power so that we can
call each once(Abhay).
v3: Reset power well 2 to a
The old state will be needed by an upcoming patch to determine if the
commit increases or decreases CDCLK, so move the old state to the atomic
state (while keeping the new one in dev_priv). cdclk.logical and
cdclk.actual in the atomic state isn't used atm anywhere after the
atomic check phase, so t
From: Ville Syrjälä
If we have only a single active pipe and the cdclk change only requires
the cd2x divider to be updated bxt+ can do the update with forcing a full
modeset on the pipe. Try to hook that up.
v2:
- Wait for vblank after an optimized CDCLK change.
- Avoid optimization if the pipe
We copied the original state into the atomic state already earlier in
the function, so no need to do it a second time.
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu
== Series Details ==
Series: Add HDR Metadata Parsing and handling in DRM layer (rev6)
URL : https://patchwork.freedesktop.org/series/25091/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5780 -> Patchwork_12528
Summary
On Wed, 20 Mar 2019 at 12:36, Chris Wilson wrote:
>
> Quoting Matthew Auld (2019-03-20 12:26:00)
> > On Wed, 20 Mar 2019 at 11:48, Chris Wilson wrote:
> > >
> > > Quoting Matthew Auld (2019-03-20 11:41:52)
> > > > On Tue, 19 Mar 2019 at 11:58, Chris Wilson
> > > > wrote:
> > > > > @@ -2534,6 +2
== Series Details ==
Series: series starting with [1/2] drm/i915/icl/dsi: Ungate clocks if gated
URL : https://patchwork.freedesktop.org/series/58241/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5780 -> Patchwork_12529
Su
On Tue, Mar 19, 2019 at 02:59:38PM -0700, Matt Roper wrote:
> On Mon, Mar 18, 2019 at 06:13:08PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > In prepartion for per-platform color_check() functions extract the
> > common code into a separate function.
> >
> > Signed-off-by: Ville S
On Tue, Mar 19, 2019 at 03:00:26PM -0700, Matt Roper wrote:
> On Mon, Mar 18, 2019 at 06:13:11PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Since CHV has the CGM unit we require a custom implementation
> > of .color_check().
> >
> > This fixes the computation of gamma_enable as
On Tue, Mar 19, 2019 at 06:24:47PM +0200, Jani Nikula wrote:
> On Mon, 18 Mar 2019, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > In prepartion for per-platform color_check() functions extract the
> > common code into a separate function.
> >
> > Signed-off-by: Ville Syrjälä
> > ---
> >
On Mon, Mar 18, 2019 at 07:05:29PM -0300, Rodrigo Siqueira wrote:
> On 03/18, Liviu Dudau wrote:
> > On Wed, Mar 06, 2019 at 06:30:05PM -0300, Rodrigo Siqueira wrote:
> > > Hi Liviu,
> > >
> > > I’m using your patchset to guide my implementation of writeback in the
> > > VKMS, so, first of all, th
Chris Wilson writes:
> Don't try to evaluate whether reads executed on an absent ring do
> anything.
>
> Signed-off-by: Chris Wilson
Reviewed-by: Mika Kuoppala
> ---
> tests/i915/gem_mocs_settings.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/tests/i915/gem_m
== Series Details ==
Series: drm/i915: always use masks on FW regs
URL : https://patchwork.freedesktop.org/series/58246/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5780 -> Patchwork_12530
Summary
---
**SUCCESS**
On Mon, 18 Mar 2019 at 08:58, Chris Wilson wrote:
>
> Signed-off-by: Chris Wilson
Should do the trick,
Reviewed-by: Matthew Auld
___
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
On Wed, Mar 20, 2019 at 04:41:31PM +0200, Ville Syrjälä wrote:
> On Tue, Mar 19, 2019 at 02:59:38PM -0700, Matt Roper wrote:
> > On Mon, Mar 18, 2019 at 06:13:08PM +0200, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > In prepartion for per-platform color_check() functions extract the
On Mon, Mar 18, 2019 at 05:10:49PM -0700, Matt Roper wrote:
> On Tue, Mar 12, 2019 at 10:58:42PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Clean up skl_allocate_pipe_ddb() a bit by moving the 'wm' variable
> > to tighter scope. We'll also consitify it where appropriate.
> >
> >
On Tue, Mar 19, 2019 at 01:29:58PM +, Tvrtko Ursulin wrote:
>
> On 18/03/2019 16:56, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > To allow unsetting .is_mobile for the desktop variant
> > of PNV fix up the cdclk code to select the mobile HPLLVCO register
> > for both PNV variants.
>
On Wed, Mar 20, 2019 at 08:14:56AM -0700, Matt Roper wrote:
> On Wed, Mar 20, 2019 at 04:41:31PM +0200, Ville Syrjälä wrote:
> > On Tue, Mar 19, 2019 at 02:59:38PM -0700, Matt Roper wrote:
> > > On Mon, Mar 18, 2019 at 06:13:08PM +0200, Ville Syrjala wrote:
> > > > From: Ville Syrjälä
> > > >
> >
gcc-4.8 and older dislike the use of __builtin_constant_p() within a
constant expression context, and so we must use the magical
__is_constexpr() instead.
For example, with gcc-4.8.5:
../drivers/gpu/drm/i915/i915_reg.h:167:27: error: first argument to
‘__builtin_choose_expr’ not a constant
../inc
On Tue, 2019-03-19 at 13:17 +0100, Maarten Lankhorst wrote:
> There has unfortunately been a conflict with the following 3 commits:
>
> commit e9961ab95af81b8d29054361cd5f0c575102cf87
> Author: Ayan Kumar Halder
> Date: Fri Nov 9 17:21:12 2018 +
> drm: Added a new format DRM_FORMAT_XVYU
From: Ville Syrjälä
The hardware never sees the uv_wm values (apart from
uv_wm.min_ddb_alloc affecting the ddb allocation). Thus there
is no point in comparing uv_wm to determine if we need to
reprogram the watermark registers. So let's check only the
rgb/y watermark in skl_plane_wm_equals(). But
On 19/03/2019 11:57, Chris Wilson wrote:
Having allowed the user to define a set of engines that they will want
to only use, we go one step further and allow them to bind those engines
into a single virtual instance. Submitting a batch to the virtual engine
will then forward it to any one of the
Op 20-03-2019 om 16:48 schreef Adam Jackson:
> On Tue, 2019-03-19 at 13:17 +0100, Maarten Lankhorst wrote:
>> There has unfortunately been a conflict with the following 3 commits:
>>
>> commit e9961ab95af81b8d29054361cd5f0c575102cf87
>> Author: Ayan Kumar Halder
>> Date: Fri Nov 9 17:21:12 2018
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110212
Fixes: 8ae86621d6ff ("lib/igt_device: Move intel_get_pci_device under
igt_device")
Signed-off-by: Chris Wilson
Cc: Michał Winiarski
---
tests/i915/gem_shrink.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --
On 3/20/19 8:40 AM, Chris Wilson wrote:
> gcc-4.8 and older dislike the use of __builtin_constant_p() within a
> constant expression context, and so we must use the magical
> __is_constexpr() instead.
>
> For example, with gcc-4.8.5:
> ../drivers/gpu/drm/i915/i915_reg.h:167:27: error: first argume
Thank you very much for your reply. Do you mean if I track the argument to the
callers, I should be able to figure out that the pin is always valid? I think I
have two questions for this approach. First, does it mean that the branch
returning NULL is practically dead code? Second, the driver cod
== Series Details ==
Series: series starting with [CI,1/4] drm/i915: Force 2*96 MHz cdclk on glk/cnl
when audio power is enabled
URL : https://patchwork.freedesktop.org/series/58273/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Force 2*96
>-Original Message-
>From: Syrjala, Ville
>Sent: Tuesday, March 19, 2019 10:29 PM
>To: Lankhorst, Maarten
>Cc: Shankar, Uma ; intel-gfx@lists.freedesktop.org;
>Sharma, Shashank ; Roper, Matthew D
>
>Subject: Re: [RFC v1 3/7] drm/i915: Add Support for Multi Segment Gamma Mode
>
>On Tue, M
== Series Details ==
Series: drm/i915: Use __is_constexpr()
URL : https://patchwork.freedesktop.org/series/58278/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
3ae1e5b1f498 drm/i915: Use __is_constexpr()
-:38: WARNING:LONG_LINE: line over 100 characters
#38: FILE: drivers/gpu/d
== Series Details ==
Series: series starting with [CI,1/4] drm/i915: Force 2*96 MHz cdclk on glk/cnl
when audio power is enabled
URL : https://patchwork.freedesktop.org/series/58273/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5781 -> Patchwork_12531
===
Quoting Chris Wilson (2019-03-04 09:43:43)
> Quoting Andy Shevchenko (2019-03-04 09:29:07)
> > Switch to bitmap_zalloc() to show clearly what we are allocating.
> > Besides that it returns pointer of bitmap type instead of opaque void *.
> >
> > Signed-off-by: Andy Shevchenko
> Reviewed-by: Chris
PSR2 logic is incorrectly looking at this register bit during DC5 exit.
Not a DMC problem, but DMC enables DC5.
I'll update Bspec to require the bit to be not set when PSR2 is used.
> -Original Message-
> From: Runyan, Arthur J
> Sent: Tuesday, 12 March, 2019 4:42 PM
> To: Souza, Jose ; V
== Series Details ==
Series: series starting with [1/2] drm/i915/icl/dsi: Ungate clocks if gated
URL : https://patchwork.freedesktop.org/series/58241/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5780_full -> Patchwork_12529_full
==
Thanks for checking, appreciate it.
-DK
> -Original Message-
> From: Runyan, Arthur J
> Sent: Wednesday, March 20, 2019 11:58 AM
> To: Souza, Jose ; Vivi, Rodrigo
> ; Pandiyan, Dhinakaran
>
> Cc: Aigal, Pavana A ; 'intel-
> g...@lists.freedesktop.org'
> Subject: RE: [PATCH] drm/i915: Fi
Pushed to dinq, thanks for the review!
Regards
Manasi
On Wed, Mar 20, 2019 at 11:17:49AM +0200, Jani Nikula wrote:
> On Tue, 19 Mar 2019, Manasi Navare wrote:
> > This patch fixes the PORT_SYNC_MODE_MASTER_SELECT macro
> > to correctly do the left shifting to set the port sync
> > master select
On Wed, Mar 20, 2019 at 04:01:51PM +, Chris Wilson wrote:
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110212
> Fixes: 8ae86621d6ff ("lib/igt_device: Move intel_get_pci_device under
> igt_device")
> Signed-off-by: Chris Wilson
> Cc: Michał Winiarski
> ---
> tests/i915/gem_shrink
== Series Details ==
Series: drm/i915: always use masks on FW regs
URL : https://patchwork.freedesktop.org/series/58246/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5780_full -> Patchwork_12530_full
Summary
---
**S
Hi Dave and Daniel,
Here goes the first round of fixes for 5.1-rc cycle.
I will be out on vacation next week, so next week's pull request
might come from Jani. Although things looks calm right now.
only 3 patches on top of -rc1:
drm-intel-fixes-2019-03-20:
A protection on our mmap against atte
Quoting Ville Syrjälä (2019-03-20 19:26:29)
> On Wed, Mar 20, 2019 at 04:01:51PM +, Chris Wilson wrote:
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110212
> > Fixes: 8ae86621d6ff ("lib/igt_device: Move intel_get_pci_device under
> > igt_device")
> > Signed-off-by: Chris Wilson
From: Daniele Ceraolo Spurio
Move the init, fini, prune, suspend, resume function to work on
intel_uncore instead of dev_priv.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Reviewed-by: Paulo Zanoni
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/201
From: Daniele Ceraolo Spurio
This will allow futher simplifications in the uncore handling.
v2: move register access setup under uncore (Chris)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Cc: Chris Wilson
Reviewed-by: Paulo Zanoni
Signed-off-by: Chris Wilson
Link:
https://patch
From: Daniele Ceraolo Spurio
Get/put functions used outside of uncore.c are updated in the next
patch for a nicer split.
v2: use dev_priv where we still have it (Paulo)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Reviewed-by: Paulo Zanoni
Signed-off-by: Chris Wilson
Link:
https:
From: Daniele Ceraolo Spurio
Use a local variable where it makes sense.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Reviewed-by: Paulo Zanoni
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20190319183543.13679-7-daniele.ceraolospu...@intel.com
---
From: Daniele Ceraolo Spurio
Now that the internal code all works on intel_uncore, flip the
external-facing interface.
v2: fix GVT.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Reviewed-by: Paulo Zanoni
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msg
From: Daniele Ceraolo Spurio
This allows us to ditch i915 in some more places.
v2: use local var in check_vgpu (Paulo)
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Reviewed-by: Paulo Zanoni
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/2019031918
From: Daniele Ceraolo Spurio
Remove unneeded usage of dev_priv from 1 extra function.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Paulo Zanoni
Reviewed-by: Paulo Zanoni
Signed-off-by: Chris Wilson
Link:
https://patchwork.freedesktop.org/patch/msgid/20190319183543.13679-6-daniele.ceraolospu...
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