Op 18-03-2019 om 19:15 schreef Ville Syrjälä:
> On Mon, Mar 18, 2019 at 04:13:57PM +0100, Maarten Lankhorst wrote:
>> Op 18-03-2019 om 15:18 schreef Ville Syrjälä:
>>> On Mon, Mar 18, 2019 at 03:07:18PM +0100, Maarten Lankhorst wrote:
Signed-off-by: Maarten Lankhorst
---
drivers/gp
== Series Details ==
Series: drm/i915/psr: remove drmP.h include that crept in
URL : https://patchwork.freedesktop.org/series/58136/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5768_full -> Patchwork_12501_full
Summary
--
Gen platforms support multiple gamma modes, currently
it's hard coded to operate only in 1 specific mode.
This patch adds a property to make gamma mode programmable.
User can select which mode should be used for a particular
usecase or scenario.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i91
Implement get and set property handler for multi segment gamma
mode.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_display.c | 46
drivers/gpu/drm/i915/intel_drv.h | 12 ++
2 files changed, 58 insertions(+)
diff --git a/drivers/gpu/dr
Gen11 introduced a new gamma mode i.e, multi segmented
gamma mode. Added support for the same.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 105 +++--
1 file changed, 90 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel
Add macros to define multi segmented gamma registers
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 31a3020..44ca13b 100644
--- a/drivers
This series adds support for programmable gamma modes and
exposes a property interface for the same. Also added,
support for mult segment gamma mode introduced in ICL+
Uma Shankar (7):
drm/i915: Add gamma mode property
drm/i915: Add intel crtc set and get property callback
drm/i915: Add Supp
Add intel crtc set and get property callbacks. Currently
added for gamma mode property set and get implementation.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_display.c | 58
1 file changed, 58 insertions(+)
diff --git a/drivers/gpu/drm/i915/in
Multi Segment Gamma Mode is added in Gen11+ platforms.
Added a property interface to enable that.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_drv.h| 1 +
drivers/gpu/drm/i915/intel_color.c | 23 +++
include/uapi/drm/i915_drm.h| 14 ++
3 f
Added support for ICL platform multi segment gamma
capabilties and attached the property, exposing the
same to userspace.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i
== Series Details ==
Series: Add Multi Segment Gamma Support
URL : https://patchwork.freedesktop.org/series/58169/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
21ee2af67f85 drm/i915: Add gamma mode property
a2f2f0bff701 drm/i915: Add intel crtc set and get property callback
e8
== Series Details ==
Series: Add Multi Segment Gamma Support
URL : https://patchwork.freedesktop.org/series/58169/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Add gamma mode property
+drivers/gpu/drm/i915/intel_color.c:131:1: warning: symb
On Tue, 19 Mar 2019, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915/psr: remove drmP.h include that crept in
> URL : https://patchwork.freedesktop.org/series/58136/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_5768_full -> Patchwork_12501_full
>
On Mon, 18 Mar 2019, Ville Syrjälä wrote:
> On Mon, Mar 18, 2019 at 06:00:19PM +0200, Jani Nikula wrote:
>> We no longer allow mixed C99 and kernel types, and the preference is to
>> use kernel types exclusively. Fix the C99 types that have crept in since
>> the mass conversion. No functional chan
Add Plane Degamma as a blob property and plane degamma size as
a range property.
v2: Rebase
v3: Fixed Sean, Paul's review comments. Moved the property from
mode_config to drm_plane. Created a helper function to instantiate
these properties and removed from drm_mode_create_standard_properties
Adde
Enable and initialize plane color features.
v2: Rebase and some cleanup
v3: Updated intel_plane_color_init to call
drm_plane_color_create_prop function, which will
in turn create plane color properties.
v4: Rebase
v5: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_drv.h
Update the plane gamma and degamma feature in the
plane state and eventually program to PLANE_COLOR_CTL.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_color.c | 6 ++
drivers/gpu/drm/i915/intel_display.c | 6 +-
3 files changed, 1
This is how a typical display color hardware pipeline looks like:
+---+
|RAM|
| +--++-++-+ |
| | FB 1 || FB 2 || FB N| |
| +--++-++-+
Add Plane color capabilties, support for
degamma and gamma added.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 12 +---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
drivers/gpu/drm/i915/intel_drv.h | 3 ++-
drivers/gpu/drm/i915/intel_sprite.c | 11 ++
Implement plane CSC on ICL.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_color.c | 86
drivers/gpu/drm/i915/intel_display.c | 3 ++
3 files changed, 90 insertions(+)
diff --git a/drivers/gpu/drm/i9
Existing LUT precision structure is having only 16 bit
precision. This is not enough for upcoming enhanced hardwares
and advance usecases like HDR processing. Hence added a new
structure with 32 bit precision values. Also added the code,
for extracting the same from values passed from userspace.
v
Implement Plane Gamma on ICL.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 75 ++
1 file changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 504c046..22790b4 100644
--- a
Add register definitions for ICL Plane Degamma.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 42 +
1 file changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0beed42..b9a2084 1
Load plane color luts as part of atomic plane updates.
This will be done only if the plane color luts are changed.
v4: Rebase
v5: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 3 +++
drivers/gpu/drm/i915/intel_color.c| 8
drivers/gpu/drm/i91
Add Plane Gamma Register definitions for ICL+
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 42 -
1 file changed, 41 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b9a20
Define helper function to enable Plane color features
to attach plane color properties to plane structure.
v2: Rebase
v3: Modiefied the function to use updated property names.
v4: Rebase
v5: Moved helper function to drm_color_mgmt.c file to have all
color operations consolidated at one place. N
Add a blob property for plane CSC usage.
v2: Rebase
v3: Fixed Sean, Paul's review comments. Moved the property from
mode_config to drm_plane. Created a helper function to instantiate
these properties and removed from drm_mode_create_standard_properties
Added property documentation as suggested by
Implement Plane Gamma feature for BDW and Gen9 platforms.
v2: Used newly added drm_color_lut_ext structure for enhanced
precision for Gamma LUT entries.
v3: Rebase
v4: Used extended function for LUT extraction (pointed by
Alexandru).
v5: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/
Enable Plane Degamma for ICL.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 86 ++
1 file changed, 86 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index afb1d00..504c046 100644
--- a
Define Register macros for plane CSC.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 44 +
1 file changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7e2e746..38e0c46 100644
---
Add plane gamma as blob property and size as a
range property.
v2: Rebase
v3: Fixed Sean, Paul's review comments. Moved the property from
mode_config to drm_plane. Created a helper function to instantiate
these properties and removed from drm_mode_create_standard_properties
Added property documen
On Mon, 18 Mar 2019, Shaobo He wrote:
> I see. In light of this commit, is it a better solution than adding
> NULL-checks
> is to replace the if branch conditioned by `WARN_ON` with simply `WARN` like
> the
> following,
>
> struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *d
== Series Details ==
Series: Add Multi Segment Gamma Support
URL : https://patchwork.freedesktop.org/series/58169/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5770 -> Patchwork_12509
Summary
---
**FAILURE**
Seri
tis 2019-03-19 klockan 14:00 +0530 skrev Uma Shankar:
> Multi Segment Gamma Mode is added in Gen11+ platforms.
> Added a property interface to enable that.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/i915_drv.h| 1 +
> drivers/gpu/drm/i915/intel_color.c | 23
== Series Details ==
Series: drm/i915: Clean up intel_color_check()
URL : https://patchwork.freedesktop.org/series/58137/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5768_full -> Patchwork_12502_full
Summary
---
**
== Series Details ==
Series: Add Plane Color Properties (rev6)
URL : https://patchwork.freedesktop.org/series/30875/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ac8ffabdea94 drm: Add Enhanced Gamma LUT precision structure
cb4da76aa060 drm: Add Plane Degamma properties
-:180:
== Series Details ==
Series: Add Plane Color Properties (rev6)
URL : https://patchwork.freedesktop.org/series/30875/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm: Add Enhanced Gamma LUT precision structure
+drivers/gpu/drm/drm_color_mgmt.c:146:45
== Series Details ==
Series: Add Plane Color Properties (rev6)
URL : https://patchwork.freedesktop.org/series/30875/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5771 -> Patchwork_12510
Summary
---
**SUCCESS**
No
On Mon, Mar 18, 2019 at 05:11:30PM -0700, Matt Roper wrote:
> On Tue, Mar 12, 2019 at 10:58:44PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > skl_build_pipe_wm() is quite pointless now. Just inline it into
>
> I think you actually mean skl_update_pipe_wm(), right?
Indeed.
>
> T
On Tue, Mar 12, 2019 at 10:58:39PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Currently we just assume that 32 or 8 blocks of ddb is sufficient
> for the cursor. The 32 might be, but the 8 is certainly not. The
> minimum we need is at least what level 0 watermarks need, but that
> is a
On Mon, Mar 18, 2019 at 04:33:51PM -0700, Lucas De Marchi wrote:
> On Mon, Mar 18, 2019 at 08:53:23PM +0200, Ville Syrjälä wrote:
> >On Mon, Mar 18, 2019 at 11:40:34AM -0700, Lucas De Marchi wrote:
> >> On Mon, Mar 18, 2019 at 03:31:52PM +0200, Ville Syrjälä wrote:
> >> >On Fri, Mar 15, 2019 at 05:
On Tue, Mar 19, 2019 at 08:28:58AM +0100, Maarten Lankhorst wrote:
> Op 18-03-2019 om 19:15 schreef Ville Syrjälä:
> > On Mon, Mar 18, 2019 at 04:13:57PM +0100, Maarten Lankhorst wrote:
> >> Op 18-03-2019 om 15:18 schreef Ville Syrjälä:
> >>> On Mon, Mar 18, 2019 at 03:07:18PM +0100, Maarten Lankho
Some users require that when a master batch is executed on one particular
engine, a companion batch is run simultaneously on a specific slave
engine. For this purpose, we introduce virtual engine bonding, allowing
maps of master:slaves to be constructed to constrain which physical
engines a virtual
If a test fails, we quite often mark the device as wedged. Provide the
stub functions so that we can wedge the mock device, and avoid exploding
on test failures.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109981
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/
There is a desire to split a task onto two engines and have them run at
the same time, e.g. scanline interleaving to spread the workload evenly.
Through the use of the out-fence from the first execbuf, we can
coordinate secondary execbuf to only become ready simultaneously with
the first, so that w
When we return pages to the system, we ensure that they are marked as
being in the CPU domain since any external access is uncontrolled and we
must assume the worst. This means that we need to always flush the pages
on acquisition if we need to use them on the GPU, and from the beginning
have used
In later patches, it became apparent that userspace can see a partially
constructed GEM context and begin using it before it was ready, to much
hilarity. Close this window of opportunity by lifting the registration of
the context with userspace (the insertion of the context into the filp's
idr) to
Previously, our view has been always to run the engines independently
within a context. (Multiple engines happened before we had contexts and
timelines, so they always operated independently and that behaviour
persisted into contexts.) However, at the user level the context often
represents a singl
In the next patch, we will want to configure the slave request
depending on which physical engine the master request is executed on.
For this, we introduce a callback from the execute fence to convey this
information.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i
Allow the user to specify a local engine index (as opposed to
class:index) that they can use to refer to a preset engine inside the
ctx->engine[] array defined by an earlier I915_CONTEXT_PARAM_ENGINES.
This will be useful for setting SSEU parameters on virtual engines that
are local to the context
We want to use intel_engine_mask_t inside i915_request.h, which means
extracting it from the general header file mess and placing it inside a
types.h. A knock on effect is that the compiler wants to warn about
type-contraction of ALL_ENGINES into intel_engine_maskt_t, so prepare
for the worst.
v2:
Having allowed the user to define a set of engines that they will want
to only use, we go one step further and allow them to bind those engines
into a single virtual instance. Submitting a batch to the virtual engine
will then forward it to any one of the set in a manner as best to
distribute load.
Define a mutex for the exclusive use of interacting with the per-file
context-idr, that was previously guarded by struct_mutex. This allows us
to reduce the coverage of struct_mutex, with a view to removing the last
bits coordinating GEM context later. (In the short term, we avoid taking
struct_mut
The timeline->name is only used for convenience in pretty printing the
i915_request.fence->ops->get_timeline_name() and it is just as
convenient to pull it from the gem_context directly. The few instances
of its use inside GEM_TRACE() has proven more of a nuisance than
helpful, so not worth saving
A usecase arose out of handling context recovery in mesa, whereby they
wish to recreate a context with fresh logical state but preserving all
other details of the original. Currently, they create a new context and
iterate over which bits they want to copy across, but it would much more
convenient i
It can be useful to have a single ioctl to create a context with all
the initial parameters instead of a series of create + setparam + setparam
ioctls. This extension to create context allows any of the parameters
to be passed in as a linked list to be applied to the newly constructed
context.
v2:
The user_handle need only be known by userspace for it to lookup the
context via the idr; internally we have no use for it.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 ++--
drivers/gpu/drm/i915/i915_gem_context.c | 23 ---
drivers/gpu
Over the last few years, we have debated how to extend the user API to
support an increase in the number of engines, that may be sparse and
even be heterogeneous within a class (not all video decoders created
equal). We settled on using (class, instance) tuples to identify a
specific engine, with a
In preparation to making the ppGTT binding for a context explicit (to
facilitate reusing the same ppGTT between different contexts), allow the
user to create and destroy named ppGTT.
v2: Replace global barrier for swapping over the ppgtt and tlbs with a
local context barrier (Tvrtko)
v3: serialise
An idea for extending uABI inspired by Vulkan's extension chains.
Instead of expanding the data struct for each ioctl every time we need
to add a new feature, define an extension chain instead. As we add
optional interfaces to control the ioctl, we define a new extension
struct that can be linked i
== Series Details ==
Series: series starting with [01/18] drm/i915/selftests: Provide stub reset
functions
URL : https://patchwork.freedesktop.org/series/58179/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4af79bb9ca20 drm/i915/selftests: Provide stub reset functions
383e05f9
There has unfortunately been a conflict with the following 3 commits:
commit e9961ab95af81b8d29054361cd5f0c575102cf87
Author: Ayan Kumar Halder
Date: Fri Nov 9 17:21:12 2018 +
drm: Added a new format DRM_FORMAT_XVYU2101010
commit 7ba0fee247ee7a36b3bfbed68f6988d980aa3aa3
Author: Brian S
== Series Details ==
Series: series starting with [01/18] drm/i915/selftests: Provide stub reset
functions
URL : https://patchwork.freedesktop.org/series/58179/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/selftests: Provide stub reset func
On 18/03/2019 00:15, Carlos Santa wrote:
On Mon, 2019-03-11 at 10:39 +, Tvrtko Ursulin wrote:
On 08/03/2019 03:16, Carlos Santa wrote:
On Fri, 2019-03-01 at 09:36 +, Chris Wilson wrote:
Quoting Carlos Santa (2019-02-21 02:58:16)
+#define GEN8_WATCHDOG_1000US(dev_priv)
watchdog_to_
== Series Details ==
Series: series starting with [01/18] drm/i915/selftests: Provide stub reset
functions
URL : https://patchwork.freedesktop.org/series/58179/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5772 -> Patchwork_12511
=
== Series Details ==
Series: drm/fourcc: Fix conflicting Y41x definitions
URL : https://patchwork.freedesktop.org/series/58182/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
68cd4376136d drm/fourcc: Fix conflicting Y41x definitions
-:8: ERROR:GIT_COMMIT_ID: Please use git commi
On Tue, Mar 19, 2019 at 01:15:55PM +0200, Ville Syrjälä wrote:
> On Tue, Mar 19, 2019 at 08:28:58AM +0100, Maarten Lankhorst wrote:
> > Op 18-03-2019 om 19:15 schreef Ville Syrjälä:
> > > On Mon, Mar 18, 2019 at 04:13:57PM +0100, Maarten Lankhorst wrote:
> > >> Op 18-03-2019 om 15:18 schreef Ville
On 19/03/2019 12:39, Tvrtko Ursulin wrote:
On 18/03/2019 00:15, Carlos Santa wrote:
On Mon, 2019-03-11 at 10:39 +, Tvrtko Ursulin wrote:
On 08/03/2019 03:16, Carlos Santa wrote:
On Fri, 2019-03-01 at 09:36 +, Chris Wilson wrote:
Quoting Carlos Santa (2019-02-21 02:58:16)
+#defin
The user_handle need only be known by userspace for it to lookup the
context via the idr; internally we have no use for it.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 ++--
drivers/gpu/drm/i915/i915_gem_context.c | 23 ---
drivers/gpu
On Tue, Mar 19, 2019 at 01:17:02PM +0100, Maarten Lankhorst wrote:
> There has unfortunately been a conflict with the following 3 commits:
>
> commit e9961ab95af81b8d29054361cd5f0c575102cf87
> Author: Ayan Kumar Halder
> Date: Fri Nov 9 17:21:12 2018 +
> drm: Added a new format DRM_FORM
== Series Details ==
Series: series starting with [1/6] drm/i915: Reorder gen3/4 swizzle detection
logic
URL : https://patchwork.freedesktop.org/series/58139/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5770_full -> Patchwork_12503_full
=
== Series Details ==
Series: drm/fourcc: Fix conflicting Y41x definitions
URL : https://patchwork.freedesktop.org/series/58182/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5772 -> Patchwork_12512
Summary
---
**SUCC
== Series Details ==
Series: series starting with [01/18] drm/i915/selftests: Provide stub reset
functions (rev2)
URL : https://patchwork.freedesktop.org/series/58179/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
58fb48773f00 drm/i915/selftests: Provide stub reset functions
8
On 18/03/2019 16:56, Ville Syrjala wrote:
From: Ville Syrjälä
g33/i964g/g45 are the exceptional cases when it comes to
the swizzle detectiong. Let's reorder the code to handle
them first and let everything else be handled by the
else branch. This allows us to unset .is_mobile for the
desktop P
== Series Details ==
Series: series starting with [01/18] drm/i915/selftests: Provide stub reset
functions (rev2)
URL : https://patchwork.freedesktop.org/series/58179/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/selftests: Provide stub res
On 18/03/2019 16:56, Ville Syrjala wrote:
From: Ville Syrjälä
Make the code self-documenting by introducing i9xx_has_pfit().
Also make PNV an exceptional case so that we can unset
.is_mobile for the desktop variant.
Cc: Tvrtko Ursulin
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/
On 18/03/2019 16:56, Ville Syrjala wrote:
From: Ville Syrjälä
Add a small helper to determine if we have the panel power
sequencer or not. We'll make PNV an exceptional case so
that we can unset .is_mobile for the desktop variant.
Cc: Tvrtko Ursulin
Signed-off-by: Ville Syrjälä
---
driver
On 18/03/2019 16:56, Ville Syrjala wrote:
From: Ville Syrjälä
We want to allow the desktop PNV to not have .is_mobile set. To
that end let's add a small helper to determine if the platform
has the ASLE interrupt (or equivalent). Supposdely both PNV
variants have it.
Cc: Tvrtko Ursulin
Signed
On 18/03/2019 16:56, Ville Syrjala wrote:
From: Ville Syrjälä
To allow unsetting .is_mobile for the desktop variant
of PNV fix up the cdclk code to select the mobile HPLLVCO register
for both PNV variants.
Cc: Tvrtko Ursulin
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_cdcl
== Series Details ==
Series: series starting with [01/18] drm/i915/selftests: Provide stub reset
functions (rev2)
URL : https://patchwork.freedesktop.org/series/58179/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5772 -> Patchwork_12513
==
On 18/03/2019 16:56, Ville Syrjala wrote:
From: Ville Syrjälä
The current gen2 DPLL readout code:
* assumes i845/i865 have LVDS which is not true
* assumes only pipe B can drive LVDS (true, but makes
the code appear a bit magical)
* hard to parse in general
Clean it up by checking for i85x
On 19/03/2019 11:57, Chris Wilson wrote:
In later patches, it became apparent that userspace can see a partially
constructed GEM context and begin using it before it was ready, to much
hilarity. Close this window of opportunity by lifting the registration of
the context with userspace (the inser
32 is too many for the likes of kbl, and in order to insert that many
requests into the ring requires us to declare the first few hung --
understandably a slow and unexpected process. Instead, measure the size
of a singe requests and use that to estimate the upper bound on the
chain length we can u
Quoting Tvrtko Ursulin (2019-03-19 13:41:37)
>
> On 19/03/2019 11:57, Chris Wilson wrote:
> > In later patches, it became apparent that userspace can see a partially
> > constructed GEM context and begin using it before it was ready, to much
> > hilarity. Close this window of opportunity by liftin
On Tue, Mar 19, 2019 at 01:17:02PM +0100, Maarten Lankhorst wrote:
> There has unfortunately been a conflict with the following 3 commits:
>
> commit e9961ab95af81b8d29054361cd5f0c575102cf87
> Author: Ayan Kumar Halder
> Date: Fri Nov 9 17:21:12 2018 +
> drm: Added a new format DRM_FORM
== Series Details ==
Series: drm/i915: Fix PSR2 selective update corruption after PSR1 setup (rev5)
URL : https://patchwork.freedesktop.org/series/57900/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5770_full -> Patchwork_12504_full
===
On Tue, Mar 19, 2019 at 01:24:16PM +, Tvrtko Ursulin wrote:
>
> On 18/03/2019 16:56, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Make the code self-documenting by introducing i9xx_has_pfit().
> > Also make PNV an exceptional case so that we can unset
> > .is_mobile for the desktop v
On Tue, Mar 19, 2019 at 01:34:31PM +, Tvrtko Ursulin wrote:
>
> On 18/03/2019 16:56, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > The current gen2 DPLL readout code:
> > * assumes i845/i865 have LVDS which is not true
> > * assumes only pipe B can drive LVDS (true, but makes
> >t
== Series Details ==
Series: series starting with [1/2] drm/i915/cml: Add CML PCI IDS
URL : https://patchwork.freedesktop.org/series/58147/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5770_full -> Patchwork_12505_full
Sum
From: Ville Syrjälä
Make the code self-documenting by introducing i9xx_has_pfit().
Also make PNV an exceptional case so that we can unset
.is_mobile for the desktop variant.
v2: s/gen4/gen>=4/ (Tvrtko)
Cc: Tvrtko Ursulin
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_display.c |
== Series Details ==
Series: series starting with [1/3] drm/i915: Add some missing curly braces
URL : https://patchwork.freedesktop.org/series/58148/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5770_full -> Patchwork_12506_full
===
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Lock the
gem_context->active_list while dropping the link
URL : https://patchwork.freedesktop.org/series/58151/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5770_full -> Patchwork_12507_full
===
== Series Details ==
Series: series starting with [v2,1/2] drm/i915: Add support for retrying hotplug
URL : https://patchwork.freedesktop.org/series/58156/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5770_full -> Patchwork_12508_full
=
On Mon, Mar 18, 2019 at 01:34:37PM -0700, Rodrigo Vivi wrote:
> On Mon, Mar 18, 2019 at 10:26:51PM +0200, Ville Syrjala wrote:
> > From: Ville Syrjälä
> >
> > Sprinkle some curly braces in accordance with the coding style.
> >
> > Signed-off-by: Ville Syrjälä
>
> Reviewed-by: Rodrigo Vivi
Th
== Series Details ==
Series: drm/i915/selftests: Calculate maximum ring size for preemption chain
URL : https://patchwork.freedesktop.org/series/58188/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5772 -> Patchwork_12514
S
On Mon, 18 Mar 2019, Ville Syrjälä wrote:
> On Mon, Mar 18, 2019 at 09:45:16PM +0100, Michal Wajdeczko wrote:
>> > Make things look a bit nicer by passing dev_priv to
>>
>> In other places we are changing naming from dev_priv to i915.
>> Can we do the same here ?
>
> The display code uses dev_pri
== Series Details ==
Series: series starting with [1/6] drm/i915: Reorder gen3/4 swizzle detection
logic (rev2)
URL : https://patchwork.freedesktop.org/series/58139/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5773 -> Patchwork_12515
From: Ville Syrjälä
Currently we just assume that 32 or 8 blocks of ddb is sufficient
for the cursor. The 32 might be, but the 8 is certainly not. The
minimum we need is at least what level 0 watermarks need, but that
is a bit restrictive, so instead let's calculate what level 7
would need for a
Op 19-03-2019 om 14:02 schreef Ville Syrjälä:
> On Tue, Mar 19, 2019 at 01:17:02PM +0100, Maarten Lankhorst wrote:
>> There has unfortunately been a conflict with the following 3 commits:
>>
>> commit e9961ab95af81b8d29054361cd5f0c575102cf87
>> Author: Ayan Kumar Halder
>> Date: Fri Nov 9 17:21:
On Tue, Mar 19, 2019 at 05:06:36PM +0100, Maarten Lankhorst wrote:
> Op 19-03-2019 om 14:02 schreef Ville Syrjälä:
> > On Tue, Mar 19, 2019 at 01:17:02PM +0100, Maarten Lankhorst wrote:
> >> There has unfortunately been a conflict with the following 3 commits:
> >>
> >> commit e9961ab95af81b8d29054
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