From: Ville Syrjälä
Rename the dimm info structs for clarity.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.c | 18 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +-
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/dr
From: Ville Syrjälä
Pass the dimm struct to skl_is_16gb_dimm() rather than passing each
value separately. And let's replace the hardcoded set of values with
some simple arithmetic.
Also fix the byte vs. bit inconsistency in the debug message,
and polish the wording otherwise as well.
Signed-off
From: Ville Syrjälä
Reduce the code duplication a bit by sharing the same
code for parsing both DIMMs on a channel.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.c | 44 ++---
1 file changed, 24 insertions(+), 20 deletions(-)
diff --git a/drivers/g
From: Ville Syrjälä
Polish the bxt DIMM parsing by extracting a few small helpers.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.c | 79 ++---
1 file changed, 52 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/
From: Ville Syrjälä
The BXT code for parsing DIMM info works for GLK too. Let's
dig it out even if we might not need it immediately.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i91
From: Ville Syrjälä
Decouple intel_is_dram_symmetric() from the raw register values
by comparing just the dram_channel_info structs.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.c | 28
1 file changed, 12 insertions(+), 16 deletions(-)
diff --git
From: Ville Syrjälä
Remove the pointless zero initialization of bunch of things
(the thing is kzalloc()ed).
Also throw out the mostly useless on-stack string. I think
it'll be clear enough from the logs that 0 means unknown.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.c | 1
From: Ville Syrjälä
We'll need information about the memory configuration on cnl+ too.
Extend the code to parse the slightly changed register layout.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.c | 69 -
drivers/gpu/drm/i915/i915_reg.h | 17 ++
From: Ville Syrjälä
We'll need to know the memory type in the system for some
bandwidth limitations and whatnot. Let's read that out on
gen9+.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.c | 83 +++--
drivers/gpu/drm/i915/i915_drv.h | 7 +++
driv
Quoting Ville Syrjala (2019-02-25 20:29:00)
> From: Ville Syrjälä
>
> The BXT DUNIT register tells us the size of each DRAM device
> in Gb. We want to report the size of the whole DIMM in GB, so
> that it matches how we report it for non-LP platforms.
>
> Signed-off-by: Ville Syrjälä
> ---
> d
On Fri, Feb 22, 2019 at 03:23:22PM -0800, Lucas De Marchi wrote:
> Let the MG plls have their own hooks since it shares very little with
> other PLL types. It's also better so the platform info contains the info
> if the PLL is for MG PHY rather than relying on the PLL ids.
>
> Signed-off-by: Luca
On Fri, Feb 22, 2019 at 03:23:24PM -0800, Lucas De Marchi wrote:
> Use the first 3 bits of dpll_info.platform_flags to mark the type of the
> PLL instead of relying on the IDs. This is more future proof for
> allowing the same set of functions to be reused, even if the IDs change.
>
> The warning
On Mon, Feb 25, 2019 at 08:35:08PM +, Chris Wilson wrote:
> Quoting Ville Syrjala (2019-02-25 20:29:00)
> > From: Ville Syrjälä
> >
> > The BXT DUNIT register tells us the size of each DRAM device
> > in Gb. We want to report the size of the whole DIMM in GB, so
> > that it matches how we rep
Quoting Ville Syrjälä (2019-02-25 20:48:10)
> On Mon, Feb 25, 2019 at 08:35:08PM +, Chris Wilson wrote:
> > Quoting Ville Syrjala (2019-02-25 20:29:00)
> > > From: Ville Syrjälä
> > >
> > > The BXT DUNIT register tells us the size of each DRAM device
> > > in Gb. We want to report the size of
== Series Details ==
Series: Polish DRAM information readout code
URL : https://patchwork.freedesktop.org/series/57213/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
00f769077034 drm/i915: Store DIMM rank information as a number
6000a48eb1cf drm/i915: Extract functions to deriv
== Series Details ==
Series: drm/tinydrm: Remove tinydrm_device
URL : https://patchwork.freedesktop.org/series/57197/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5658_full -> Patchwork_12297_full
Summary
---
**SUCC
== Series Details ==
Series: Polish DRAM information readout code
URL : https://patchwork.freedesktop.org/series/57213/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Store DIMM rank information as a number
-O:drivers/gpu/drm/i915/i915_drv.c:
On Mon, Feb 25, 2019 at 08:57:45PM +, Chris Wilson wrote:
> Quoting Ville Syrjälä (2019-02-25 20:48:10)
> > On Mon, Feb 25, 2019 at 08:35:08PM +, Chris Wilson wrote:
> > > Quoting Ville Syrjala (2019-02-25 20:29:00)
> > > > From: Ville Syrjälä
> > > >
> > > > The BXT DUNIT register tells
== Series Details ==
Series: Polish DRAM information readout code
URL : https://patchwork.freedesktop.org/series/57213/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5659 -> Patchwork_12301
Summary
---
**SUCCESS**
On Mon, Feb 25, 2019 at 10:45:34PM +0200, Ville Syrjälä wrote:
On Fri, Feb 22, 2019 at 03:23:24PM -0800, Lucas De Marchi wrote:
Use the first 3 bits of dpll_info.platform_flags to mark the type of the
PLL instead of relying on the IDs. This is more future proof for
allowing the same set of funct
On Fri, 2019-02-22 at 22:14 -0800, Dhinakaran Pandiyan wrote:
> On Sat, 2019-02-23 at 02:48 +, Souza, Jose wrote:
> > On Fri, 2019-02-22 at 18:13 -0800, Dhinakaran Pandiyan wrote:
> > > On Wed, 2019-02-13 at 18:02 -0800, José Roberto de Souza wrote:
> > > > As stated in CRC_CTL spec, after PSR
On Mon, Feb 25, 2019 at 09:28:06PM +0200, Ville Syrjälä wrote:
On Fri, Feb 22, 2019 at 04:34:48PM -0800, Lucas De Marchi wrote:
No change in behavior. Just removing the unused bits since it makes it
easier to compare them on new platforms and one of them was wrong
(PP_SEQUENCE_STATE_ON_S1_0 vs t
On Mon, Feb 25, 2019 at 10:42:12PM +0200, Ville Syrjälä wrote:
On Fri, Feb 22, 2019 at 03:23:22PM -0800, Lucas De Marchi wrote:
Let the MG plls have their own hooks since it shares very little with
other PLL types. It's also better so the platform info contains the info
if the PLL is for MG PHY
No change in behavior, this only allows to more easily follow the flow
of gen8_de_irq_handler without the mask assignments for each platform.
This also re-organizes the branches a little bit, so the one-off case
for CNL_WITH_PORT_F is separate from the generic gen >= 11.
v2: rename de_port_iir_aux
== Series Details ==
Series: series starting with [1/4] drm/i915: Replace global_seqno with a
hangcheck heartbeat seqno
URL : https://patchwork.freedesktop.org/series/57203/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5659_full -> Patchwork_12298_full
==
== Series Details ==
Series: drm/i915: extract AUX mask assignment to separate function (rev2)
URL : https://patchwork.freedesktop.org/series/57119/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5659 -> Patchwork_12302
Summ
== Series Details ==
Series: drm/i915: Infoframe precompute/check (rev7)
URL : https://patchwork.freedesktop.org/series/49983/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5659_full -> Patchwork_12299_full
Summary
---
Quoting Dave Airlie (2019-02-25 12:24:48)
> On Tue, 19 Feb 2019 at 23:32, Joonas Lahtinen
> wrote:
> >
> > + dri-devel mailing list, especially for the buddy allocator part
> >
> > Quoting Dave Airlie (2019-02-15 02:47:07)
> > > On Fri, 15 Feb 2019 at 00:57, Matthew Auld wrote:
> > > >
> > > > In
== Series Details ==
Series: drm/i915: Yet another if/else sort of newer to older platforms. (rev2)
URL : https://patchwork.freedesktop.org/series/57112/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5659_full -> Patchwork_12300_full
===
On Mon, Feb 25, 2019 at 9:35 PM Joonas Lahtinen
wrote:
>
> Quoting Dave Airlie (2019-02-25 12:24:48)
> > On Tue, 19 Feb 2019 at 23:32, Joonas Lahtinen
> > wrote:
> > >
> > > + dri-devel mailing list, especially for the buddy allocator part
> > >
> > > Quoting Dave Airlie (2019-02-15 02:47:07)
> >
== Series Details ==
Series: Polish DRAM information readout code
URL : https://patchwork.freedesktop.org/series/57213/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5659_full -> Patchwork_12301_full
Summary
---
**SU
Hey,
Op 21-02-2019 om 01:28 schreef Matt Roper:
> Some display controllers can be programmed to present non-black colors
> for pixels not covered by any plane (or pixels covered by the
> transparent regions of higher planes). Compositors that want a UI with
> a solid color background can potentia
On 25/02/2019 18:40, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2019-02-25 17:59:40)
On 25/02/2019 16:23, Chris Wilson wrote:
static inline struct i915_priolist *to_priolist(struct rb_node *rb)
{
return rb_entry(rb, struct i915_priolist, node);
@@ -2206,6 +2212,10 @@ static u32
This patch adds a drm blob property to selected connectors.
And also adds capability to parse the new HDCP1.4 srm blob passed
through cp_srm_property.
The revocated KSV list and their counts are stored in
the intel_hdcp. This list should be used for revocation check
of BKSVs in first stage HDCP au
This patch adds a drm blob property to the selected connector.
This property will be used to pass the SRM Blob ID from userspace
to kernel.
Revocated ksv list from SRM Table will be used by the kernel in the HDCP
authentication.
Kernel doesn't validate the incoming SRM table or store it in
non-vo
This patch adds a DRM ENUM property to the selected connectors.
This property is used for pass the protected content's type
from userspace to kernel HDCP authentication.
Type of the stream is decided by the protected content providers as
Type 0/1.
Type 0 content can be rendered on any HDCP protec
Attaches the content type property for HDCP2.2 capable connectors.
Implements the update of content type from property and apply the
restriction on HDCP version selection.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_ddi.c | 21 +++--
drivers/gpu/drm/i915/intel_dr
Hi Hans,
I love your patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on next-20190225]
[cannot apply to v5.0-rc8]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https
HDCP2.2 phase-II mojorly adds below features:
Addition of three connector properties
CP_Content_Type
CP_SRM
CP_Downstream_Info
parsing for HDCP1.4 and 2.2 SRM Blobs
Once HDCP1.4/2.2 authentication is completed gathering the all
Adding the HDCP2.2 capability of HDCP src and sink info into debugfs
entry "i915_hdcp_sink_capability"
This helps the userspace tests to skip the HDCP2.2 test on non HDCP2.2
sinks.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/i915_debugfs.c | 13 +++--
drivers/gpu/drm/i915/intel
This patch adds CP downstream info blob property to the
connectors. This enables the Userspace to read the information of HDCP
authenticated downstream topology.
Driver will updated this blob with all downstream information at the
end of the authentication.
Userspace need this informations to con
SRM blob with hdcp2 id is parsed and parsed list of revoked ids is
used in the authentication process to identify the compromised HDCP
sinks.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_hdcp.c | 86 +--
include/drm/drm_hdcp.h| 20 +++
KSV list revocated by DCP LLC is provided as SRM Blob to kernel.
Which is parsed and stored in intel_hdcp->revocated_ksv_list.
This patch adds the revocation check for BKSV and KSV_FIFO in HDCP1.4
authentication.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_hdcp.c | 67 +++
Populates the downstream info for HDCP2.2 encryption also. On success
of encryption Blob is updated.
Additional two variable are added to downstream info blob. Such as
ver_in_force and content type.
Signed-off-by: Ramalingam C
---
drivers/gpu/drm/i915/intel_hdcp.c | 29 +
Implements drm blob property cp_downstream_info property on HDCP
capable connectors.
Downstream topology info is gathered across authentication stages
and stored in intel_hdcp. When HDCP authentication is complete,
new blob with latest downstream topology information is updated to
cp_downstream_in
Quoting Tvrtko Ursulin (2019-02-26 07:34:37)
>
> On 25/02/2019 18:40, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2019-02-25 17:59:40)
> >>
> >> On 25/02/2019 16:23, Chris Wilson wrote:
> >>>static inline struct i915_priolist *to_priolist(struct rb_node *rb)
> >>>{
> >>>return
To determine whether an engine has 'stuck', we simply check whether or
not is still on the same seqno for several seconds. To keep this simple
mechanism intact over the loss of a global seqno, we can simply add a
new global heartbeat seqno instead. As we cannot know the sequence in
which requests w
On 26/02/2019 07:49, Chris Wilson wrote:
To determine whether an engine has 'stuck', we simply check whether or
not is still on the same seqno for several seconds. To keep this simple
mechanism intact over the loss of a global seqno, we can simply add a
new global heartbeat seqno instead. As we
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