On 2018.12.03 15:35:17 +0800, Tina Zhang wrote:
> Create and initialize vGPU meta framebuffers during vGPU's creation.
> Each meta framebuffer is an intel_framebuffer. Userspace can get the
> userspace visible identifier of that meta framebuffer by accessing
> plane_id_index attribute.
>
> For exa
On 2018.12.03 16:21:04 +0800, Zhenyu Wang wrote:
> On 2018.12.03 15:35:17 +0800, Tina Zhang wrote:
> > Create and initialize vGPU meta framebuffers during vGPU's creation.
> > Each meta framebuffer is an intel_framebuffer. Userspace can get the
> > userspace visible identifier of that meta framebuf
> -Original Message-
> From: Zhenyu Wang [mailto:zhen...@linux.intel.com]
> Sent: Monday, December 3, 2018 4:21 PM
> To: Zhang, Tina
> Cc: intel-gfx@lists.freedesktop.org; Kondapally, Kalyan
> ; intel-gvt-...@lists.freedesktop.org; Wang, Zhi
> A
> Subject: Re: [RFC PATCH 2/7] drm/i915/g
> -Original Message-
> From: Zhang, Tina
> Sent: Monday, December 3, 2018 4:53 PM
> To: 'Zhenyu Wang'
> Cc: intel-gfx@lists.freedesktop.org; Kondapally, Kalyan
> ; intel-gvt-...@lists.freedesktop.org; Wang, Zhi
> A
> Subject: RE: [RFC PATCH 2/7] drm/i915/gvt: Use meta fbs to stand for v
> -Original Message-
> From: Zhenyu Wang [mailto:zhen...@linux.intel.com]
> Sent: Monday, December 3, 2018 4:36 PM
> To: Zhang, Tina
> Cc: intel-gfx@lists.freedesktop.org; Kondapally, Kalyan
> ; intel-gvt-...@lists.freedesktop.org; Wang, Zhi
> A
> Subject: Re: [RFC PATCH 2/7] drm/i915/g
Add encoder specific pll mapping for DSI. The differences with the DDI
version are big enough to warrant a separate function.
v2: add posting read (Madhav)
Cc: Madhav Chauhan
Cc: Vandita Kulkarni
Reviewed-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 25 +
Hey Matt,
On Fri, Nov 30, 2018 at 5:22 PM Matt Roper wrote:
> I think Joonas is describing something closer in
> design to the cgroup-v2 "cpu" controller, which partitions the general
> time/usage allocated to via cgroup; afaiu, "cpu" doesn't really care
> which specific core the tasks run on, ju
Sean and Daniel,
Could you please help me with the review these changes?
--Ram
On 11/27/2018 7:32 PM, Ramalingam C wrote:
Couple of more HDCP1.4 fixes on
- Key load process for CFL
- Encryption status change time
- debug log addition
- active platform coverage
Ramalingam C (4):
On 30/11/2018 21:22, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-30 17:44:11)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h
b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 91a750e90dc4..8f985c35ec92 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/
On Fri, Nov 30, 2018 at 1:15 AM Guang Bai wrote:
>
> On Thu, 29 Nov 2018 10:17:49 +0200
> Jani Nikula wrote:
>
> > On Wed, 28 Nov 2018, Guang Bai wrote:
> > > On some GEN9 platforms, slowly unplugging (wiggling) the HDMI cable
> > > makes the kernel to believe the HDMI display is still connected
On 30/11/2018 21:58, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-11-30 17:44:12)
From: Tvrtko Ursulin
The new workaround list allocator grows the list in chunks so will end up
with some unused space. Trim it when the initialization phase is done to
free up a tiny bit of slab.
v2:
* Si
== Series Details ==
Series: drm/i915/icl: dsi enabling (rev7)
URL : https://patchwork.freedesktop.org/series/51011/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
96d02a19d096 drm/i915/icl: push pll to port mapping/unmapping to ddi encoder
hooks
a3c740ce09ea drm/i915/icl: Sani
== Series Details ==
Series: drm/i915/icl: dsi enabling (rev7)
URL : https://patchwork.freedesktop.org/series/51011/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooks
Okay!
Commit: drm
On 30.11.2018 15:48, Hans Verkuil wrote:
> On 11/30/18 15:29, Ville Syrjälä wrote:
>> On Fri, Nov 30, 2018 at 03:20:59PM +0100, Andrzej Hajda wrote:
>>> Hi Ville,
>>>
>>> As Christoph cannot respond till middle next week I can try to respond
>>> in his absence, as I am familiar with the subject.
>>
Currently we allocate a scratch page for each engine, but since we only
ever write into it for post-sync operations, it is not exposed to
userspace nor do we care for coherency. As we then do not care about its
contents, we can use one page for all, reducing our allocations and
avoid complications
Adding an extra MI_STORE_DWORD_IMM to the gpu relocation path for gen3
was good, but still not good enough. To survive 24+ hours under test we
needed to perform not one, not two but three extra store-dw. Doing so
for each GPU relocation was a little unsightly and since we need to
worry about usersp
Ensure that the sync registers are cleared every time we restart the
ring to avoid stale values from creeping in from random neutrinos.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ri
Impose a restraint that we have all vma pinned for a request prior to
its allocation. This is to simplify request construction, and should
facilitate unravelling the lock interdependencies later.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/huge_pages.c | 31 +++--
drivers/g
Currently we face a severe problem on Braswell that manifests as invalid
ppGTT accesses. The code tries to maintain the PDP (page directory
pointers) inside the context in two ways, direct write into the context
and a pipelined LRI update. The direct write into the context is
fundamentally racy as
Change the on-cpu check to on-runqueue to catch if the waiter has been
woken (and reset its current_state back to TASK_UNINTERRUPTIBLE to
perform the seqno check) but is sleeping due to being preempted off the
cpu.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_br
We inspect the requests under the assumption that they will be marked as
completed when they are removed from the queue. Currently however, in the
process of wedging the requests will be removed from the queue before they
are completed, so rearrange the code to complete the fences before the
locks
If all else fails and we are stuck eternally waiting for the undying
request, abandon all hope.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/intel_h
== Series Details ==
Series: drm/i915/icl: dsi enabling (rev7)
URL : https://patchwork.freedesktop.org/series/51011/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5239 -> Patchwork_10995
Summary
---
**SUCCESS**
No
From: Tvrtko Ursulin
We stopped re-applying the GT workarounds after engine reset since commit
59b449d5c82a ("drm/i915: Split out functions for different kinds of
workarounds").
Issue with this is that some of the GT workarounds live in the MMIO space
which gets lost during engine resets. So far
From: Tvrtko Ursulin
First two patches in this series fix losing of workarounds after engine reset
(https://bugzilla.freedesktop.org/show_bug.cgi?id=107945) which started
happening after 59b449d5c82a ("drm/i915: Split out functions for different kinds
of workarounds").
But since it was discovere
From: Tvrtko Ursulin
Instead of having a separate list of white-listed registers we can
trivially move this to the common workarounds framework.
This brings us one step closer to the goal of driving all workaround
classes using the same code.
v2:
* Use GEM_DEBUG_WARN_ON for the sanity check. (
From: Tvrtko Ursulin
Convert the per context workaround handling code to run against the newly
introduced common workaround framework and fuse the two to use the
existing smarter list add helper, the one which does the sorted insert and
merges registers where possible.
This completes migration o
From: Tvrtko Ursulin
Two simple selftests which test that both GT and engine workarounds are
not lost after either a full GPU reset, or after the per-engine ones.
(Including checks that one engine reset is not affecting workarounds not
belonging to itself.)
v2:
* Rebase for series refactoring.
From: Tvrtko Ursulin
Since we now have all the GT workarounds in a table, by adding a simple
shared helper function we can now verify that their values are still
applied after some interesting events in the lifetime of the driver.
Initially we only do this after GPU initialization.
v2:
Chris W
From: Tvrtko Ursulin
The new workaround list allocator grows the list in chunks so will end up
with some unused space. Trim it when the initialization phase is done to
free up a tiny bit of slab.
v2:
* Simplify with kmemdup. (Chris Wilson)
v3:
* Refactor for __size removal.
Signed-off-by: Tv
From: Tvrtko Ursulin
To enable later verification of GT workaround state at various stages of
driver lifetime, we record the list of applicable ones per platforms to a
list, from which they are also applied.
The added data structure is a simple array of register, mask and value
items, which is a
On 12/03/2018 12:23 PM, Andrzej Hajda wrote:
> On 30.11.2018 15:48, Hans Verkuil wrote:
>> On 11/30/18 15:29, Ville Syrjälä wrote:
>>> On Fri, Nov 30, 2018 at 03:20:59PM +0100, Andrzej Hajda wrote:
Hi Ville,
As Christoph cannot respond till middle next week I can try to respond
Quoting Tvrtko Ursulin (2018-12-03 11:46:11)
> From: Tvrtko Ursulin
>
> To enable later verification of GT workaround state at various stages of
> driver lifetime, we record the list of applicable ones per platforms to a
> list, from which they are also applied.
>
> The added data structure is a
Quoting Tvrtko Ursulin (2018-12-03 11:46:14)
> +static int
> +live_engine_reset_gt_engine_workarounds(void *arg)
> +{
...
> + ok = verify_gt_engine_wa(i915, "after idle reset");
> + if (!ok) {
> + ret = -ESRCH;
> + goto err;
>
On Thu, Nov 29, 2018 at 01:57:15PM +0200, Jani Nikula wrote:
> Unclutter the haswell_crtc_enable() and haswell_crtc_disable() functions
> a bit by moving the pll to port mapping and unmapping functions to the
> ddi encoder hooks. This allows removal of a bunch of boilerplate code
> from the functio
== Series Details ==
Series: series starting with [1/8] drm/i915/breadcrumbs: Reduce
missed-breadcrumb false positive rate
URL : https://patchwork.freedesktop.org/series/53396/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
766ea4f65bdf drm/i915/breadcrumbs: Reduce missed-bread
Quoting Tvrtko Ursulin (2018-12-03 11:46:16)
> From: Tvrtko Ursulin
>
> Convert the per context workaround handling code to run against the newly
> introduced common workaround framework and fuse the two to use the
> existing smarter list add helper, the one which does the sorted insert and
> mer
== Series Details ==
Series: series starting with [1/8] drm/i915/breadcrumbs: Reduce
missed-breadcrumb false positive rate
URL : https://patchwork.freedesktop.org/series/53396/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/breadcrumbs: Reduc
Quoting Tvrtko Ursulin (2018-12-03 11:46:17)
> From: Tvrtko Ursulin
>
> The new workaround list allocator grows the list in chunks so will end up
> with some unused space. Trim it when the initialization phase is done to
> free up a tiny bit of slab.
>
> v2:
> * Simplify with kmemdup. (Chris Wi
On Thu, 29 Nov 2018, José Roberto de Souza wrote:
> i915 yet don't support PSR in Apple panels, so lets keep it disabled
> while we work on that.
>
> v2: Renamed DP_DPCD_QUIRK_PSR_NOT_CURRENTLY_SUPPORTED to
> DP_DPCD_QUIRK_NO_PSR (Ville)
>
> Fixes: 598c6cfe0690 (drm/i915/psr: Enable PSR1 on gen-9+
On Fri, Nov 30, 2018 at 05:04:12PM -0800, Manasi Navare wrote:
> Fix the intel_link_compute_m_n in case of display stream
> compression. This patch passes the compressed_bpp to
> intel_link_compute_m_n if compression is enabled.
>
> Fixes: a4a15c80 ("drm/i915/dp: Compute DSC pipe config in ato
Chris Wilson writes:
> Ensure that the sync registers are cleared every time we restart the
> ring to avoid stale values from creeping in from random neutrinos.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
> 1 file changed, 7 insertions(+)
>
> dif
Chris Wilson writes:
> If all else fails and we are stuck eternally waiting for the undying
> request, abandon all hope.
>
> Signed-off-by: Chris Wilson
> ---
> drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 12 +---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a
Quoting Mika Kuoppala (2018-12-03 12:05:25)
> Chris Wilson writes:
>
> > Ensure that the sync registers are cleared every time we restart the
> > ring to avoid stale values from creeping in from random neutrinos.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/intel_ringbuf
== Series Details ==
Series: series starting with [1/8] drm/i915/breadcrumbs: Reduce
missed-breadcrumb false positive rate
URL : https://patchwork.freedesktop.org/series/53396/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5239 -> Patchwork_10996
=
Quoting Mika Kuoppala (2018-12-03 12:09:39)
> Chris Wilson writes:
>
> > If all else fails and we are stuck eternally waiting for the undying
> > request, abandon all hope.
> >
> > Signed-off-by: Chris Wilson
> > ---
> > drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 12 +---
> > 1
On Fri, Nov 30, 2018 at 02:58:01PM -0800, clinton.a.tay...@intel.com wrote:
> From: Clint Taylor
>
> In August 2018 the BSPEC changed the ICL port programming sequence to
> closely resemble earlier gen programming sequence.
>
> BSpec: 21257
> Cc: Ville Syrjälä
> Cc: Imre Deak
> Cc: Rodrigo Viv
== Series Details ==
Series: Restore workarounds after engine reset and unify their handling (rev3)
URL : https://patchwork.freedesktop.org/series/53313/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ed91418aaeec drm/i915: Record GT workarounds in a list
-:492: CHECK:PARENTHESI
Chris Wilson writes:
> Quoting Mika Kuoppala (2018-12-03 12:09:39)
>> Chris Wilson writes:
>>
>> > If all else fails and we are stuck eternally waiting for the undying
>> > request, abandon all hope.
>> >
>> > Signed-off-by: Chris Wilson
>> > ---
>> > drivers/gpu/drm/i915/selftests/intel_hang
== Series Details ==
Series: Restore workarounds after engine reset and unify their handling (rev3)
URL : https://patchwork.freedesktop.org/series/53313/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Record GT workarounds in a list
-drivers/
On 30/11/2018 19:27, Vivi, Rodrigo wrote:
> On Fri, Nov 30, 2018 at 03:04:40PM +0200, Martin Peres wrote:
>>
>>
>> On 29/11/2018 19:36, Rodrigo Vivi wrote:
>>> On Wed, Nov 28, 2018 at 11:52:49PM -0800, Saarinen, Jani wrote:
Hi,
> -Original Message-
> From: Intel-gfx [mail
On 03/12/2018 11:54, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-12-03 11:46:11)
From: Tvrtko Ursulin
To enable later verification of GT workaround state at various stages of
driver lifetime, we record the list of applicable ones per platforms to a
list, from which they are also applied.
Quoting Tvrtko Ursulin (2018-12-03 12:34:24)
>
> On 03/12/2018 11:54, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-12-03 11:46:11)
> >> From: Tvrtko Ursulin
> >> @@ -575,160 +587,240 @@ int intel_ctx_workarounds_emit(struct i915_request
> >> *rq)
> >> return 0;
> >> }
> >>
== Series Details ==
Series: Restore workarounds after engine reset and unify their handling (rev3)
URL : https://patchwork.freedesktop.org/series/53313/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5239 -> Patchwork_10997
On 03/12/2018 12:38, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-12-03 12:34:24)
On 03/12/2018 11:54, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-12-03 11:46:11)
From: Tvrtko Ursulin
@@ -575,160 +587,240 @@ int intel_ctx_workarounds_emit(struct i915_request *rq)
return 0
From: Tvrtko Ursulin
Two simple selftests which test that both GT and engine workarounds are
not lost after either a full GPU reset, or after the per-engine ones.
(Including checks that one engine reset is not affecting workarounds not
belonging to itself.)
v2:
* Rebase for series refactoring.
From: Tvrtko Ursulin
Instead of having a separate list of white-listed registers we can
trivially move this to the common workarounds framework.
This brings us one step closer to the goal of driving all workaround
classes using the same code.
v2:
* Use GEM_DEBUG_WARN_ON for the sanity check. (
From: Tvrtko Ursulin
First two patches in this series fix losing of workarounds after engine reset
(https://bugzilla.freedesktop.org/show_bug.cgi?id=107945) which started
happening after 59b449d5c82a ("drm/i915: Split out functions for different kinds
of workarounds").
But since it was discovere
From: Tvrtko Ursulin
The new workaround list allocator grows the list in chunks so will end up
with some unused space. Trim it when the initialization phase is done to
free up a tiny bit of slab.
v2:
* Simplify with kmemdup. (Chris Wilson)
v3:
* Refactor for __size removal.
Signed-off-by: Tv
From: Tvrtko Ursulin
Since we now have all the GT workarounds in a table, by adding a simple
shared helper function we can now verify that their values are still
applied after some interesting events in the lifetime of the driver.
Initially we only do this after GPU initialization.
v2:
Chris W
From: Tvrtko Ursulin
To enable later verification of GT workaround state at various stages of
driver lifetime, we record the list of applicable ones per platforms to a
list, from which they are also applied.
The added data structure is a simple array of register, mask and value
items, which is a
From: Tvrtko Ursulin
Convert the per context workaround handling code to run against the newly
introduced common workaround framework and fuse the two to use the
existing smarter list add helper, the one which does the sorted insert and
merges registers where possible.
This completes migration o
From: Tvrtko Ursulin
We stopped re-applying the GT workarounds after engine reset since commit
59b449d5c82a ("drm/i915: Split out functions for different kinds of
workarounds").
Issue with this is that some of the GT workarounds live in the MMIO space
which gets lost during engine resets. So far
On 03.12.2018 12:52, Hans Verkuil wrote:
> On 12/03/2018 12:23 PM, Andrzej Hajda wrote:
>> On 30.11.2018 15:48, Hans Verkuil wrote:
>>> On 11/30/18 15:29, Ville Syrjälä wrote:
On Fri, Nov 30, 2018 at 03:20:59PM +0100, Andrzej Hajda wrote:
> Hi Ville,
>
> As Christoph cannot respond
Quoting Tvrtko Ursulin (2018-12-03 12:50:14)
> From: Tvrtko Ursulin
>
> The new workaround list allocator grows the list in chunks so will end up
> with some unused space. Trim it when the initialization phase is done to
> free up a tiny bit of slab.
>
> v2:
> * Simplify with kmemdup. (Chris Wi
Quoting Tvrtko Ursulin (2018-12-03 12:50:08)
> From: Tvrtko Ursulin
>
> To enable later verification of GT workaround state at various stages of
> driver lifetime, we record the list of applicable ones per platforms to a
> list, from which they are also applied.
>
> The added data structure is a
== Series Details ==
Series: Restore workarounds after engine reset and unify their handling (rev4)
URL : https://patchwork.freedesktop.org/series/53313/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2c7ee2141088 drm/i915: Record GT workarounds in a list
-:135: WARNING:ALLOC_WI
== Series Details ==
Series: Restore workarounds after engine reset and unify their handling (rev4)
URL : https://patchwork.freedesktop.org/series/53313/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Record GT workarounds in a list
-drivers/
From: Tvrtko Ursulin
To enable later verification of GT workaround state at various stages of
driver lifetime, we record the list of applicable ones per platforms to a
list, from which they are also applied.
The added data structure is a simple array of register, mask and value
items, which is a
From: Tvrtko Ursulin
We stopped re-applying the GT workarounds after engine reset since commit
59b449d5c82a ("drm/i915: Split out functions for different kinds of
workarounds").
Issue with this is that some of the GT workarounds live in the MMIO space
which gets lost during engine resets. So far
From: Tvrtko Ursulin
Convert the per context workaround handling code to run against the newly
introduced common workaround framework and fuse the two to use the
existing smarter list add helper, the one which does the sorted insert and
merges registers where possible.
This completes migration o
== Series Details ==
Series: Restore workarounds after engine reset and unify their handling (rev4)
URL : https://patchwork.freedesktop.org/series/53313/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5240 -> Patchwork_10998
Chris Wilson writes:
> Since commit fd8526e50902 ("drm/i915/execlists: Trust the CSB") we
> actually broke the force-mmio mode for our execlists implementation. No
> one noticed, so ergo no one is actually using an old vGPU host (where we
> required the older method) and so can simply remove the
On 03/12/2018 11:36, Chris Wilson wrote:
Change the on-cpu check to on-runqueue to catch if the waiter has been
woken (and reset its current_state back to TASK_UNINTERRUPTIBLE to
perform the seqno check) but is sleeping due to being preempted off the
cpu.
Signed-off-by: Chris Wilson
Cc: Tvrtko
On Thu, 29 Nov 2018, Jani Nikula wrote:
> v11 of [1], incorporating DSI PLL work [2] from Vandita as well as PLL
> mapping and gating patches [3] from me and [4] from Imre.
>
> It made sense to squash some patches in [1] and [2] together, I've tried
> to set authorship and co-developed-by tags fai
== Series Details ==
Series: drm/i915/icl: dsi enabling (rev7)
URL : https://patchwork.freedesktop.org/series/51011/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5239_full -> Patchwork_10995_full
Summary
---
**WARNI
On Mon, 03 Dec 2018, Ville Syrjälä wrote:
> On Thu, Nov 29, 2018 at 01:57:15PM +0200, Jani Nikula wrote:
>> Unclutter the haswell_crtc_enable() and haswell_crtc_disable() functions
>> a bit by moving the pll to port mapping and unmapping functions to the
>> ddi encoder hooks. This allows removal o
On Thu, 29 Nov 2018, Jani Nikula wrote:
> On Tue, 27 Nov 2018, Imre Deak wrote:
>> The requirement for the DDI port clock gating for a port in DSI mode is
>> the opposite wrt. the case when the port is in DDI mode: the clock
>> should be gated when the port is active and ungated when the port is
On Tue, Nov 27, 2018 at 07:32:56PM +0530, Ramalingam C wrote:
> HDCP1.4 key load process varies between Intel platform to platform.
>
> For Gen9 platforms except BXT and GLK, HDCP1.4 key is loaded using
> the GT Driver Mailbox interface. Instead of listing all the platforms
> for this method, adop
On Tue, Nov 27, 2018 at 07:32:57PM +0530, Ramalingam C wrote:
> HDCP1.4 is enabled and validated only on GEN9+ platforms.
>
> Signed-off-by: Ramalingam C
Reviewed-by: Sean Paul
> ---
> drivers/gpu/drm/i915/intel_hdcp.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git
On Tue, Nov 27, 2018 at 07:32:58PM +0530, Ramalingam C wrote:
> Adding a debug log when the DP_AUX_NATIVE_REPLY_ACK is missing
> for aksv write. This helps to locate the possible non responding
> DP HDCP sinks.
>
> Signed-off-by: Ramalingam C
> ---
> drivers/gpu/drm/i915/intel_dp.c | 6 +-
>
On Tue, Nov 27, 2018 at 07:32:59PM +0530, Ramalingam C wrote:
> At enable/disable of the HDCP encryption, for encryption status change
> we need minimum one frame duration. And we might program this bit any
> point(start/End) in the previous frame.
>
> With 20mSec, observed the timeout for change
== Series Details ==
Series: Restore workarounds after engine reset and unify their handling (rev7)
URL : https://patchwork.freedesktop.org/series/53313/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0d8922bbcea9 drm/i915: Record GT workarounds in a list
5f4bdd949a82 drm/i915:
== Series Details ==
Series: Restore workarounds after engine reset and unify their handling (rev7)
URL : https://patchwork.freedesktop.org/series/53313/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Record GT workarounds in a list
-drivers/
== Series Details ==
Series: Restore workarounds after engine reset and unify their handling (rev7)
URL : https://patchwork.freedesktop.org/series/53313/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5243 -> Patchwork_10999
== Series Details ==
Series: series starting with [1/8] drm/i915/breadcrumbs: Reduce
missed-breadcrumb false positive rate
URL : https://patchwork.freedesktop.org/series/53396/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5239_full -> Patchwork_10996_full
===
Chris Wilson writes:
> Currently we allocate a scratch page for each engine, but since we only
> ever write into it for post-sync operations, it is not exposed to
> userspace nor do we care for coherency. As we then do not care about its
> contents, we can use one page for all, reducing our alloc
Quoting Mika Kuoppala (2018-12-03 13:40:26)
> Chris Wilson writes:
>
> > Since commit fd8526e50902 ("drm/i915/execlists: Trust the CSB") we
> > actually broke the force-mmio mode for our execlists implementation. No
> > one noticed, so ergo no one is actually using an old vGPU host (where we
> >
Chris Wilson writes:
> Quoting Mika Kuoppala (2018-12-03 13:40:26)
>> Chris Wilson writes:
>>
>> > Since commit fd8526e50902 ("drm/i915/execlists: Trust the CSB") we
>> > actually broke the force-mmio mode for our execlists implementation. No
>> > one noticed, so ergo no one is actually using a
Quoting Mika Kuoppala (2018-12-03 15:28:22)
> Chris Wilson writes:
>
> > Currently we allocate a scratch page for each engine, but since we only
> > ever write into it for post-sync operations, it is not exposed to
> > userspace nor do we care for coherency. As we then do not care about its
> > c
On 03/12/2018 11:36, Chris Wilson wrote:
We inspect the requests under the assumption that they will be marked as
completed when they are removed from the queue. Currently however, in the
process of wedging the requests will be removed from the queue before they
are completed, so rearrange the c
== Series Details ==
Series: Restore workarounds after engine reset and unify their handling (rev8)
URL : https://patchwork.freedesktop.org/series/53313/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e2c45229710e drm/i915: Record GT workarounds in a list
68a4800dce59 drm/i915:
== Series Details ==
Series: Restore workarounds after engine reset and unify their handling (rev8)
URL : https://patchwork.freedesktop.org/series/53313/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Record GT workarounds in a list
-drivers/
Currently we allocate a scratch page for each engine, but since we only
ever write into it for post-sync operations, it is not exposed to
userspace nor do we care for coherency. As we then do not care about its
contents, we can use one page for all, reducing our allocations and
avoid complications
Quoting Tvrtko Ursulin (2018-12-03 17:11:59)
>
> On 03/12/2018 11:36, Chris Wilson wrote:
> > We inspect the requests under the assumption that they will be marked as
> > completed when they are removed from the queue. Currently however, in the
> > process of wedging the requests will be removed f
== Series Details ==
Series: series starting with [1/8] drm/i915/breadcrumbs: Reduce
missed-breadcrumb false positive rate (rev2)
URL : https://patchwork.freedesktop.org/series/53396/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0c7799b14282 drm/i915: Complete the fences as t
== Series Details ==
Series: series starting with [1/8] drm/i915/breadcrumbs: Reduce
missed-breadcrumb false positive rate (rev2)
URL : https://patchwork.freedesktop.org/series/53396/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Complete t
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: Add HAS_DISPLAY() and use it
(rev2)
URL : https://patchwork.freedesktop.org/series/53341/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2ea25bb8bc83 drm/i915: Add HAS_DISPLAY() and use it
b7a8a1adc388 drm/i91
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: Add HAS_DISPLAY() and use it
(rev2)
URL : https://patchwork.freedesktop.org/series/53341/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Add HAS_DISPLAY() and use it
-drive
On Mon, Dec 03, 2018 at 06:46:01AM +, Ho, Kenny wrote:
> Hey Matt,
>
> On Fri, Nov 30, 2018 at 5:22 PM Matt Roper wrote:
> > I think Joonas is describing something closer in
> > design to the cgroup-v2 "cpu" controller, which partitions the general
> > time/usage allocated to via cgroup; afai
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