[Intel-gfx] [PATCH 2/2] drm/i915/selftests: Fix live_workarounds to actually do resets

From: Tvrtko Ursulin The test was missing some magic ingredients to actually trigger the resets. In case of the full reset we need the I915_RESET_HANDOFF flag set, and in case of engine reset we need a busy request. Thanks to Chris for helping with reset magic. Signed-off-by: Tvrtko Ursulin C

[Intel-gfx] [PATCH 1/2] drm/i915/selftests: Extract spinner code

From: Tvrtko Ursulin Pull out spinner code to a standalone file to enable it to be shortly used by other and new test cases. Plain code movement - no functional changes. Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/Makefile| 3 +- drivers/gpu/drm/i915/selftests/igt

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/selftests: Extract spinner code

== Series Details == Series: series starting with [1/2] drm/i915/selftests: Extract spinner code URL : https://patchwork.freedesktop.org/series/53298/ State : warning == Summary == $ dim checkpatch origin/drm-tip afa57c2cbca8 drm/i915/selftests: Extract spinner code -:28: WARNING:FILE_PATH_CHA

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/selftests: Extract spinner code

== Series Details == Series: series starting with [1/2] drm/i915/selftests: Extract spinner code URL : https://patchwork.freedesktop.org/series/53298/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/selftests: Extract spinner code +./include/ua

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Remove whitelist application from ringbuffer backend (rev3)

== Series Details == Series: drm/i915: Remove whitelist application from ringbuffer backend (rev3) URL : https://patchwork.freedesktop.org/series/53243/ State : success == Summary == CI Bug Log - changes from CI_DRM_5224_full -> Patchwork_10960_full

Re: [Intel-gfx] [PATCH 01/16] drm/i915: Properly set PCH as NOP when display is disabled

On Sat, Nov 03, 2018 at 11:41:10PM +0200, Jani Nikula wrote: > On Fri, 12 Oct 2018, José Roberto de Souza wrote: > > num_pipes is set to 0 if disable_display is set inside > > intel_device_info_runtime_init() but when that happen PCH will > > already be set in intel_detect_pch(). > > > > i915_driv

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/selftests: Extract spinner code

== Series Details == Series: series starting with [1/2] drm/i915/selftests: Extract spinner code URL : https://patchwork.freedesktop.org/series/53298/ State : success == Summary == CI Bug Log - changes from CI_DRM_5227 -> Patchwork_10974 Su

Re: [Intel-gfx] [PATCH 3/3] drm/i915: Implement half float formats and pixel normalize property

On Thu, Nov 29, 2018 at 05:52:28PM +, Strasser, Kevin wrote: > Daniel Vetter wrote: > > Do we have end-to-end userspace for this? > > I have patches for IGT and I'm planning on adding usage code to Weston. Apart > from that there is a Windows use case that Tina mentioned previously. I take > i

[Intel-gfx] [PATCH v2 2/2] drm/i915/selftests: Fix live_workarounds to actually do resets

From: Tvrtko Ursulin The test was missing some magic ingredients to actually trigger the resets. In case of the full reset we need the I915_RESET_HANDOFF flag set, and in case of engine reset we need a busy request. Thanks to Chris for helping with reset magic. v2: * Grab RPM ref over reset.

[Intel-gfx] [PATCH 3/6] drm/i915: Allocate a common scratch page

Currently we allocate a scratch page for each engine, but since we only ever write into it for post-sync operations, it is not exposed to userspace nor do we care for coherency. As we then do not care about its contents, we can use one page for all, reducing our allocations and avoid complications

[Intel-gfx] [PATCH 6/6] drm/i915: Pipeline PDP updates for Braswell

Currently we face a severe problem on Braswell that manifests as invalid ppGTT accesses. The code tries to maintain the PDP (page directory pointers) inside the context in two ways, direct write into the context and a pipelined LRI update. The direct write into the context is fundamentally racy as

[Intel-gfx] [PATCH 4/6] drm/i915/selftests: Terminate hangcheck sanitycheck forcibly

If all else fails and we are stuck eternally waiting for the undying request, abandon all hope. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/selftests/intel_h

Re: [Intel-gfx] [PATCH 1/2] drm/i915/selftests: Extract spinner code

Quoting Tvrtko Ursulin (2018-11-30 08:02:53) > From: Tvrtko Ursulin > > Pull out spinner code to a standalone file to enable it to be shortly used > by other and new test cases. > > Plain code movement - no functional changes. > > Signed-off-by: Tvrtko Ursulin Shiver me conflicts. Reviewed-by

[Intel-gfx] [PATCH 5/6] drm/i915/selftests: Reorder request allocation vs vma pinning

Impose a restraint that we have all vma pinned for a request prior to its allocation. This is to simplify request construction, and should facilitate unravelling the lock interdependencies later. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/selftests/huge_pages.c | 31 +++-- .../gpu/d

[Intel-gfx] [PATCH 2/6] drm/i915/ringbuffer: Clear semaphore sync registers on ring init

Ensure that the sync registers are cleared every time we restart the ring to avoid stale values from creeping in from random neutrinos. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ri

[Intel-gfx] [PATCH 1/6] drm/i915: Complete the fences as they are cancelled due to wedging

We inspect the requests under the assumption that they will be marked as completed when they are removed from the queue. Currently however, in the process of wedging the requests will be removed from the queue before they are completed, so rearrange the code to complete the fences before the locks

Re: [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Fix live_workarounds to actually do resets

Quoting Tvrtko Ursulin (2018-11-30 08:02:54) > From: Tvrtko Ursulin > > The test was missing some magic ingredients to actually trigger the > resets. > > In case of the full reset we need the I915_RESET_HANDOFF flag set, and in > case of engine reset we need a busy request. > > Thanks to Chris

Re: [Intel-gfx] [PATCH] drm/lease: Send a distinct uevent

On Thu, Nov 29, 2018 at 04:06:56PM -0800, Keith Packard wrote: > Daniel Vetter writes: > > > Cc: Keith Packard > > Reviewed-by: Keith Packard Thanks for review, pushed to drm-misc-fixes. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch __

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/2] drm/i915: s/PUNIT_REG_DSPFREQ/PUNIT_REG_DSPSSPM/

== Series Details == Series: series starting with [1/2] drm/i915: s/PUNIT_REG_DSPFREQ/PUNIT_REG_DSPSSPM/ URL : https://patchwork.freedesktop.org/series/53275/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5224_full -> Patchwork_10961_full =

Re: [Intel-gfx] [PATCH] drm/i915: Fixup stub definitions for intel_opregion_suspend|resume

Quoting Randy Dunlap (2018-11-29 22:16:08) > On 11/29/18 1:05 PM, Chris Wilson wrote: > > 248 "multiple definition of ...". E.g.: > > > > LD [M] drivers/gpu/drm/i915/i915.o > > ld: drivers/gpu/drm/i915/i915_irq.o: in function `intel_opregion_resume': > > i915_irq.c:(.text+0x58f0): multip

[Intel-gfx] [PATCH] drm/i915/vgpu: Disallow loading on old vGPU hosts

Since commit fd8526e50902 ("drm/i915/execlists: Trust the CSB") we actually broke the force-mmio mode for our execlists implementation. No one noticed, so ergo no one is actually using an old vGPU host (where we required the older method) and so can simply remove the broken support. Reported-by: M

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915/selftests: Extract spinner code (rev2)

== Series Details == Series: series starting with [1/2] drm/i915/selftests: Extract spinner code (rev2) URL : https://patchwork.freedesktop.org/series/53298/ State : warning == Summary == $ dim checkpatch origin/drm-tip bcfddfda17f5 drm/i915/selftests: Extract spinner code -:29: WARNING:FILE_

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/2] drm/i915/selftests: Extract spinner code (rev2)

== Series Details == Series: series starting with [1/2] drm/i915/selftests: Extract spinner code (rev2) URL : https://patchwork.freedesktop.org/series/53298/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915/selftests: Extract spinner code +./in

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/selftests: Extract spinner code (rev2)

== Series Details == Series: series starting with [1/2] drm/i915/selftests: Extract spinner code (rev2) URL : https://patchwork.freedesktop.org/series/53298/ State : success == Summary == CI Bug Log - changes from CI_DRM_5230 -> Patchwork_10975

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/6] drm/i915: Complete the fences as they are cancelled due to wedging

== Series Details == Series: series starting with [1/6] drm/i915: Complete the fences as they are cancelled due to wedging URL : https://patchwork.freedesktop.org/series/53308/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1826a0f0e99f drm/i915: Complete the fences as they are

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [1/6] drm/i915: Complete the fences as they are cancelled due to wedging

== Series Details == Series: series starting with [1/6] drm/i915: Complete the fences as they are cancelled due to wedging URL : https://patchwork.freedesktop.org/series/53308/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Complete the fenc

[Intel-gfx] [PATCH 2/8] drm/i915: Introduce per-engine workarounds

From: Tvrtko Ursulin We stopped re-applying the GT workarounds after engine reset since commit 59b449d5c82a ("drm/i915: Split out functions for different kinds of workarounds"). Issue with this is that some of the GT workarounds live in the MMIO space which gets lost during engine resets. So far

[Intel-gfx] [PATCH 0/8] Restore workarounds after engine reset and unify their handling

From: Tvrtko Ursulin First two patches in this series fix losing of workarounds after engine reset (https://bugzilla.freedesktop.org/show_bug.cgi?id=107945) which started happening after 59b449d5c82a ("drm/i915: Split out functions for different kinds of workarounds"). But since it was discovere

[Intel-gfx] [PATCH 4/8] drm/i915: Verify engine workaround state at runtime

From: Tvrtko Ursulin Analogue to the previous patch we add at runtime verification that after engine reset all respective workarounds have been correctly applied. Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_drv.c | 3 +++ drivers/gpu/drm/i915/intel_workarounds.c | 6 ++

[Intel-gfx] [PATCH 1/8] drm/i915: Record GT workarounds in a list

From: Tvrtko Ursulin To enable later verification of GT workaround state at various stages of driver lifetime, we record the list of applicable ones per platforms to a list, from which they are also applied. The added data structure is a simple array of register, mask and value items, which is a

[Intel-gfx] [PATCH 6/8] drm/i915: Move register white-listing to the common workaround framework

From: Tvrtko Ursulin Instead of having a separate list of white-listed registers we can trivially move this to the common workarounds framework. This brings us one step closer to the goal of driving all workaround classes using the same code. Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/

[Intel-gfx] [PATCH 8/8] drm/i915: Trim unused workaround list entries

From: Tvrtko Ursulin The new workaround list allocator grows the list in chunks so will end up with some unused space. Trim it when the initialization phase is done to free up a tiny bit of slab. Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/intel_workarounds.c | 13 + 1 f

[Intel-gfx] [PATCH 3/8] drm/i915: Verify GT workaround state at runtime

From: Tvrtko Ursulin Since we now have all the GT workarounds in a table, by adding a simple shared helper function we can now verify that their values are still applied after some interesting events in the lifetime of the driver. At this stage these are the driver initialization and engine rese

[Intel-gfx] [PATCH 7/8] drm/i915: Fuse per-context workaround handling with the common framework

From: Tvrtko Ursulin Convert the per context workaround handling code to run against the newly introduced common workaround framework and fuse the two to use the existing smarter list add helper, the one which does the sorted insert and merges registers where possible. This completes migration o

[Intel-gfx] [PATCH 5/8] drm/i915/selftests: Add tests for GT and engine workaround verification

From: Tvrtko Ursulin Two simple selftests which test that both GT and engine workarounds are not lost after either a full GPU reset, or after the per-engine ones. (Including checks that one engine reset is not affecting workarounds not belonging to itself.) Signed-off-by: Tvrtko Ursulin --- d

Re: [Intel-gfx] [PATCH 3/8] drm/i915: Verify GT workaround state at runtime

Quoting Tvrtko Ursulin (2018-11-30 11:31:56) > From: Tvrtko Ursulin > > Since we now have all the GT workarounds in a table, by adding a simple > shared helper function we can now verify that their values are still > applied after some interesting events in the lifetime of the driver. > > At thi

Re: [Intel-gfx] [PATCH 5/8] drm/i915/selftests: Add tests for GT and engine workaround verification

Quoting Tvrtko Ursulin (2018-11-30 11:31:58) > From: Tvrtko Ursulin > > Two simple selftests which test that both GT and engine workarounds are > not lost after either a full GPU reset, or after the per-engine ones. > > (Including checks that one engine reset is not affecting workarounds not > b

Re: [Intel-gfx] [PATCH 6/8] drm/i915: Move register white-listing to the common workaround framework

Quoting Tvrtko Ursulin (2018-11-30 11:31:59) > -static void whitelist_reg(struct whitelist *w, i915_reg_t reg) > +static void > +whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) > { > - if (GEM_DEBUG_WARN_ON(w->count >= RING_MAX_NONPRIV_SLOTS)) > - return; > - > -

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Fuse per-context workaround handling with the common framework

Quoting Tvrtko Ursulin (2018-11-30 11:32:00) > From: Tvrtko Ursulin > > Convert the per context workaround handling code to run against the newly > introduced common workaround framework and fuse the two to use the > existing smarter list add helper, the one which does the sorted insert and > mer

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/6] drm/i915: Complete the fences as they are cancelled due to wedging

== Series Details == Series: series starting with [1/6] drm/i915: Complete the fences as they are cancelled due to wedging URL : https://patchwork.freedesktop.org/series/53308/ State : success == Summary == CI Bug Log - changes from CI_DRM_5230 -> Patchwork_10976 =

Re: [Intel-gfx] [PATCH 8/8] drm/i915: Trim unused workaround list entries

Quoting Tvrtko Ursulin (2018-11-30 11:32:01) > From: Tvrtko Ursulin > > The new workaround list allocator grows the list in chunks so will end up > with some unused space. Trim it when the initialization phase is done to > free up a tiny bit of slab. > > Signed-off-by: Tvrtko Ursulin > --- > d

Re: [Intel-gfx] [PATCH 3/8] drm/i915: Verify GT workaround state at runtime

Quoting Tvrtko Ursulin (2018-11-30 11:31:56) > From: Tvrtko Ursulin > > Since we now have all the GT workarounds in a table, by adding a simple > shared helper function we can now verify that their values are still > applied after some interesting events in the lifetime of the driver. > > At thi

Re: [Intel-gfx] [PATCH] drm/i915/vgpu: Disallow loading on old vGPU hosts

Chris Wilson writes: > Since commit fd8526e50902 ("drm/i915/execlists: Trust the CSB") we > actually broke the force-mmio mode for our execlists implementation. No > one noticed, so ergo no one is actually using an old vGPU host (where we > required the older method) and so can simply remove the

Re: [Intel-gfx] [PATCH 3/8] drm/i915: Verify GT workaround state at runtime

On 30/11/2018 11:38, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-11-30 11:31:56) From: Tvrtko Ursulin Since we now have all the GT workarounds in a table, by adding a simple shared helper function we can now verify that their values are still applied after some interesting events in the

[Intel-gfx] ✗ Fi.CI.BAT: failure for Restore workarounds after engine reset and unify their handling

== Series Details == Series: Restore workarounds after engine reset and unify their handling URL : https://patchwork.freedesktop.org/series/53313/ State : failure == Summary == Applying: drm/i915: Record GT workarounds in a list Applying: drm/i915: Introduce per-engine workarounds Applying: dr

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/vgpu: Disallow loading on old vGPU hosts

== Series Details == Series: drm/i915/vgpu: Disallow loading on old vGPU hosts URL : https://patchwork.freedesktop.org/series/53311/ State : success == Summary == CI Bug Log - changes from CI_DRM_5230 -> Patchwork_10977 Summary --- *

Re: [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Fix live_workarounds to actually do resets

On 30/11/2018 09:53, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-11-30 08:02:54) From: Tvrtko Ursulin The test was missing some magic ingredients to actually trigger the resets. In case of the full reset we need the I915_RESET_HANDOFF flag set, and in case of engine reset we need a busy

[Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev3)

== Series Details == Series: series starting with [CI,v13,01/17] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state (rev3) URL : https://patchwork.freedesktop.org/series/53184/ State : failure == Summary == CI Bug Log - changes from CI_DRM_5224_full -> Patchwork_10963_full ===

Re: [Intel-gfx] [PATCH 2/2] drm/i915/selftests: Fix live_workarounds to actually do resets

Quoting Tvrtko Ursulin (2018-11-30 12:17:13) > > On 30/11/2018 09:53, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2018-11-30 08:02:54) > >> From: Tvrtko Ursulin > >> > >> The test was missing some magic ingredients to actually trigger the > >> resets. > >> > >> In case of the full reset we ne

[Intel-gfx] [PATCH v2] drm/i915/vgpu: Disallow loading on old vGPU hosts

Since commit fd8526e50902 ("drm/i915/execlists: Trust the CSB") we actually broke the force-mmio mode for our execlists implementation. No one noticed, so ergo no one is actually using an old vGPU host (where we required the older method) and so can simply remove the broken support. v2: csb_read c

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Get pipe id following atomic guidelines (rev2)

On 29/11/2018 19:36, Rodrigo Vivi wrote: > On Wed, Nov 28, 2018 at 11:52:49PM -0800, Saarinen, Jani wrote: >> Hi, >> >>> -Original Message- >>> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf >>> Of >>> Rodrigo Vivi >>> Sent: torstai 29. marraskuuta 2018 8.18

Re: [Intel-gfx] [v2, 1/8] drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to drm_plane

On Fri, Nov 30, 2018 at 02:08:11PM +0100, Christoph Manszewski wrote: > Hi, > > I am looking for a way to export the color encoding and range selection > to user space. I came across those properties and am wondering, why > they are meant only for non RGB color encodings. Would it be okay, to > mo

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/vgpu: Disallow loading on old vGPU hosts (rev2)

== Series Details == Series: drm/i915/vgpu: Disallow loading on old vGPU hosts (rev2) URL : https://patchwork.freedesktop.org/series/53311/ State : success == Summary == CI Bug Log - changes from CI_DRM_5230 -> Patchwork_10979 Summary -

Re: [Intel-gfx] [PATCH v11 01/23] drm/i915/icl: push pll to port mapping/unmapping to ddi encoder hooks

On 11/29/2018 7:42 PM, Jani Nikula wrote: Unclutter the haswell_crtc_enable() and haswell_crtc_disable() functions a bit by moving the pll to port mapping and unmapping functions to the ddi encoder hooks. This allows removal of a bunch of boilerplate code from the functions. Additionally, the IC

Re: [Intel-gfx] [PATCH v11 17/23] drm/i915/icl: add dummy DSI GPIO element execution function

On 11/29/2018 7:42 PM, Jani Nikula wrote: Add dummy debug logging GPIO element execution function for ICL. Looks fine to me. Reviewed-by: Madhav Chauhan Regards, Madhav Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_dsi_vbt.c | 10 +- 1 file changed, 9 insertions(+),

Re: [Intel-gfx] [PATCH v11 20/23] drm/i915/icl: add pll mapping for DSI

On 11/29/2018 7:42 PM, Jani Nikula wrote: Add encoder specific pll mapping for DSI. The differences with the DDI version are big enough to warrant a separate function. Cc: Madhav Chauhan Cc: Vandita Kulkarni Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/icl_dsi.c | 24

Re: [Intel-gfx] [PATCH v11 23/23] HACK: drm/i915/bios: ignore VBT not overflowing the mailbox

On 11/29/2018 7:42 PM, Jani Nikula wrote: Some machines seem to have a broken opregion where the VBT overflows the mailbox. Ignore this until properly fixed. Right, otherwise DSI modeset doesn't progress further. Acked-by: Madhav Chauhan Regards, Madhav Signed-off-by: Jani Nikula --- dr

Re: [Intel-gfx] [PATCH v10 00/15] drm/i915/icl: dsi enabling

On 11/2/2018 5:17 PM, Jani Nikula wrote: Next version of [1]. Sorry for the spam, needed to get the authorship straight. Fixed power domains and compute config hook initialization. Overall, with this series ICL DSI dual link video mode feature looks complete to me. Thanks!! Regards, Madhav

Re: [Intel-gfx] [PATCH v10 00/15] drm/i915/icl: dsi enabling

> -Original Message- > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of > Madhav Chauhan > Sent: Friday, November 30, 2018 7:43 PM > To: Nikula, Jani ; intel-gfx@lists.freedesktop.org > Subject: Re: [Intel-gfx] [PATCH v10 00/15] drm/i915/icl: dsi enabling > > O

Re: [Intel-gfx] [PATCH 0/3] Support 64 bpp half float formats

On Thu, Nov 29, 2018 at 09:39:52PM +, Strasser, Kevin wrote: > Ville Syrjälä wrote: > > On Wed, Nov 28, 2018 at 10:38:10PM -0800, Kevin Strasser wrote: > >> This series defines new formats and adds a plane property to be used for > >> floating point framebuffer content. Implementation is then a

Re: [Intel-gfx] [v2, 1/8] drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to drm_plane

Hi Ville, As Christoph cannot respond till middle next week I can try to respond in his absence, as I am familiar with the subject. On 30.11.2018 14:25, Ville Syrjälä wrote: > On Fri, Nov 30, 2018 at 02:08:11PM +0100, Christoph Manszewski wrote: >> Hi, >> >> I am looking for a way to export the c

Re: [Intel-gfx] [v2, 1/8] drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to drm_plane

On Fri, Nov 30, 2018 at 03:20:59PM +0100, Andrzej Hajda wrote: > Hi Ville, > > As Christoph cannot respond till middle next week I can try to respond > in his absence, as I am familiar with the subject. > > On 30.11.2018 14:25, Ville Syrjälä wrote: > > On Fri, Nov 30, 2018 at 02:08:11PM +0100, Ch

Re: [Intel-gfx] [PATCH 3/8] drm/i915: Verify GT workaround state at runtime

Quoting Tvrtko Ursulin (2018-11-30 12:02:56) > > On 30/11/2018 11:38, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2018-11-30 11:31:56) > >> From: Tvrtko Ursulin > >> > >> Since we now have all the GT workarounds in a table, by adding a simple > >> shared helper function we can now verify that

Re: [Intel-gfx] [v2, 1/8] drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to drm_plane

On 11/30/18 15:20, Andrzej Hajda wrote: > Hi Ville, > > As Christoph cannot respond till middle next week I can try to respond > in his absence, as I am familiar with the subject. > > On 30.11.2018 14:25, Ville Syrjälä wrote: >> On Fri, Nov 30, 2018 at 02:08:11PM +0100, Christoph Manszewski wrote

Re: [Intel-gfx] [v2, 1/8] drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to drm_plane

On 11/30/18 15:29, Ville Syrjälä wrote: > On Fri, Nov 30, 2018 at 03:20:59PM +0100, Andrzej Hajda wrote: >> Hi Ville, >> >> As Christoph cannot respond till middle next week I can try to respond >> in his absence, as I am familiar with the subject. >> >> On 30.11.2018 14:25, Ville Syrjälä wrote: >>

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/selftests: Extract spinner code (rev2)

On 30/11/2018 11:24, Patchwork wrote: == Series Details == Series: series starting with [1/2] drm/i915/selftests: Extract spinner code (rev2) URL : https://patchwork.freedesktop.org/series/53298/ State : success == Summary == CI Bug Log - changes from CI_DRM_5230 -> Patchwork_10975 ===

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/icl: Remove Wa_1604302699

On 29/11/2018 14:47, Patchwork wrote: == Series Details == Series: drm/i915/icl: Remove Wa_1604302699 URL : https://patchwork.freedesktop.org/series/53244/ State : success == Summary == CI Bug Log - changes from CI_DRM_5222 -> Patchwork_10955

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Remove whitelist application from ringbuffer backend (rev3)

On 29/11/2018 17:48, Patchwork wrote: == Series Details == Series: drm/i915: Remove whitelist application from ringbuffer backend (rev3) URL : https://patchwork.freedesktop.org/series/53243/ State : success == Summary == CI Bug Log - changes from CI_DRM_5224 -> Patchwork_10960 =

Re: [Intel-gfx] [PATCH 5/8] drm/i915/selftests: Add tests for GT and engine workaround verification

On 30/11/2018 11:43, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-11-30 11:31:58) From: Tvrtko Ursulin Two simple selftests which test that both GT and engine workarounds are not lost after either a full GPU reset, or after the per-engine ones. (Including checks that one engine reset is

Re: [Intel-gfx] [v2, 1/8] drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to drm_plane

On Fri, Nov 30, 2018 at 03:48:00PM +0100, Hans Verkuil wrote: > On 11/30/18 15:29, Ville Syrjälä wrote: > > On Fri, Nov 30, 2018 at 03:20:59PM +0100, Andrzej Hajda wrote: > >> Hi Ville, > >> > >> As Christoph cannot respond till middle next week I can try to respond > >> in his absence, as I am fam

Re: [Intel-gfx] [PATCH 7/8] drm/i915: Fuse per-context workaround handling with the common framework

On 30/11/2018 11:47, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-11-30 11:32:00) From: Tvrtko Ursulin Convert the per context workaround handling code to run against the newly introduced common workaround framework and fuse the two to use the existing smarter list add helper, the one whi

Re: [Intel-gfx] [PATCH 6/8] drm/i915: Move register white-listing to the common workaround framework

On 30/11/2018 11:45, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-11-30 11:31:59) -static void whitelist_reg(struct whitelist *w, i915_reg_t reg) +static void +whitelist_reg(struct i915_wa_list *wal, i915_reg_t reg) { - if (GEM_DEBUG_WARN_ON(w->count >= RING_MAX_NONPRIV_SLOTS)) -

Re: [Intel-gfx] [PATCH 8/8] drm/i915: Trim unused workaround list entries

On 30/11/2018 11:49, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-11-30 11:32:01) From: Tvrtko Ursulin The new workaround list allocator grows the list in chunks so will end up with some unused space. Trim it when the initialization phase is done to free up a tiny bit of slab. Signed-off

Re: [Intel-gfx] [PATCH 3/8] drm/i915: Verify GT workaround state at runtime

On 30/11/2018 11:54, Chris Wilson wrote: Quoting Tvrtko Ursulin (2018-11-30 11:31:56) From: Tvrtko Ursulin Since we now have all the GT workarounds in a table, by adding a simple shared helper function we can now verify that their values are still applied after some interesting events in the

Re: [Intel-gfx] [PATCH 5/8] drm/i915/selftests: Add tests for GT and engine workaround verification

Quoting Tvrtko Ursulin (2018-11-30 15:15:28) > > On 30/11/2018 11:43, Chris Wilson wrote: > > Quoting Tvrtko Ursulin (2018-11-30 11:31:58) > >> From: Tvrtko Ursulin > >> > >> Two simple selftests which test that both GT and engine workarounds are > >> not lost after either a full GPU reset, or af

Re: [Intel-gfx] [v3 1/3] drm/i915/icl: Add icl pipe degamma and gamma support

>-Original Message- >From: Roper, Matthew D >Sent: Friday, November 30, 2018 4:38 AM >To: Shankar, Uma >Cc: intel-gfx@lists.freedesktop.org; Lankhorst, Maarten >; Syrjala, Ville ; >Sharma, >Shashank >Subject: Re: [v3 1/3] drm/i915/icl: Add icl pipe degamma and gamma support > >On Thu,

Re: [Intel-gfx] [v2, 1/8] drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to drm_plane

On 11/30/18 16:16, Ville Syrjälä wrote: > On Fri, Nov 30, 2018 at 03:48:00PM +0100, Hans Verkuil wrote: >> On 11/30/18 15:29, Ville Syrjälä wrote: >>> On Fri, Nov 30, 2018 at 03:20:59PM +0100, Andrzej Hajda wrote: Hi Ville, As Christoph cannot respond till middle next week I can try

Re: [Intel-gfx] [PATCH] drm: Fix up drm_atomic_state_helper.[hc] extraction

On Thu, Nov 29, 2018 at 10:36:13AM -0500, Sean Paul wrote: > On Wed, Nov 28, 2018 at 5:07 AM Daniel Vetter wrote: > > > > I've misplaced two functions by accident: > > - drm_atomic_helper_duplicate_state is really part of the > > resume/suspend/shutdown device-wide helpers. > > - drm_atomic_help

Re: [Intel-gfx] [PATCH v2] drm/i915/gvt: Change KVMGT as self load module

On Fri, 30 Nov 2018 14:51:24 +0800 Zhenyu Wang wrote: > This trys to make 'kvmgt' module as self loadable instead of loading > by i915/gvt device model. So hypervisor specific module could be > stand-alone, e.g only after loading hypervisor specific module, GVT > feature could be enabled via spec

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/fbdev: Make skip_vt_switch the default (rev3)

== Series Details == Series: drm/fbdev: Make skip_vt_switch the default (rev3) URL : https://patchwork.freedesktop.org/series/53094/ State : warning == Summary == $ dim checkpatch origin/drm-tip 56cf8aa074f9 drm/fbdev: Make skip_vt_switch the default -:22: ERROR:GIT_COMMIT_ID: Please use git c

Re: [Intel-gfx] [v2, 1/8] drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to drm_plane

Hi, On Fri, Nov 30, 2018 at 04:34:54PM +0100, Hans Verkuil wrote: > On 11/30/18 16:16, Ville Syrjälä wrote: > > On Fri, Nov 30, 2018 at 03:48:00PM +0100, Hans Verkuil wrote: > >> On 11/30/18 15:29, Ville Syrjälä wrote: > >>> On Fri, Nov 30, 2018 at 03:20:59PM +0100, Andrzej Hajda wrote: > Hi

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Fixup stub definitions for intel_opregion_suspend|resume

== Series Details == Series: drm/i915: Fixup stub definitions for intel_opregion_suspend|resume URL : https://patchwork.freedesktop.org/series/53284/ State : success == Summary == CI Bug Log - changes from CI_DRM_5226_full -> Patchwork_10965_full ===

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/fbdev: Make skip_vt_switch the default (rev3)

== Series Details == Series: drm/fbdev: Make skip_vt_switch the default (rev3) URL : https://patchwork.freedesktop.org/series/53094/ State : success == Summary == CI Bug Log - changes from CI_DRM_5234 -> Patchwork_10980 Summary --- *

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT (rev4)

== Series Details == Series: drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT (rev4) URL : https://patchwork.freedesktop.org/series/49669/ State : success == Summary == CI Bug Log - changes from CI_DRM_5226_full -> Patchwork_10967_full

Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/ddi: Check for unexpectedly disabled transcoders

On Fri, Nov 30, 2018 at 07:31:01AM +, Patchwork wrote: > == Series Details == > > Series: drm/i915/ddi: Check for unexpectedly disabled transcoders > URL : https://patchwork.freedesktop.org/series/53256/ > State : failure > > == Summary == > > CI Bug Log - changes from CI_DRM_5224_full ->

Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/psr: Get pipe id following atomic guidelines (rev2)

On Fri, Nov 30, 2018 at 03:04:40PM +0200, Martin Peres wrote: > > > On 29/11/2018 19:36, Rodrigo Vivi wrote: > > On Wed, Nov 28, 2018 at 11:52:49PM -0800, Saarinen, Jani wrote: > >> Hi, > >> > >>> -Original Message- > >>> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] O

Re: [Intel-gfx] [v2, 1/8] drm: Add optional COLOR_ENCODING and COLOR_RANGE properties to drm_plane

Hi, I am looking for a way to export the color encoding and range selection to user space. I came across those properties and am wondering, why they are meant only for non RGB color encodings. Would it be okay, to modify them and use with RGB formats as well? Regards, Chris On 02/19/2018 09:28

[Intel-gfx] [PATCH v2 0/8] Restore workarounds after engine reset and unify their handling

From: Tvrtko Ursulin First two patches in this series fix losing of workarounds after engine reset (https://bugzilla.freedesktop.org/show_bug.cgi?id=107945) which started happening after 59b449d5c82a ("drm/i915: Split out functions for different kinds of workarounds"). But since it was discovere

[Intel-gfx] [PATCH 4/7] drm/i915/selftests: Add tests for GT and engine workaround verification

From: Tvrtko Ursulin Two simple selftests which test that both GT and engine workarounds are not lost after either a full GPU reset, or after the per-engine ones. (Including checks that one engine reset is not affecting workarounds not belonging to itself.) v2: * Rebase for series refactoring.

[Intel-gfx] [PATCH 7/7] drm/i915: Trim unused workaround list entries

From: Tvrtko Ursulin The new workaround list allocator grows the list in chunks so will end up with some unused space. Trim it when the initialization phase is done to free up a tiny bit of slab. v2: * Simplify with kmemdup. (Chris Wilson) Signed-off-by: Tvrtko Ursulin --- drivers/gpu/drm/i9

[Intel-gfx] [PATCH 5/7] drm/i915: Move register white-listing to the common workaround framework

From: Tvrtko Ursulin Instead of having a separate list of white-listed registers we can trivially move this to the common workarounds framework. This brings us one step closer to the goal of driving all workaround classes using the same code. v2: * Use GEM_DEBUG_WARN_ON for the sanity check. (

[Intel-gfx] [PATCH 6/7] drm/i915: Fuse per-context workaround handling with the common framework

From: Tvrtko Ursulin Convert the per context workaround handling code to run against the newly introduced common workaround framework and fuse the two to use the existing smarter list add helper, the one which does the sorted insert and merges registers where possible. This completes migration o

[Intel-gfx] [PATCH 1/7] drm/i915: Record GT workarounds in a list

From: Tvrtko Ursulin To enable later verification of GT workaround state at various stages of driver lifetime, we record the list of applicable ones per platforms to a list, from which they are also applied. The added data structure is a simple array of register, mask and value items, which is a

[Intel-gfx] [PATCH 2/7] drm/i915: Introduce per-engine workarounds

From: Tvrtko Ursulin We stopped re-applying the GT workarounds after engine reset since commit 59b449d5c82a ("drm/i915: Split out functions for different kinds of workarounds"). Issue with this is that some of the GT workarounds live in the MMIO space which gets lost during engine resets. So far

[Intel-gfx] [PATCH 3/7] drm/i915: Verify GT workaround state after GPU init

From: Tvrtko Ursulin Since we now have all the GT workarounds in a table, by adding a simple shared helper function we can now verify that their values are still applied after some interesting events in the lifetime of the driver. Initially we only do this after GPU initialization. v2: Chris W

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Restore workarounds after engine reset and unify their handling (rev2)

== Series Details == Series: Restore workarounds after engine reset and unify their handling (rev2) URL : https://patchwork.freedesktop.org/series/53313/ State : warning == Summary == $ dim checkpatch origin/drm-tip 1125245b3d4b drm/i915: Record GT workarounds in a list -:460: CHECK:PARENTHESI

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for Restore workarounds after engine reset and unify their handling (rev2)

== Series Details == Series: Restore workarounds after engine reset and unify their handling (rev2) URL : https://patchwork.freedesktop.org/series/53313/ State : warning == Summary == $ dim sparse origin/drm-tip Sparse version: v0.5.2 Commit: drm/i915: Record GT workarounds in a list -drivers/

Re: [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/psr: Get pipe id following atomic guidelines (rev5)

Pushed to drm-intel-next-queued, thanks for the review Rodrigo. On Thu, 2018-11-29 at 23:52 +, Patchwork wrote: > == Series Details == > > Series: drm/i915/psr: Get pipe id following atomic guidelines (rev5) > URL : https://patchwork.freedesktop.org/series/53132/ > State : success > > == S

[Intel-gfx] ✓ Fi.CI.BAT: success for Restore workarounds after engine reset and unify their handling (rev2)

== Series Details == Series: Restore workarounds after engine reset and unify their handling (rev2) URL : https://patchwork.freedesktop.org/series/53313/ State : success == Summary == CI Bug Log - changes from CI_DRM_5235 -> Patchwork_10981

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/psr: Get pipe id following atomic guidelines (rev5)

== Series Details == Series: drm/i915/psr: Get pipe id following atomic guidelines (rev5) URL : https://patchwork.freedesktop.org/series/53132/ State : success == Summary == CI Bug Log - changes from CI_DRM_5227_full -> Patchwork_10968_full

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