On Tue, 06 Nov 2018, Lucas De Marchi wrote:
> From: Rodrigo Vivi
>
> RANGE makes it longer, but clear. We are also going to add a check for
> the display part, so make rename to GT.
I also still have my doubts about this patch I'm afraid. I've expressed
the concern before, but here goes again.
On Wed, Nov 28, 2018 at 08:17:04AM +0100, Maarten Lankhorst wrote:
> Op 27-11-18 om 18:34 schreef Daniel Vetter:
> > KMS drivers really should all be able to restore their display state
> > on resume without fbcon helping out. So make this the default.
> >
> > Since I'm not entirely foolish, make i
On Tue, Nov 27, 2018 at 12:38:44PM -0800, Eric Anholt wrote:
> Daniel Vetter writes:
>
> > On Mon, Nov 26, 2018 at 04:36:21PM -0800, Eric Anholt wrote:
> >> Noralf Trønnes writes:
> >> > +static void drm_gem_shmem_vm_close(struct vm_area_struct *vma)
> >> > +{
> >> > +struct drm_gem_obje
== Series Details ==
Series: drm/i915/psr: Get pipe id following atomic guidelines
URL : https://patchwork.freedesktop.org/series/53132/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5213 -> Patchwork_10924 =
== Summary - WARNING ==
Minor unknown changes coming with Patc
On Tue, Nov 27, 2018 at 08:44:14PM -0500, Lyude Paul wrote:
> On Tue, 2018-11-27 at 20:44 +0100, Daniel Vetter wrote:
> > On Tue, Nov 27, 2018 at 12:48:59PM -0500, Lyude Paul wrote:
> > > On Mon, 2018-11-26 at 22:22 +0100, Daniel Vetter wrote:
> > > > On Mon, Nov 26, 2018 at 10:04:21PM +0100, Danie
On Tue, 27 Nov 2018, Manasi Navare wrote:
> From: Matt Atwood
>
> According to DP spec (2.9.3.1 of DP 1.4) if
> EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
> 02200h through 0220Fh shall contain the DPRX's true capability. These
> values will match 0h through Fh
Quoting Ho, Kenny (2018-11-27 17:41:17)
> On Tue, Nov 27, 2018 at 4:46 AM Joonas Lahtinen
> wrote:
> > I think a more abstract property "% of GPU (processing power)" might
> > be a more universal approach. One can then implement that through
> > subdividing the resources or timeslicing them, depe
Quoting Jani Nikula (2018-11-28 10:02:22)
> On Tue, 06 Nov 2018, Lucas De Marchi wrote:
> > From: Rodrigo Vivi
> >
> > RANGE makes it longer, but clear. We are also going to add a check for
> > the display part, so make rename to GT.
>
> I also still have my doubts about this patch I'm afraid. I
Hi Dave,
Here's the next pull request for v4.21. :)
drm-misc-next-2018-11-28:
drm-misc-next for v4.21:
Core Changes:
- Merge drm_info.c into drm_debugfs.c
- Complete the fake drm_crtc_commit's hw_done/flip_done sooner.
- Remove deprecated drm_obj_ref/unref functions. All drivers use get/put now.
== Series Details ==
Series: drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT (rev2)
URL : https://patchwork.freedesktop.org/series/49669/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5212_full -> Patchwork_10921_full =
== Summary - WARNING ==
Minor unknow
I've misplaced two functions by accident:
- drm_atomic_helper_duplicate_state is really part of the
resume/suspend/shutdown device-wide helpers.
- drm_atomic_helper_legacy_gamma_set is part of the legacy ioctl
compat helpers.
Move them both back.
Fixes: 9ef8a9dc4b21 ("drm: Extract drm_atomic_
== Series Details ==
Series: drm: Fix up drm_atomic_state_helper.[hc] extraction
URL : https://patchwork.freedesktop.org/series/53148/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9288282eb7cc drm: Fix up drm_atomic_state_helper.[hc] extraction
-:413: WARNING:NO_AUTHOR_SIGN_OF
== Series Details ==
Series: drm/i915/ringbuffer: Clear semaphore sync registers on ring init
URL : https://patchwork.freedesktop.org/series/53112/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5212_full -> Patchwork_10922_full =
== Summary - WARNING ==
Minor unknown cha
== Series Details ==
Series: drm: Fix up drm_atomic_state_helper.[hc] extraction
URL : https://patchwork.freedesktop.org/series/53148/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5213 -> Patchwork_10925 =
== Summary - SUCCESS ==
No regressions found.
External URL:
On Wed, Nov 07, 2018 at 04:05:52PM -0800, José Roberto de Souza wrote:
> When suspending or unloading the driver, it needs to release the
> TC ports so HW can change it state without wait for driver handshake.
According to
https://bugs.freedesktop.org/show_bug.cgi?id=108070#c26
this patch should
Hi Uma,
On Tue, Nov 27, 2018 at 10:10:42PM +0530, Uma Shankar wrote:
> This patch adds a DP colorspace property, enabling
> userspace to switch to various supported colorspaces.
> This will help enable BT2020 along with other colorspaces.
>
> v2: Addressed Maarten and Ville's review comments. Enh
== Series Details ==
Series: series starting with [CI,v12,01/23] drm/dsc: Modify DRM helper to
return complete DSC color depth capabilities
URL : https://patchwork.freedesktop.org/series/53113/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5212_full -> Patchwork_10923_full
ci/linux/commits/Manasi-Navare/drm-dsc-Modify-DRM-helper-to-return-complete-DSC-color-depth-capabilities/20181128-095026
base: git://anongit.freedesktop.org/drm-intel for-linux-next
:: branch date: 10 hours ago
:: commit date: 10 hours ago
>> drivers/gpu/drm/i915/intel_vdsc.c:404:22
Hi,
On Tue, Nov 27, 2018 at 10:10:40PM +0530, Uma Shankar wrote:
> This patch series creates a new connector property to program
> colorspace to sink devices. Modern sink devices support more
> than 1 type of colorspace like 601, 709, BT2020 etc. This helps
> to switch based on content type which
Ensure that the sync registers are cleared every time we restart the
ring to avoid stale values from creeping in from random neutrinos.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_ringbuffer.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ri
Currently we face a severe problem on Braswell that manifests as invalid
ppGTT accesses. The code tries to maintain the PDP (page directory
pointers) inside the context in two ways, direct write into the context
and a pipelined LRI update. The direct write into the context is
fundamentally racy as
Currently we allocate a scratch page for each engine, but since we only
ever write into it for post-sync operations, it is not exposed to
userspace nor do we care for coherency. As we then do not care about its
contents, we can use one page for all, reducing our allocations and
avoid complications
== Series Details ==
Series: series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync
registers on ring init
URL : https://patchwork.freedesktop.org/series/53154/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
300cb53c30ed drm/i915/ringbuffer: Clear semaphore sync r
== Series Details ==
Series: series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync
registers on ring init
URL : https://patchwork.freedesktop.org/series/53154/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/ringbuffer: Clear se
== Series Details ==
Series: series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync
registers on ring init
URL : https://patchwork.freedesktop.org/series/53154/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5213 -> Patchwork_10926
===
Chris Wilson writes:
> Currently we allocate a scratch page for each engine, but since we only
> ever write into it for post-sync operations, it is not exposed to
> userspace nor do we care for coherency. As we then do not care about its
> contents, we can use one page for all, reducing our alloc
Hi,
> -Original Message-
> From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf Of
> Patchwork
> Sent: keskiviikko 28. marraskuuta 2018 15.20
> To: Chris Wilson
> Cc: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] ✓ Fi.CI.BAT: success for series starting wit
Quoting Mika Kuoppala (2018-11-28 13:21:41)
> Chris Wilson writes:
> > diff --git a/drivers/gpu/drm/i915/intel_lrc.c
> > b/drivers/gpu/drm/i915/intel_lrc.c
> > index 08fd9b12e4d7..3464058cbfc7 100644
> > --- a/drivers/gpu/drm/i915/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/intel_lrc.c
> > @@ -128
Currently we face a severe problem on Braswell that manifests as invalid
ppGTT accesses. The code tries to maintain the PDP (page directory
pointers) inside the context in two ways, direct write into the context
and a pipelined LRI update. The direct write into the context is
fundamentally racy as
Currently kernel might allocate different connector ids
for the same outputs in case of DP MST, which seems to
confuse userspace. There are can be different connector
ids in the list, which could be assigned to the same
output, while being in different states.
This results in issues, like external
Mark A0 as the one and only pre-production variant of Kabylake and
remove its couple of workarounds, consigning them to the annals of
history.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.c | 1
It is time to prune kbl preproduction bits from the
driver. Add kbl revision A0 to preproduction hw list.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/i915_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index b
No need to carry kbl preproduction workarounds anymore,
so drop them.
Signed-off-by: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 12
drivers/gpu/drm/i915/intel_workarounds.c | 5 -
2 files changed, 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c
Currently kernel might allocate different connector ids
for the same outputs in case of DP MST, which seems to
confuse userspace. There are can be different connector
ids in the list, which could be assigned to the same
output, while being in different states.
This results in issues, like external
Chris Wilson writes:
> Mark A0 as the one and only pre-production variant of Kabylake and
> remove its couple of workarounds, consigning them to the annals of
> history.
>
> Signed-off-by: Chris Wilson
> Cc: Joonas Lahtinen
> Cc: Jani Nikula
> Cc: Rodrigo Vivi
> Cc: Mika Kuoppala
My two pat
>-Original Message-
>From: Brian Starkey [mailto:brian.star...@arm.com]
>Sent: Wednesday, November 28, 2018 5:12 PM
>To: Shankar, Uma
>Cc: intel-gfx@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>Lankhorst,
>Maarten ; Syrjala, Ville
>;
>Sharma, Shashank ; jo...@kwiboo.se;
>ha
== Series Details ==
Series: series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync
registers on ring init (rev2)
URL : https://patchwork.freedesktop.org/series/53154/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
82f42511a45b drm/i915/ringbuffer: Clear semaphore
== Series Details ==
Series: series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync
registers on ring init (rev2)
URL : https://patchwork.freedesktop.org/series/53154/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/ringbuffer: C
HDCP1.4 key load process varies between Intel platform to platform.
For Gen9 platforms except BXT and GLK, HDCP1.4 key is loaded using
the GT Driver Mailbox interface. So all GEN9_BC platforms will use
the GT Driver Mailbox interface for HDCP1.4 key load.
v2:
Using the IS_GEN9_BC for filtering
If all else fails and we are stuck eternally waiting for the undying
request, abandon all hope.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/intel_ha
== Series Details ==
Series: series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync
registers on ring init (rev2)
URL : https://patchwork.freedesktop.org/series/53154/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5213 -> Patchwork_10927
== Series Details ==
Series: Return only active connectors for GET_RESOURCES
URL : https://patchwork.freedesktop.org/series/53159/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
1b346bba5470 Return only active connectors for GET_RESOURCES
-:39: CHECK:PARENTHESIS_ALIGNMENT: Align
Quoting Patchwork (2018-11-28 14:18:05)
> == Series Details ==
>
> Series: series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync
> registers on ring init (rev2)
> URL : https://patchwork.freedesktop.org/series/53154/
> State : success
>
> == Summary ==
>
> CI Bug Log - changes
>-Original Message-
>From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
>Brian Starkey
>Sent: Wednesday, November 28, 2018 5:27 PM
>To: Shankar, Uma
>Cc: Syrjala, Ville ; jo...@kwiboo.se; intel-
>g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
>han
== Series Details ==
Series: Return only active connectors for GET_RESOURCES
URL : https://patchwork.freedesktop.org/series/53159/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5213 -> Patchwork_10928
Summary
---
**S
Quoting Stanislav Lisovskiy (2018-11-28 13:52:10)
> Currently kernel might allocate different connector ids
> for the same outputs in case of DP MST, which seems to
> confuse userspace. There are can be different connector
> ids in the list, which could be assigned to the same
> output, while being
On Wed, Nov 28, 2018 at 02:29:53PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: dri-devel [mailto:dri-devel-boun...@lists.freedesktop.org] On Behalf Of
> >Brian Starkey
> >Sent: Wednesday, November 28, 2018 5:27 PM
> >To: Shankar, Uma
> >Cc: Syrjala, Ville ; jo...@kwiboo
== Series Details ==
Series: drm/i915: Mark up early pre-production Kabylakes
URL : https://patchwork.freedesktop.org/series/53161/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5213 -> Patchwork_10929
Summary
---
**
Am Dienstag, 27. November 2018, 18:34:24 CET schrieb Daniel Vetter:
> KMS drivers really should all be able to restore their display state
> on resume without fbcon helping out. So make this the default.
>
> Since I'm not entirely foolish, make it only a default, which drivers
> can still override
== Series Details ==
Series: drm/i915/psr: Get pipe id following atomic guidelines
URL : https://patchwork.freedesktop.org/series/53132/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5213_full -> Patchwork_10924_full
Summar
== Series Details ==
Series: series starting with [1/2] drm/i915: Add kbl A0 to preproduction
detection list
URL : https://patchwork.freedesktop.org/series/53162/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5213 -> Patchwork_10930
===
== Series Details ==
Series: Return only active connectors for get_resources ioctl
URL : https://patchwork.freedesktop.org/series/53163/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9e2ef2ea4d7b Return only active connectors for get_resources ioctl
-:41: CHECK:PARENTHESIS_ALIG
On Wed, 2018-11-28 at 14:39 +, Chris Wilson wrote:
> Quoting Stanislav Lisovskiy (2018-11-28 13:52:10)
> > Currently kernel might allocate different connector ids
> > for the same outputs in case of DP MST, which seems to
> > confuse userspace. There are can be different connector
> > ids in th
== Series Details ==
Series: Return only active connectors for get_resources ioctl
URL : https://patchwork.freedesktop.org/series/53163/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5213 -> Patchwork_10931
Summary
---
== Series Details ==
Series: drm/i915/selftests: Terminate hangcheck sanitycheck forcibly
URL : https://patchwork.freedesktop.org/series/53165/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915
== Series Details ==
Series: HDCP1.4 fixes (rev9)
URL : https://patchwork.freedesktop.org/series/38978/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5213 -> Patchwork_10932
Summary
---
**SUCCESS**
No regressions
Regards
Shashank
On 11/27/2018 10:10 PM, Uma Shankar wrote:
This patch adds a HDMI colorspace property, enabling
userspace to switch to various supported colorspaces.
This will help enable BT2020 along with other colorspaces.
v2: Addressed Maarten and Ville's review comments. Enhanced
the col
Regards
Shashank
On 11/27/2018 10:10 PM, Uma Shankar wrote:
This patch adds a DP colorspace property, enabling
userspace to switch to various supported colorspaces.
This will help enable BT2020 along with other colorspaces.
v2: Addressed Maarten and Ville's review comments. Enhanced
the
On Tue, Nov 27, 2018 at 11:28:38PM -0800, José Roberto de Souza wrote:
> As stated in struct drm_encoder, crtc field should only be used
> by non-atomic drivers.
>
> So here caching the pipe id in intel_psr_enable() what is way more
> simple and efficient than at every call to
> intel_psr_flush()/
On Wed, Nov 28, 2018 at 03:58:19PM +0200, Mika Kuoppala wrote:
> Chris Wilson writes:
>
> > Mark A0 as the one and only pre-production variant of Kabylake and
> > remove its couple of workarounds, consigning them to the annals of
> > history.
> >
> > Signed-off-by: Chris Wilson
> > Cc: Joonas La
On Wed, Nov 28, 2018 at 10:02:22AM +0200, Jani Nikula wrote:
> On Tue, 06 Nov 2018, Lucas De Marchi wrote:
> > From: Rodrigo Vivi
> >
> > RANGE makes it longer, but clear. We are also going to add a check for
> > the display part, so make rename to GT.
>
> I also still have my doubts about this
Reviewed-by: Samuel Li
On 2018-11-28 3:20 a.m., Daniel Vetter wrote:
> On Wed, Nov 28, 2018 at 08:17:04AM +0100, Maarten Lankhorst wrote:
>> Op 27-11-18 om 18:34 schreef Daniel Vetter:
>>> KMS drivers really should all be able to restore their display state
>>> on resume without fbcon helping o
Ville Syrjala writes:
> From: Ville Syrjälä
>
> Move the CEA-861 QS bit handling entirely into the edid code. No
> need to bother the drivers with this.
>
> Cc: Alex Deucher
> Cc: "Christian König"
> Cc: "David (ChunMing) Zhou"
> Cc: amd-...@lists.freedesktop.org
> Cc: Eric Anholt (supporter
On Tue, Nov 27, 2018 at 04:19:23PM -0800, Rodrigo Vivi wrote:
> > Then on the question of IS_ prefix or not, I don't feel very strongly about
> > it. IS_ has a nice parallel with HAS_ and IS_platform, but I agree it
> > doesn't look the prettiest (IS_GT_GEN). So don't know, whatever the vote
> > en
On Wed, Nov 28, 2018 at 10:02:22AM +0200, Jani Nikula wrote:
> On Tue, 06 Nov 2018, Lucas De Marchi wrote:
> > From: Rodrigo Vivi
> >
> > RANGE makes it longer, but clear. We are also going to add a check for
> > the display part, so make rename to GT.
>
> I also still have my doubts about this
== Series Details ==
Series: drm: Fix up drm_atomic_state_helper.[hc] extraction
URL : https://patchwork.freedesktop.org/series/53148/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5213_full -> Patchwork_10925_full
Summary
Hi Dave,
Been a steady week, and no fixes apart from GVT, so quoting Zhenyu:
"One to correct MOCS registers load on engine list, one for rpm lock
warning fix, and another for use-after-free fix for partial ggtt
list destroy. "
Next week, Thursday is a national holiday in Finland, so I'll send
th
On Wed, 2018-11-28 at 08:55 -0800, Rodrigo Vivi wrote:
> On Tue, Nov 27, 2018 at 11:28:38PM -0800, José Roberto de Souza
> wrote:
> > As stated in struct drm_encoder, crtc field should only be used
> > by non-atomic drivers.
> >
> > So here caching the pipe id in intel_psr_enable() what is way mor
On Wed, Nov 28, 2018 at 10:21:05AM -0800, Souza, Jose wrote:
> On Wed, 2018-11-28 at 08:55 -0800, Rodrigo Vivi wrote:
> > On Tue, Nov 27, 2018 at 11:28:38PM -0800, José Roberto de Souza
> > wrote:
> > > As stated in struct drm_encoder, crtc field should only be used
> > > by non-atomic drivers.
> >
annot apply to v4.20-rc4]
> [if your patch is applied to the wrong git tree, please drop us a note to
> help improve the system]
>
> url:
> https://github.com/0day-ci/linux/commits/Manasi-Navare/drm-dsc-Modify-DRM-helper-to-return-complete-DSC-color-depth-capabilities/20181128-095
On Wed, 2018-11-28 at 09:17 +0100, Daniel Vetter wrote:
> On Tue, Nov 27, 2018 at 08:44:14PM -0500, Lyude Paul wrote:
> > On Tue, 2018-11-27 at 20:44 +0100, Daniel Vetter wrote:
> > > On Tue, Nov 27, 2018 at 12:48:59PM -0500, Lyude Paul wrote:
> > > > On Mon, 2018-11-26 at 22:22 +0100, Daniel Vette
== Series Details ==
Series: series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync
registers on ring init
URL : https://patchwork.freedesktop.org/series/53154/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5213_full -> Patchwork_10926_full
=
; [also build test WARNING on next-20181127]
> > [cannot apply to v4.20-rc4]
> > [if your patch is applied to the wrong git tree, please drop us a note to
> > help improve the system]
> >
> > url:
> > https://github.com/0day-ci/linux/commits/Manasi-Nava
On Mon, Nov 26, 2018 at 04:37:03PM -0800, José Roberto de Souza wrote:
> For PSR2 there is no register to tell HW to keep main link enabled
> while PSR2 is active, so don't configure sink DPCD with a
> misleading value.
>
> Cc: Dhinakaran Pandiyan
> Cc: Rodrigo Vivi
> Signed-off-by: José Roberto
On Wed, Nov 28, 2018 at 11:09:46AM +0200, Jani Nikula wrote:
> On Tue, 27 Nov 2018, Manasi Navare wrote:
> > From: Matt Atwood
> >
> > According to DP spec (2.9.3.1 of DP 1.4) if
> > EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
> > 02200h through 0220Fh shall contain th
== Series Details ==
Series: series starting with [1/3] drm/i915/ringbuffer: Clear semaphore sync
registers on ring init (rev2)
URL : https://patchwork.freedesktop.org/series/53154/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5213_full -> Patchwork_10927_full
==
On 27/11/2018 11:34, Daniele Ceraolo Spurio wrote:
On 26/11/2018 06:51, Michal Wajdeczko wrote:
On Wed, 17 Oct 2018 00:46:47 +0200, Daniele Ceraolo Spurio
wrote:
/snip/
diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
b/drivers/gpu/drm/i915/intel_guc_fwif.h
index 8382d591c784..1a853c
Hi Dave,
Happy meson week! A bunch of stellar fixes coming in this week from Lyude, and a
couple others plugging holes in meson and core.
drm-misc-fixes-2018-11-28:
- mst: Don't try to validate ports while destroying them (Lyude)
- core: Don't set device to master unless set_master succeeds (Ser
On Wed, 2018-11-28 at 11:02 -0800, Rodrigo Vivi wrote:
> On Mon, Nov 26, 2018 at 04:37:03PM -0800, José Roberto de Souza
> wrote:
> > For PSR2 there is no register to tell HW to keep main link enabled
> > while PSR2 is active, so don't configure sink DPCD with a
> > misleading value.
> >
> > Cc: D
On Wed, Nov 14, 2018 at 11:07:16PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Here's the remainder of the skl+ ddb/wm programming series. I tried to
> split up the ugly monster patch into a few chunks, and I tossed in
> a few extra nuggets on top. I also tried to improve the commit
> m
After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the
DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.
v3:
* Rename to intel_dp_write_pps_sdp (Ville)
* Use const intel_crtc_state (Ville)
v2:
* Rebase ond
If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.
v4:
Fix the unrealted stuff removed during rebase (Ville)
v3:
* Rebase
v2:
* Add warning f
Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.
v4:
* Remove redundant comment (Ville)
v3:
* Use cpu_tran
Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.
v3:
* Unused variables cleanup (Ville)
v2:
* Rebase on drm-tip (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
From: Anusha Srivatsa
For DP 1.4 and above, Display Stream compression can be
enabled only if Forward Error Correctin can be performed.
Add a crtc state for FEC. Currently, the state
is determined by platform, DP and DSC being
enabled. Moving forward we can use the state
to have error correction
From: Anusha Srivatsa
Set the suitable bits in DP_TP_CTL to stop
bit correction when DSC is disabled.
v2:
- rebased.
- Add additional check for compression state. (Gaurav)
v3: rebased.
v4:
- Move the code to the proper spot according to spec (Ville)
- Use proper checks (manasi)
v5: Remove unn
DSC params like the enable, compressed bpp, slice count and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the remaining
Basic DSC parameters and DSC configuration data needs to be computed
for each of the requested mode during atomic check. This is
required since for certain modes, valid DSC parameters and config
data might not be computed in which case compression cannot be
enabled for that mode.
For that reason we
From: Gaurav K Singh
This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.
v3 (From manasi):
* Pass bool state to enable/disable (Ville)
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of inte
From: Gaurav K Singh
This computation of RC params happens in the atomic commit phase
during compute_config() to validate if display stream compression
can be enabled for the requested mode.
v7 (From Manasi):
* Use DRM_DEBUG instead of DRM_ERROR (Ville)
* Use Error numberinstead of -1 (Ville)
v6
On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.
v3:
* Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville)
* Move it around TRANSCODER power domain defs (Ville)
v2:
* Fix the power well mismatch CI er
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v4:
* Remove encoder, make crtc_state const (Ville)
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc para
A separate power well 2 (PG2) is required for VDSC on eDP transcoder
whereas all other transcoders use the power wells associated with the
transcoders for VDSC.
This patch adds a helper to obtain correct power domain depending on
transcoder being used and enables/disables the power wells during
VDS
From: Gaurav K Singh
This patches does the following:
1. This patch defines all the DSC parameters as per the VESA
DSC specification. These are stored in the encoder and used
to compute the PPS parameters to be sent to the Sink.
2. Compute all the DSC parameters which are derived from DSC
state
From: Anusha Srivatsa
If FEC is supported, the corresponding
DP_TP_CTL register bits have to be configured.
The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register
and wait till FEC_STATUS in DP_TP_CTL[28] is 1.
Also add the warn message to make sure that the control
register is alrea
From: Anusha Srivatsa
If the panel supports FEC, the driver has to
set the FEC_READY bit in the dpcd register:
FEC_CONFIGURATION.
This has to happen before link training.
v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
- change commit message. (Gaurav)
v3: rebased. (r-b Manasi)
v4
== Series Details ==
Series: Return only active connectors for GET_RESOURCES
URL : https://patchwork.freedesktop.org/series/53159/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5213_full -> Patchwork_10928_full
Summary
If all else fails and we are stuck eternally waiting for the undying
request, abandon all hope.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/selftests/intel_hangcheck.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/selftests/intel_h
Currently we allocate a scratch page for each engine, but since we only
ever write into it for post-sync operations, it is not exposed to
userspace nor do we care for coherency. As we then do not care about its
contents, we can use one page for all, reducing our allocations and
avoid complications
1 - 100 of 162 matches
Mail list logo
