From: Anusha Srivatsa
Set the suitable bits in DP_TP_CTL to stop
bit correction when DSC is disabled.
v2:
- rebased.
- Add additional check for compression state. (Gaurav)
v3: rebased.
v4:
- Move the code to the proper spot according to spec (Ville)
- Use proper checks (manasi)
v5: Remove unn
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v4:
* Remove encoder, make crtc_state const (Ville)
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc para
From: Anusha Srivatsa
If the panel supports FEC, the driver has to
set the FEC_READY bit in the dpcd register:
FEC_CONFIGURATION.
This has to happen before link training.
v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
- change commit message. (Gaurav)
v3: rebased. (r-b Manasi)
v4
After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the
On Tue, Nov 20, 2018 at 11:39:26AM +0100, Maarten Lankhorst wrote:
> On lynxpoint the bios sometimes sets up the backlight using the CPU
> display, but the driver expects using the PWM PCH override register.
>
> Read the value from the CPU register, then convert it to the other
> units by converti
== Series Details ==
Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)
URL : https://patchwork.freedesktop.org/series/51878/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5174 -> Patchwork_10868 =
== Summary - SUCCESS ==
No regressions found.
Externa
== Series Details ==
Series: Respin of remaining DSC + FEC patches
URL : https://patchwork.freedesktop.org/series/52781/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
72d53683f5ab drm/dsc: Modify DRM helper to return complete DSC color depth
capabilities
a82354d4ddcd drm/dsc:
== Series Details ==
Series: Respin of remaining DSC + FEC patches
URL : https://patchwork.freedesktop.org/series/52781/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/dsc: Modify DRM helper to return complete DSC color depth
capabilities
Okay!
C
== Series Details ==
Series: Respin of remaining DSC + FEC patches
URL : https://patchwork.freedesktop.org/series/52781/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5174 -> Patchwork_10869 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchw
Hello,
On Tue, Nov 20, 2018 at 01:58:11PM -0500, Kenny Ho wrote:
> Since many parts of the DRM subsystem has vendor-specific
> implementations, we introduce mechanisms for vendor to register their
> specific resources and control files to the DRM cgroup subsystem. A
> vendor will register itself
Always show the FEC capability as it is initialised to 0 before error.
Fixing,
drivers/gpu/drm/i915/intel_dp.c:3846 intel_dp_get_dsc_sink_cap() warn:
inconsistent indenting
Fixes: 08cadae8e157 ("i915/dp/fec: Cache the FEC_CAPABLE DPCD register")
Signed-off-by: Chris Wilson
Cc: Jani Nikula
Cc:
Found by smatch:
drivers/gpu/drm/i915/gvt/gtt.c:2452 intel_vgpu_destroy_ggtt_mm() error:
dereferencing freed memory 'pos'
Signed-off-by: Chris Wilson
Cc: Zhenyu Wang
---
drivers/gpu/drm/i915/gvt/gtt.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i
== Series Details ==
Series: series starting with [1/2] drm/i915/gvt: Avoid use-after-free iterating
the gtt list
URL : https://patchwork.freedesktop.org/series/52786/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5174 -> Patchwork_10870 =
== Summary - SUCCESS ==
No reg
== Series Details ==
Series: series starting with [1/2] drm/i915: Force a LUT update in
intel_initial_commit()
URL : https://patchwork.freedesktop.org/series/52754/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5172_full -> Patchwork_10861_full =
== Summary - WARNING ==
Kenny Ho writes:
> Account for the total size of buffer object requested to amdgpu by
> buffer type on a per cgroup basis.
>
> x prefix in the control file name x.bo_requested.amd.stat signify
> experimental.
Why is a counting of the size of buffer objects ever allocated useful,
as opposed to th
Kenny Ho writes:
> Account for the number of command submitted to amdgpu by type on a per
> cgroup basis, for the purpose of profiling/monitoring applications.
For profiling other drivers, I've used perf tracepoints, which let you
get useful timelines of multiple events in the driver. Have you
On Mon, 2018-11-19 at 17:05 -0800, Rodrigo Vivi wrote:
> On Mon, Nov 19, 2018 at 03:01:01PM -0800, José Roberto de Souza
> wrote:
> > When there is no output no one will hold a runtime_pm reference
> > causing a warning when trying to read emom_status in debugfs.
> >
> > [22.756480] [
On Tue, Nov 20, 2018 at 03:54:50PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> If we need to force a full plane update before userspace/fbdev
> have given us a proper plane state we should try to maintain the
> current plane state as much as possible (apart from the parts
> of the state
On Tue, Nov 20, 2018 at 03:54:49PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> If we force a plane update to fix up our half populated plane state
> we'll also force on the pipe gamma for the plane (since we always
> enable pipe gamma currently). If the BIOS hasn't programmed a sensible
On Tue, Nov 20, 2018 at 02:40:49PM +0100, Maarten Lankhorst wrote:
> Now that we've solved the backlight issue, I think it's time to enable
> this again by default. We've enabled it in the past, but backlight
> issues prevented us from enabling it by default.
>
> Our hardware readout is pretty com
Hello,
On Tue, Nov 20, 2018 at 10:21:14PM +, Ho, Kenny wrote:
> By this reply, are you suggesting that vendor specific resources
> will never be acceptable to be managed under cgroup? Let say a user
I wouldn't say never but whatever which gets included as a cgroup
controller should have clea
If no PCH was detected in intel_detect_pch() don't touch the
handshake registers.
Cc: Lucas De Marchi
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
This helps separate what capabilities are display capabilities.
Cc: Jani Nikula
Cc: Lucas De Marchi
Suggested-by: Jani Nikula
Suggested-by: Lucas De Marchi
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.h | 22 ++---
drivers/gpu/drm/i915/i915_pci.c
Right now it is decided if GEN has display by checking the num_pipes,
so lets make it explicit and use a macro.
Cc: Lucas De Marchi
Cc: Jani Nikula
Signed-off-by: José Roberto de Souza
---
drivers/gpu/drm/i915/i915_drv.c | 10 +-
drivers/gpu/drm/i915/i915_drv.h | 2 +
On Fri, Nov 09, 2018 at 12:20:11PM -0800, José Roberto de Souza wrote:
> When a PSR error happens sink sets the PSR errors register and also
> set the link to a error status.
> So in the short pulse handling it was returning earlier and doing a
> full detection and attempting to retrain but it fail
On Fri, Nov 09, 2018 at 12:20:12PM -0800, José Roberto de Souza wrote:
> When we detect a error and disable PSR, it is kept disable until the
> next modeset but as the sink already show signs that it do not
> properly work with PSR lets disabled it for good to avoid any
> additional flickering.
>
On Wed, Nov 14, 2018 at 11:07:24PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Make a cleaner split between the skl+ and icl+ ways of computing
> watermarks. This way skl_build_pipe_wm() doesn't have to know any
> of the gritty details of icl+ master/slave planes.
>
> We can also simpl
On Wed, Nov 14, 2018 at 11:07:25PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Simplify the calling convention of the skl+ watermark functions
> by not passing around dev_priv needlessly. The callees have
> what they need to dig it out anyway.
>
> Signed-off-by: Ville Syrjälä
Reviewe
On Fri, Nov 09, 2018 at 12:20:13PM -0800, José Roberto de Souza wrote:
> While PSR is active hardware will do aux transactions by it self to
> wakeup sink to receive a new frame when necessary. If that
> transaction is not acked by sink, hardware will trigger this
> interruption.
>
> So let's disa
On Fri, Nov 09, 2018 at 12:20:14PM -0800, José Roberto de Souza wrote:
> If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
> will still keep the error set even after the reset done in the
> irq_preinstall and irq_uninstall hooks.
> And enabling in this situation cause the screen t
On Fri, Nov 09, 2018 at 12:20:15PM -0800, José Roberto de Souza wrote:
> We should not access hardware while computing config also we don't
> support stereo 3D so this tests was never true.
yeap... it was there becase at some point we were planing to enabled that S3D
and if that happen we would ea
== Series Details ==
Series: series starting with [1/3] drm/i915: Add HAS_DISPLAY() and use it
URL : https://patchwork.freedesktop.org/series/52790/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7a61c38bd7ad drm/i915: Add HAS_DISPLAY() and use it
3259afbd74f1 drm/i915: Do not t
== Series Details ==
Series: series starting with [1/3] drm/i915: Add HAS_DISPLAY() and use it
URL : https://patchwork.freedesktop.org/series/52790/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Add HAS_DISPLAY() and use it
-drivers/gpu/drm/
On Tue, 2018-11-20 at 14:47 -0800, Rodrigo Vivi wrote:
> On Fri, Nov 09, 2018 at 12:20:13PM -0800, José Roberto de Souza
> wrote:
> > While PSR is active hardware will do aux transactions by it self to
> > wakeup sink to receive a new frame when necessary. If that
> > transaction is not acked by si
== Series Details ==
Series: series starting with [1/3] drm/i915: Add HAS_DISPLAY() and use it
URL : https://patchwork.freedesktop.org/series/52790/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5175 -> Patchwork_10871 =
== Summary - SUCCESS ==
No regressions found.
E
== Series Details ==
Series: Add Colorspace connector property interface (rev3)
URL : https://patchwork.freedesktop.org/series/47132/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5174_full -> Patchwork_10862_full =
== Summary - WARNING ==
Minor unknown changes coming wi
While trying to add a chamelium test for short HPD IRQs, I ran into
issues where a hotplug storm would be triggered, but the point at which
it would be reported by the kernel would be after igt actually finished
checking i915_hpd_storm_ctl's status. So, fix this by simply
synchronizing our IRQ work
On Wed, Nov 14, 2018 at 11:07:26PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> On SKL+ the plane WM/BUF_CFG registers are a proper part of each
> plane's register set. That means accessing them will cancel any
> pending plane update, and we would need a PLANE_SURF register write
> to ar
== Series Details ==
Series: series starting with [1/2] drm/i915: Enable fastset for non-boot
modesets.
URL : https://patchwork.freedesktop.org/series/52758/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5174_full -> Patchwork_10863_full =
== Summary - FAILURE ==
Seriou
== Series Details ==
Series: drm/i915: Synchronize hpd work in i915_hpd_storm_ctl_show()
URL : https://patchwork.freedesktop.org/series/52796/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5175 -> Patchwork_10872 =
== Summary - SUCCESS ==
No regressions found.
Externa
Account for the total size of buffer object requested to amdgpu by
buffer type on a per cgroup basis.
x prefix in the control file name x.bo_requested.amd.stat signify
experimental.
Change-Id: Ifb680c4bcf3652879a7a659510e25680c2465cf6
Signed-off-by: Kenny Ho
---
drivers/gpu/drm/amd/amdgpu/amdgp
The purpose of this patch series is to start a discussion for a generic cgroup
controller for the drm subsystem. The design proposed here is a very early one.
We are hoping to engage the community as we develop the idea.
Backgrounds
==
Control Groups/cgroup provide a mechanism for aggreg
Fix a spelling mistake in a comment.
Signed-off-by: Alexandre Belloni
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index f9ce35da4123..742f8ff101e4 100644
---
Since many parts of the DRM subsystem has vendor-specific
implementations, we introduce mechanisms for vendor to register their
specific resources and control files to the DRM cgroup subsystem. A
vendor will register itself with the DRM cgroup subsystem first before
registering individual DRM devi
Change-Id: I6830d3990f63f0c13abeba29b1d330cf28882831
Signed-off-by: Kenny Ho
---
include/linux/cgroup_drm.h| 32
include/linux/cgroup_subsys.h | 4 +++
init/Kconfig | 5
kernel/cgroup/Makefile| 1 +
kernel/cgroup/drm.c | 46 +
Account for the number of command submitted to amdgpu by type on a per
cgroup basis, for the purpose of profiling/monitoring applications.
x prefix in the control file name x.cmd_submitted.amd.stat signify
experimental.
Change-Id: Ibc22e5bda600f54fe820fe0af5400ca348691550
Signed-off-by: Kenny Ho
Change-Id: Ib66c44ac1b1c367659e362a2fc05b6fbb3805876
Signed-off-by: Kenny Ho
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7
drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c | 37 +
drivers/gpu/drm/amd/amdgpu/amdgpu_dr
Hi Tejun,
Thanks for the reply. A few clarifying questions:
On Tue, Nov 20, 2018 at 3:21 PM Tejun Heo wrote:
> So, I'm still pretty negative about adding drm controller at this
> point. There isn't enough of common resource model defined yet and
> until that gets sorted out I think it's in the
== Series Details ==
Series: DRM cgroup controller
URL : https://patchwork.freedesktop.org/series/52799/
State : failure
== Summary ==
CALLscripts/checksyscalls.sh
DESCEND objtool
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_device.o
In file included
== Series Details ==
Series: drm/i915: fix spelling mistake "reserverd" -> "reserved"
URL : https://patchwork.freedesktop.org/series/52800/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5175 -> Patchwork_10873 =
== Summary - SUCCESS ==
No regressions found.
External U
On 2018.11.20 20:24:38 +, Chris Wilson wrote:
> Found by smatch:
>
> drivers/gpu/drm/i915/gvt/gtt.c:2452 intel_vgpu_destroy_ggtt_mm() error:
> dereferencing freed memory 'pos'
>
> Signed-off-by: Chris Wilson
> Cc: Zhenyu Wang
> ---
> drivers/gpu/drm/i915/gvt/gtt.c | 7 ---
> 1 file ch
Sorry I missed it. Thanks for the correction!
Regards,
Henry
> -Original Message-
> From: Zhenyu Wang [mailto:zhen...@linux.intel.com]
> Sent: Wednesday, November 21, 2018 10:29 AM
> To: Chris Wilson
> Cc: intel-gfx@lists.freedesktop.org; Zhenyu Wang
> ; Yuan, Hang
> Subject: Re: [PATCH
== Series Details ==
Series: series starting with [1/4] drm/edid: Add CTA-861-G modes with VIC < 128
URL : https://patchwork.freedesktop.org/series/52770/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5174_full -> Patchwork_10865_full =
== Summary - WARNING ==
Minor unkn
== Series Details ==
Series: drm/i915/selftests: Log test and subtest names for easier debugging
URL : https://patchwork.freedesktop.org/series/52774/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5174_full -> Patchwork_10866_full =
== Summary - WARNING ==
Minor unknown
== Series Details ==
Series: drm/atomic: Fix the early return in drm_atomic_set_mode_for_crtc()
URL : https://patchwork.freedesktop.org/series/52777/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5174_full -> Patchwork_10867_full =
== Summary - WARNING ==
Minor unknown c
== Series Details ==
Series: drm/i915: Program SKL+ watermarks/ddb more carefully (rev8)
URL : https://patchwork.freedesktop.org/series/51878/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5174_full -> Patchwork_10868_full =
== Summary - FAILURE ==
Serious unknown change
== Series Details ==
Series: Respin of remaining DSC + FEC patches
URL : https://patchwork.freedesktop.org/series/52781/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5174_full -> Patchwork_10869_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_
Driver obtain power well at intel_csr_ucode_init().
And release it after load DMC firmware successful.
An issue happened when DMC was not found or failed
to load. Power well would not be released and just
output some error messages. Driver have to release
power well properly to keep put/get balanc
== Series Details ==
Series: series starting with [1/2] drm/i915/gvt: Avoid use-after-free iterating
the gtt list
URL : https://patchwork.freedesktop.org/series/52786/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5174_full -> Patchwork_10870_full =
== Summary - SUCCESS ==
On Tue, 20 Nov 2018, "Lee, Shawn C" wrote:
> Driver obtain power well at intel_csr_ucode_init().
> And release it after load DMC firmware successful.
Correct.
> An issue happened when DMC was not found or failed
> to load. Power well would not be released and just
> output some error messages. D
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