Quoting Tomasz Lis (2018-10-31 14:24:13)
> From: Oscar Mateo
>
> SFC (Scaler & Format Converter) units are shared between VD and VEBoxes.
> They also happen to have separate reset bits. So, whenever we want to reset
> one or more of the media engines, we have to make sure the SFCs do not
> change
Quoting Chris Wilson (2018-10-31 14:25:40)
> Quoting Tomasz Lis (2018-10-31 14:24:13)
> > From: Oscar Mateo
> >
> > SFC (Scaler & Format Converter) units are shared between VD and VEBoxes.
> > They also happen to have separate reset bits. So, whenever we want to reset
> > one or more of the media
== Series Details ==
Series: mm, drm/i915: Mark pinned shmemfs pages as unevictable (rev2)
URL : https://patchwork.freedesktop.org/series/25337/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5061_full -> Patchwork_10658_full =
== Summary - WARNING ==
Minor unknown change
== Series Details ==
Series: RFT drm/i915/execlists: Flush memory before signaling ELSQ
URL : https://patchwork.freedesktop.org/series/51796/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10667 =
== Summary - WARNING ==
Minor unknown changes coming with
== Series Details ==
Series: series starting with [v1,1/2] drm/i915/icl: Mind the SFC units when
resetting VD or VEBox engines
URL : https://patchwork.freedesktop.org/series/51816/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/icl: Mind the
On 10/31/18 7:24 AM, Michal Hocko wrote:
> I am also wondering whether unevictable pages culling can be
> really visible when we do the anon LRU reclaim because the swap path is
> quite expensinve on its own.
Didn't we create the unevictable lists in the first place because
scanning alone was obse
Chris Wilson writes:
> We observe that the ordering of writes for a CS event is not as strong
> from the GPU as we would like, and that on occasions we see the
> ringbuffer tail updated before the event is written into the ringbuffer,
> leading us to reuse the stale data.
>
> Through around a big
== Series Details ==
Series: series starting with [v1,1/2] drm/i915/icl: Mind the SFC units when
resetting VD or VEBox engines
URL : https://patchwork.freedesktop.org/series/51816/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10668 =
== Summary - WARNING
Quoting Mika Kuoppala (2018-10-31 14:49:38)
> Chris Wilson writes:
>
> > We observe that the ordering of writes for a CS event is not as strong
> > from the GPU as we would like, and that on occasions we see the
> > ringbuffer tail updated before the event is written into the ringbuffer,
> > lead
== Series Details ==
Series: RFT drm/i915/execlists: Flush memory before signaling ELSQ
URL : https://patchwork.freedesktop.org/series/51796/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10669 =
== Summary - WARNING ==
Minor unknown changes coming with
== Series Details ==
Series: RFT drm/i915/execlists: Flush memory before signaling ELSQ
URL : https://patchwork.freedesktop.org/series/51796/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062_full -> Patchwork_10659_full =
== Summary - WARNING ==
Minor unknown changes c
On Wed, Oct 31, 2018 at 11:00:54AM +0200, Jani Nikula wrote:
> On Wed, 31 Oct 2018, Tvrtko Ursulin wrote:
> > I saw some mention somewhere on IS_GEN_RANGE, which looked clearer than
> > IS_GEN(dev_priv, s, e). Presumably that did not go anywhere since now
> > the proposal is the above? I have to
We no longer need to differentiate between 4LVL and FULL ppgtt as
the number of bits in the address range provides that information now.
Signed-off-by: Bob Paauwe
---
drivers/gpu/drm/i915/i915_drv.h | 2 --
drivers/gpu/drm/i915/i915_pci.c | 4 ++--
drivers/gpu/drm/i915/in
48 bit ppgtt device configuration is really just extended address
range full ppgtt and may actually be something other than 48 bits.
Change HAS_FULL_48BIT_PPGTT() to HAS_4LVL_PPGTT() to better
describe that a 4 level walk table extended range PPGTT is being
used. Add a new device info field that s
With the address range being specified for each platform, we can use
that instead of the .ppgtt enum to handle the differences between
3 level and 4 level PPGTT. In most cases, we really only care if the
platform supports PPGTT or not. Because of this, we can now remove
the HAS_FULL_PPGTT macro and
On Wed, Oct 31, 2018 at 03:10:15PM +0200, Ville Syrjälä wrote:
> On Tue, Oct 30, 2018 at 04:53:49PM -0700, Manasi Navare wrote:
> > On Wed, Oct 24, 2018 at 03:28:24PM -0700, Manasi Navare wrote:
> > > Basic DSC parameters and DSC configuration data needs to be computed
> > > for each of the request
== Series Details ==
Series: RFT drm/i915/execlists: Flush memory before signaling ELSQ
URL : https://patchwork.freedesktop.org/series/51796/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10670 =
== Summary - SUCCESS ==
No regressions found.
External
On Wed, Oct 31, 2018 at 09:05:05AM -0700, Manasi Navare wrote:
> On Wed, Oct 31, 2018 at 03:10:15PM +0200, Ville Syrjälä wrote:
> > On Tue, Oct 30, 2018 at 04:53:49PM -0700, Manasi Navare wrote:
> > > On Wed, Oct 24, 2018 at 03:28:24PM -0700, Manasi Navare wrote:
> > > > Basic DSC parameters and DS
From ICL onwards DDI/TypeC ports - even in HDMI static mode - need to know
which AUX CH belongs to them, so initialize aux_ch for those ports too.
For consistency do this for all HDMI ports, not only for DDI/TypeC ones.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Cc: José Roberto de Souza
Signed-off-by:
From ICL onwards all the DDI/TypeC ports - even working in HDMI mode -
need to know their corresponding AUX channel, so move the corresponding
helper to a common place.
No functional change.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Cc: José Roberto de Souza
Signed-off-by: Imre Deak
Reviewed-by: Jos
v3 of https://patchwork.freedesktop.org/series/51765/ addressing
Jose's and Lucas' review comments.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Cc: José Roberto de Souza
Cc: Lucas De Marchi
Cc: Manasi Navare
Imre Deak (8):
drm/i915: Move intel_aux_ch() to intel_bios.c
drm/i915: Move aux_ch to int
BIOS can leave the PLL to port mapping enabled, even if the
corresponding encoder is disabled. Disable the port mapping in this
case.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Cc: José Roberto de Souza
Signed-off-by: Imre Deak
Reviewed-by: José Roberto de Souza
---
drivers/gpu/drm/i915/intel_ddi.c
From ICL onwards the AUX power domain may change dynamically based on
whether a DDI/TypeC port is in thunderbolt or non-thunderbolt mode, so
use a helper function instead of a static field to get the current
domain.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Cc: José Roberto de Souza
Cc: Lucas De March
For DDI/TypeC ports the AUX power domain needs to be enabled before the
port's PLL is enabled, so move the enabling earlier accordingly.
v2:
- Preserve the pre_pll hook for GEN9_LP. (Ville)
v3:
- Add related BSpec entries to commit log. (Jose)
BSpec: 21750, 22243
Cc: Paulo Zanoni
Cc: Ville Syrjä
From ICL onwards all DDI/TypeC ports - even working in HDMI mode - need
to know their corresponding AUX CH, so move the field to a common
struct.
No functional change.
v3:
- Add code comment about which ports aux_ch is used for. (Jose)
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Cc: José Roberto de Sou
Most of the AUX_CH_CTL flags are concerned with DP AUX transfer
parameters. As opposed to this the flag specifying the thunderbolt vs.
non-thunderbolt mode of the port is not related to AUX transfers at all
(rather it's repurposed to enable either TBT or non-TBT PHY HW blocks).
The programming has
DDI/TypeC ports need the AUX power domain for main link functionality
even when they operate in HDMI static mode, so enable the power domain
for these ports too.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Cc: José Roberto de Souza
Signed-off-by: Imre Deak
Reviewed-by: José Roberto de Souza
---
drive
First of all I believe this WA as written here was wrong.
Because it is listed on BSpec only for SKL and BXT, exactly
the only 2 platforms skipped here.
But also it is written there that we don't need this WA
anymore:
"This workaround is no longer needed since NV12 support is
dropped for the affe
CNL A stepping was the only affected there.
But also it is time to clean old pre-production
CNL Workarounds, so let's just remove and clean
this W/A.
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Signed-off-by: Rodrigo Vivi
Reviewed-by: Clint Taylor
---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
Let's introduce the WA number that is the
cause of having NV12 disabled on both SLK and BXT.
According to Spec:
WA 0870: "Display flickers with NV12 video playback in
Y tiling mode.
WA: Use YUV422 surface format instead of NV12."
v2: remove the useless dead code and consequently
avoiding dev
According to BSpec this is not needed anymore:
"This workaround is no longer needed since NV12
support is dropped for the affected projects.
"
Cc: Maarten Lankhorst
Cc: Ville Syrjälä
Signed-off-by: Rodrigo Vivi
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 11 ---
== Series Details ==
Series: RFT drm/i915/execlists: Flush memory before signaling ELSQ
URL : https://patchwork.freedesktop.org/series/51796/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10671 =
== Summary - WARNING ==
Minor unknown changes coming with
On Wed, Oct 31, 2018 at 05:34:19AM -0700, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Roper, Matthew D
> >Sent: Tuesday, October 30, 2018 4:59 AM
> >To: Shankar, Uma
> >Cc: intel-gfx@lists.freedesktop.org; Syrjala, Ville
> >;
> >Lankhorst, Maarten
> >Subject: Re: [Intel-gfx]
On Wed 31-10-18 07:40:14, Dave Hansen wrote:
> On 10/31/18 7:24 AM, Michal Hocko wrote:
> > I am also wondering whether unevictable pages culling can be
> > really visible when we do the anon LRU reclaim because the swap path is
> > quite expensinve on its own.
>
> Didn't we create the unevictable
Quoting Patchwork (2018-10-31 16:37:57)
> == Series Details ==
>
> Series: RFT drm/i915/execlists: Flush memory before signaling ELSQ
> URL : https://patchwork.freedesktop.org/series/51796/
> State : success
>
> == Summary ==
>
> = CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10671 =
>
== Series Details ==
Series: drm/i915/icl: Fix HDMI on TypeC static ports (rev3)
URL : https://patchwork.freedesktop.org/series/51765/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
700413b4d745 drm/i915: Move intel_aux_ch() to intel_bios.c
-:49: CHECK:SPACING: No space is neces
== Series Details ==
Series: drm/i915/icl: Fix HDMI on TypeC static ports (rev3)
URL : https://patchwork.freedesktop.org/series/51765/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Move intel_aux_ch() to intel_bios.c
-drivers/gpu/drm/i915/se
>-Original Message-
>From: Jani Nikula [mailto:jani.nik...@linux.intel.com]
>Sent: Wednesday, October 31, 2018 2:29 AM
>To: Lucas De Marchi
>Cc: Srivatsa, Anusha ; intel-
>g...@lists.freedesktop.org; De Marchi, Lucas
>Subject: Re: [Intel-gfx] [PATCH] drm/i915/fia: FIA registers offset
>
== Series Details ==
Series: drm/i915/icl: Fix HDMI on TypeC static ports (rev3)
URL : https://patchwork.freedesktop.org/series/51765/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10672 =
== Summary - SUCCESS ==
No regressions found.
External URL:
On Wed, Oct 31, 2018 at 07:05:31PM +0530, Uma Shankar wrote:
> Plane input CSC needs to be enabled to convert frambuffers from
> YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
> the planes have hardcoded conversion and taken care by the legacy
> code.
>
> This patch defines the co-
On Wed, 2018-10-31 at 18:26 +0200, Imre Deak wrote:
> From ICL onwards all DDI/TypeC ports - even working in HDMI mode -
> need
> to know their corresponding AUX CH, so move the field to a common
> struct.
>
> No functional change.
>
> v3:
> - Add code comment about which ports aux_ch is used for
On Wed, 2018-10-31 at 18:26 +0200, Imre Deak wrote:
> From ICL onwards the AUX power domain may change dynamically based on
> whether a DDI/TypeC port is in thunderbolt or non-thunderbolt mode,
> so
> use a helper function instead of a static field to get the current
> domain.
Reviewed-by: José Ro
== Series Details ==
Series: drm/syncobj: Mark local add/remove callback functions as static
URL : https://patchwork.freedesktop.org/series/51809/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062_full -> Patchwork_10664_full =
== Summary - WARNING ==
Minor unknown chan
On Wed, 2018-10-31 at 18:26 +0200, Imre Deak wrote:
> From ICL onwards DDI/TypeC ports - even in HDMI static mode - need to
> know
> which AUX CH belongs to them, so initialize aux_ch for those ports
> too.
> For consistency do this for all HDMI ports, not only for DDI/TypeC
> ones.
>
> Cc: Paulo
== Series Details ==
Series: series starting with [CI,1/4] drm/i915: Kill WA 0528
URL : https://patchwork.freedesktop.org/series/51826/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10673 =
== Summary - FAILURE ==
Serious unknown changes coming with Pat
On Wed, Oct 31, 2018 at 05:14:52PM +, Souza, Jose wrote:
> On Wed, 2018-10-31 at 18:26 +0200, Imre Deak wrote:
> > From ICL onwards DDI/TypeC ports - even in HDMI static mode - need to
> > know
> > which AUX CH belongs to them, so initialize aux_ch for those ports
> > too.
> > For consistency d
On Wed, Oct 31, 2018 at 04:58:27PM +, Srivatsa, Anusha wrote:
> >>> > /* ICL PHY DFLEX registers */
> >>> > -#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
> >>> > +#define PORT_TX_DFLEXDPMLE1 _MMIO(FIA1_BASE +
> >PORT_TX_DFLEXDPMLE1_OFFSET)
> >
> >IMO either:
> >
> >#define _PO
>-Original Message-
>From: Lucas De Marchi [mailto:lucas.de.mar...@gmail.com]
>Sent: Wednesday, October 31, 2018 10:23 AM
>To: Srivatsa, Anusha
>Cc: Jani Nikula ;
>intel-gfx@lists.freedesktop.org; De
>Marchi, Lucas
>Subject: Re: [Intel-gfx] [PATCH] drm/i915/fia: FIA registers offset
>i
On Wed, Oct 31, 2018 at 10:29:51AM -0700, Rodrigo Vivi wrote:
> On Wed, Oct 31, 2018 at 05:14:52PM +, Souza, Jose wrote:
> > On Wed, 2018-10-31 at 18:26 +0200, Imre Deak wrote:
> > > From ICL onwards DDI/TypeC ports - even in HDMI static mode - need to
> > > know
> > > which AUX CH belongs to t
== Series Details ==
Series: RFT drm/i915/execlists: Flush memory before signaling ELSQ
URL : https://patchwork.freedesktop.org/series/51796/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10674 =
== Summary - SUCCESS ==
No regressions found.
External
== Series Details ==
Series: RFT drm/i915/execlists: Flush memory before signaling ELSQ
URL : https://patchwork.freedesktop.org/series/51796/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062_full -> Patchwork_10665_full =
== Summary - WARNING ==
Minor unknown changes c
On Wed, 31 Oct 2018, Rodrigo Vivi wrote:
> On Wed, Oct 31, 2018 at 11:00:54AM +0200, Jani Nikula wrote:
>> On Wed, 31 Oct 2018, Tvrtko Ursulin wrote:
>> > I saw some mention somewhere on IS_GEN_RANGE, which looked clearer than
>> > IS_GEN(dev_priv, s, e). Presumably that did not go anywhere sinc
On Wed, Oct 31, 2018 at 07:36:58PM +0200, Imre Deak wrote:
> On Wed, Oct 31, 2018 at 10:29:51AM -0700, Rodrigo Vivi wrote:
> > On Wed, Oct 31, 2018 at 05:14:52PM +, Souza, Jose wrote:
> > > On Wed, 2018-10-31 at 18:26 +0200, Imre Deak wrote:
> > > > From ICL onwards DDI/TypeC ports - even in HD
== Series Details ==
Series: series starting with [CI,1/4] drm/i915: Kill WA 0528
URL : https://patchwork.freedesktop.org/series/51826/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10675 =
== Summary - WARNING ==
Minor unknown changes coming with Patch
+Chris
On Tue, Aug 28, 2018 at 10:41 AM Lucas De Marchi
wrote:
>
> subvendor and subdevice are unsigned, so fix their initialization in
> INTEL_VGA_DEVICE.
>
> Cc: Chris Wilson
> Signed-off-by: Lucas De Marchi
> ---
> include/drm/i915_pciids.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deleti
On Wed, Oct 31, 2018 at 10:13:43AM +0200, Jani Nikula wrote:
> On Tue, 30 Oct 2018, Lucas De Marchi wrote:
> > On Tue, Oct 30, 2018 at 11:52:30AM +0200, Jani Nikula wrote:
> >> On Mon, 29 Oct 2018, Rodrigo Vivi wrote:
> >> > +#define IS_DISPLAY_GEN2(dev_priv)
> >> > (!!((dev_priv)->info.di
== Series Details ==
Series: RFT drm/i915/execlists: Flush memory before signaling ELSQ
URL : https://patchwork.freedesktop.org/series/51796/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10676 =
== Summary - SUCCESS ==
No regressions found.
External
== Series Details ==
Series: Enable Plane Input CSC for ICL (rev5)
URL : https://patchwork.freedesktop.org/series/51463/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5062_full -> Patchwork_10666_full =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwor
On Tue, Oct 23, 2018 at 12:12:48PM -0700, Manasi Navare wrote:
> In case of Legacy DP connector on TypeC port, the
> flex IO DPMLE register is set to number of lanes configured
> by the display driver which will be programmed into DDI_BUF_CTL
> PORT_WIDTH_SELECTION.
> This needs to be programmed be
Den 29.10.2018 10.07, skrev Daniel Vetter:
On Sun, Oct 28, 2018 at 09:46:43PM +0100, Noralf Trønnes wrote:
Den 28.10.2018 21.21, skrev David Lechner:
On 10/26/2018 05:38 PM, Noralf Trønnes wrote:
Den 17.10.2018 15.04, skrev Noralf Trønnes:
This move makes tinydrm useful for more drivers. tin
>-Original Message-
>From: Sripada, Radhakrishna
>Sent: Tuesday, October 30, 2018 1:45 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Oscar Mateo ; Srivatsa, Anusha
>; Mika Kuoppala ;
>Sripada, Radhakrishna
>Subject: [PATCH v3 4/4] drm/i915/icl: WaAllowUMDToModifySamplerMode
>
>From: Oscar
On Tue, Oct 30, 2018 at 03:35:39PM -0700, Rodrigo Vivi wrote:
> On Tue, Oct 30, 2018 at 05:30:25PM +0800, kbuild test robot wrote:
> > Hi Radhakrishna,
> >
> > Thank you for the patch! Perhaps something to improve:
> >
> > [auto build test WARNING on drm-intel/for-linux-next]
> > [also build test
>-Original Message-
>From: Sripada, Radhakrishna
>Sent: Tuesday, October 30, 2018 1:45 AM
>To: intel-gfx@lists.freedesktop.org
>Cc: Oscar Mateo ; Mika Kuoppala
>; Srivatsa, Anusha
>; Sripada, Radhakrishna
>
>Subject: [PATCH v3 3/4] drm/i915/icl: WaAllowUMDToModifyHalfSliceChicken7
>
>From
== Series Details ==
Series: RFT drm/i915/execlists: Flush memory before signaling ELSQ
URL : https://patchwork.freedesktop.org/series/51796/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062_full -> Patchwork_10667_full =
== Summary - WARNING ==
Minor unknown changes c
== Series Details ==
Series: series starting with [v1,1/2] drm/i915/icl: Mind the SFC units when
resetting VD or VEBox engines
URL : https://patchwork.freedesktop.org/series/51816/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062_full -> Patchwork_10668_full =
== Summary
== Series Details ==
Series: series starting with [v3,1/4] drm/i915/icl: Add WaEnable32PlaneMode
URL : https://patchwork.freedesktop.org/series/51736/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10677 =
== Summary - SUCCESS ==
No regressions found.
On GEN9 LP (BXT/GLK) DC6 is not supported, so don't print the counter
on those platforms. So far we did this on GLK too.
Testcase: igt/pm_dc/dc6-dpms
Cc: Jyoti Yadav
Cc: Rodrigo Vivi
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_debugfs.c | 14 +++---
1 file changed, 7 inserti
On Wed, Oct 31, 2018 at 10:02:20PM +0200, Imre Deak wrote:
> On GEN9 LP (BXT/GLK) DC6 is not supported, so don't print the counter
> on those platforms. So far we did this on GLK too.
>
> Testcase: igt/pm_dc/dc6-dpms
> Cc: Jyoti Yadav
> Cc: Rodrigo Vivi
> Signed-off-by: Imre Deak
> ---
> drive
On Mon, Oct 29, 2018 at 04:00:31PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Let's not leak obj->framebuffer_references when we decide that
> the framebuffer domensions are not suitable for NV12.
>
> Cc: sta...@vger.kernel.org
> Cc: Maarten Lankhorst
> Cc: Vidya Srinivas
> Fixes: e
Hi Dave,
A few patches to round out the merge window. 6/7 are from one series fixing up
things around bridge/panel.
drm-misc-next-fixes-2018-10-31:
- Properly label Innolux TV123WAM as P120ZDG-BF1 (Doug)
- Add optional delay for panels without hpd hooked up (which solves the
mystery delay for
On Wed, Oct 31, 2018 at 01:08:06PM -0700, Rodrigo Vivi wrote:
> On Wed, Oct 31, 2018 at 10:02:20PM +0200, Imre Deak wrote:
> > On GEN9 LP (BXT/GLK) DC6 is not supported, so don't print the counter
> > on those platforms. So far we did this on GLK too.
> >
> > Testcase: igt/pm_dc/dc6-dpms
> > Cc: J
Fixes: 3e68928b7d4c ("drm/i915/icl: Enable DC9 as lowest possible state during
screen-off")
Cc: Imre Deak
Cc: Rodrigo Vivi
Cc: Animesh Manna
Cc: James Ausmus
Cc: Daniele Ceraolo Spurio
Signed-off-by: Anusha Srivatsa
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
1 file changed, 1 insertion(+)
== Series Details ==
Series: RFT drm/i915/execlists: Flush memory before signaling ELSQ
URL : https://patchwork.freedesktop.org/series/51796/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062_full -> Patchwork_10669_full =
== Summary - SUCCESS ==
No regressions found.
== Series Details ==
Series: drm/i915/gen9_lp: Fix DMC DC counter debugfs output
URL : https://patchwork.freedesktop.org/series/51837/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10678 =
== Summary - WARNING ==
Minor unknown changes coming with Patchw
The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
from the base - which is the FLexi IO Adaptor. Lets follow the
offset calculation while accessing these registers.
v2:
- Follow spec for numbering - s/0/1(Lucas)
- s/FIA_1/FIA1_BASE (Anusha)
v3:
- Remove register offset defines. (Jan
From: Clint Taylor
reorder structure of 297, 594 N values to group Audio Sample Frequencies
together to make updating from HDMI specification easier.
V2: Match patch 1/2 version
V3: Arrange by sample freq, then pixel clock.
Cc: Jani Nikula
Signed-off-by: Clint Taylor
---
drivers/gpu/drm/i915
On Tue, Oct 30, 2018 at 05:45:13PM -0700, Anusha Srivatsa wrote:
> For DP 1.4 and above, Display Stream compression can be
> enabled only if Forward Error Correctin can be performed.
>
> Check if the sink supports FEC using the helper.
>
> v2: Mention External DP where ever FEC is mentioned
> in
On Tue, Oct 30, 2018 at 05:45:14PM -0700, Anusha Srivatsa wrote:
> Add a crtc state for FEC. Currently, the state
> is determined by platform, DP and DSC being
> enabled. Moving forward we can use the state
> to have error correction on other scenarios too
> if needed.
>
> v2:
> - Control compress
== Series Details ==
Series: RFT drm/i915/execlists: Flush memory before signaling ELSQ
URL : https://patchwork.freedesktop.org/series/51796/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10679 =
== Summary - WARNING ==
Minor unknown changes coming with
On Tue, Oct 30, 2018 at 05:45:16PM -0700, Anusha Srivatsa wrote:
> If FEC is supported, the corresponding
> DP_TP_CTL register bits have to be configured.
>
> The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register
> and wait till FEC_STATUS in DP_TP_CTL[28] is 1.
> Also add the warn me
On Tue, Oct 30, 2018 at 05:45:17PM -0700, Anusha Srivatsa wrote:
> Set the suitable bits in DP_TP_CTL to stop
> bit correction when DSC is disabled.
>
> v2:
> - rebased.
> - Add additional check for compression state. (Gaurav)
>
> v3: rebased.
>
> v4:
> - Move the code to the proper spot accordi
On Tue, Oct 30, 2018 at 05:45:10PM -0700, Anusha Srivatsa wrote:
> With Display Compression, the bit error in the pixel
> stream can turn into a significant corruption on
> the screen. The DP1.4 adds FEC - Forward Error Correction
> scheme which uses Reed-Solomon parity/correction check
> generated
On Wed, Oct 31, 2018 at 01:27:26PM -0700, Anusha Srivatsa wrote:
I intend to modify this commit message while merging with the following:
Add missing block that takes care of inline intel_suspend_complete
for DC9 on ICL.
Daniele noticed this was part of original patch but missed on
on merged com
== Series Details ==
Series: drm/i915/icl: Fix DC9 Suspend for ICL.
URL : https://patchwork.freedesktop.org/series/51838/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10680 =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10680 nee
== Series Details ==
Series: drm/i915/fia: FIA registers offset implementation. (rev3)
URL : https://patchwork.freedesktop.org/series/51566/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10681 =
== Summary - SUCCESS ==
No regressions found.
External
On Fri, Oct 19, 2018 at 05:19:28PM +0200, Tomasz Lis wrote:
> The table has been unified across OSes to minimize virtualization overhead.
>
> The MOCS table is now versioned; the patch includes version 1 entries.
>
> BSpec: 34007
> BSpec: 560
> Signed-off-by: Tomasz Lis
> Cc: Joonas Lahtinen
>
On Wed, Oct 31, 2018 at 01:41:21PM -0700, Anusha Srivatsa wrote:
> The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
> from the base - which is the FLexi IO Adaptor. Lets follow the
> offset calculation while accessing these registers.
>
> v2:
> - Follow spec for numbering - s/0/1(Lu
== Series Details ==
Series: RFT drm/i915/execlists: Flush memory before signaling ELSQ
URL : https://patchwork.freedesktop.org/series/51796/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062_full -> Patchwork_10670_full =
== Summary - SUCCESS ==
No regressions found.
== Series Details ==
Series: RFT drm/i915/execlists: Flush memory before signaling ELSQ
URL : https://patchwork.freedesktop.org/series/51796/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062 -> Patchwork_10682 =
== Summary - SUCCESS ==
No regressions found.
External
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Wednesday, October 31, 2018 2:08 PM
>To: Srivatsa, Anusha
>Cc: intel-gfx@lists.freedesktop.org; Singh, Gaurav K
>;
>Jani Nikula ; Navare, Manasi D
>
>Subject: Re: [v4 6/7] i915/dp/fec: Configure the F
== Series Details ==
Series: RFT drm/i915/execlists: Flush memory before signaling ELSQ
URL : https://patchwork.freedesktop.org/series/51796/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062_full -> Patchwork_10671_full =
== Summary - SUCCESS ==
No regressions found.
Pushed first 7 patches of this series, thanks for the reviews.
Manasi
On Wed, Oct 24, 2018 at 03:28:12PM -0700, Manasi Navare wrote:
> VESA has developed an industry standard Display Stream Compression(DSC)
> for interoperable, visually lossless compression over display links to
> address the nee
Pushed to dinq,thanks for the patch and reviews.
Manasi
On Tue, Oct 23, 2018 at 12:12:47PM -0700, Manasi Navare wrote:
> This patch fixes the macros used for defining the DFLEXDPMLE
> register bit fields. This accounts for changes in the spec.
>
> Fixes: a2bc69a1a9d6 ("drm/i915/icl: Add register
Pushed to dinq, thanks for the patch and reviews
Manasi
On Tue, Oct 23, 2018 at 12:12:48PM -0700, Manasi Navare wrote:
> In case of Legacy DP connector on TypeC port, the
> flex IO DPMLE register is set to number of lanes configured
> by the display driver which will be programmed into DDI_BUF_CT
Den 17.10.2018 15.04, skrev Noralf Trønnes:
This adds an optional function table on GEM objects.
The main benefit is for drivers that support more than one type of
memory (shmem,vram,cma) for their buffers depending on the hardware it
runs on. With the callbacks attached to the GEM object itself
On Wed, Oct 24, 2018 at 08:30:12PM +0530, Uma Shankar wrote:
> Enable ICL pipe csc hardware. CSC block is enabled
> in CSC_MODE register instead of PLANE_COLOR_CTL.
>
> v2: Addressed Maarten's review comments.
>
> Signed-off-by: Uma Shankar
> ---
> drivers/gpu/drm/i915/i915_reg.h| 1 +
> d
On Tue, Oct 30, 2018 at 05:03:57PM -0700, Matt Roper wrote:
> On Wed, Oct 24, 2018 at 08:30:11PM +0530, Uma Shankar wrote:
> > Add support for icl pipe degamma and gamma.
> >
> > v2: Removed a POSTING_READ and corrected the Bit
> > Definition as per Maarten's comments.
> >
> > Signed-off-by: Uma
On Thu, 2018-10-25 at 18:17 -0700, José Roberto de Souza wrote:
> If a PSR error happened and the driver is reloaded, the EDP_PSR_IIR
> will still keep the error set even after the reset done in the
> irq_preinstall and irq_uninstall hooks.
Does this happen or are you suspecting it might? Is this
>-Original Message-
>From: Ville Syrjälä [mailto:ville.syrj...@linux.intel.com]
>Sent: Wednesday, October 31, 2018 2:01 PM
>To: Srivatsa, Anusha
>Cc: intel-gfx@lists.freedesktop.org; Singh, Gaurav K
>;
>Jani Nikula ; Navare, Manasi D
>; Pandiyan, Dhinakaran
>
>Subject: Re: [v4 3/7] i915
== Series Details ==
Series: drm/i915/icl: Fix HDMI on TypeC static ports (rev3)
URL : https://patchwork.freedesktop.org/series/51765/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5062_full -> Patchwork_10672_full =
== Summary - SUCCESS ==
No regressions found.
==
101 - 200 of 212 matches
Mail list logo
