== Series Details ==
Series: drm/i915/icl: Enable DC9 as lowest possible state during screen-off
(rev6)
URL : https://patchwork.freedesktop.org/series/49447/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5052_full -> Patchwork_10638_full =
== Summary - SUCCESS ==
No reg
From: Hang Yuan
This reverts commit c9e666880de5a1fed04dc412b046916d542b72dd.
Checked GVT codes that guest PPGTT PTE flag bits are propagated
to shadow PTE. Read/write bit is not changed. Further tested by
i915 self-test case "igt_ctx_readonly". No error or GPU hang was
detected. So enable read-
://github.com/0day-ci/linux/commits/Matthew-Auld/drm-i915-selftest-fix-64K-alignment-in-igt_write_huge/20181030-034107
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-allmodconfig (attached as .config)
compiler: gcc-7 (Debian 7.3.0-1) 7.3.0
reproduce:
# save the attached
== Series Details ==
Series: drm/i915/gtt: Revert "Disable read-only support under GVT"
URL : https://patchwork.freedesktop.org/series/51730/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/gtt: Revert "Disable read-only support under GVT"
-dri
== Series Details ==
Series: series starting with [CI,1/7] drm/i915/dsc: Add slice_row_per_frame in
DSC PPS programming
URL : https://patchwork.freedesktop.org/series/51711/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5052_full -> Patchwork_10641_full =
== Summary - WARN
== Series Details ==
Series: drm/i915/gtt: Revert "Disable read-only support under GVT"
URL : https://patchwork.freedesktop.org/series/51730/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5053 -> Patchwork_10644 =
== Summary - SUCCESS ==
No regressions found.
External
== Series Details ==
Series: series starting with [1/5] drm/i915: Remove CNL from WA 827 (rev3)
URL : https://patchwork.freedesktop.org/series/51713/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5052_full -> Patchwork_10642_full =
== Summary - SUCCESS ==
No regressions
From: Oscar Mateo
Required for Bindless samplers.
Userspace consumer: mesa
V2: Rebase
V3: Update commit message
Cc: Anusha Srivatsa
Cc: Mika Kuoppala
Signed-off-by: Oscar Mateo
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/i915_reg.h | 2 ++
drivers/gpu/drm/i915/int
Gen11 Display suports 32 planes in total. Enable the new format in context
status to be used and expanded to 32 planes.
V2: Move the WA to display WA's(Chris)
Cc: Chris Wilson
Cc: Michel Thierry
Cc: James Ausmus
Reviewed-by: Anusha Srivatsa
Signed-off-by: Radhakrishna Sripada
---
drivers/gp
Display WA_1405510057 asks to not enable YUV 420 HDMI
10bpc when horizontal blank size mod 8 reminder is 2.
V2: Rebase(r-b: Anusha)
V3: crtc_state->s/ycbcr420/output_format/
Cc: Anusha Srivatsa
Cc: Paulo Zanoni
Cc: Rodrigo Vivi
Cc: Ville Syrjälä
Signed-off-by: Radhakrishna Sripada
---
drive
From: Oscar Mateo
Required to dinamically set 'Trilinear Filter Quality Mode'
Userpsace consumer is mesa.
V2: Rebase
V3: Update commit message
Cc: Mika Kuoppala
Cc: Anusha Srivatsa
Signed-off-by: Oscar Mateo
Signed-off-by: Radhakrishna Sripada
---
drivers/gpu/drm/i915/intel_workarounds.c |
On Tue, Oct 30, 2018 at 12:17:30PM +1000, Dave Airlie wrote:
> On Fri, 19 Oct 2018 at 18:51, Daniel Vetter wrote:
> >
> > Hi all,
> >
> > This is just to collect feedback on this idea, and see whether the
> > overall dri-devel community stands on all this. I think the past few
> > cross-vendor uap
On Mon, Oct 29, 2018 at 03:24:29PM +0100, Daniel Vetter wrote:
> On Fri, Oct 26, 2018 at 04:35:47PM -0400, Lyude Paul wrote:
> > There has been a TODO waiting for quite a long time in
> > drm_dp_mst_topology.c:
> >
> > /* We cannot rely on port->vcpi.num_slots to update
> > * topology_sta
Quoting Radhakrishna Sripada (2018-10-30 08:45:04)
> From: Oscar Mateo
>
> Required for Bindless samplers.
> Userspace consumer: mesa
>
> V2: Rebase
> V3: Update commit message
>
> Cc: Anusha Srivatsa
> Cc: Mika Kuoppala
> Signed-off-by: Oscar Mateo
> Signed-off-by: Radhakrishna Sripada
> -
== Series Details ==
Series: series starting with [v3,1/4] drm/i915/icl: Add WaEnable32PlaneMode
URL : https://patchwork.freedesktop.org/series/51736/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5053 -> Patchwork_10645 =
== Summary - FAILURE ==
Serious unknown changes
Hi Radhakrishna,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on v4.19 next-20181030]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com
Quoting Chris Wilson (2018-10-30 09:12:20)
> Quoting Radhakrishna Sripada (2018-10-30 08:45:04)
> > From: Oscar Mateo
> >
> > Required for Bindless samplers.
> > Userspace consumer: mesa
> >
> > V2: Rebase
> > V3: Update commit message
> >
> > Cc: Anusha Srivatsa
> > Cc: Mika Kuoppala
> > Sig
Hi Radhakrishna,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on v4.19 next-20181030]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https
Chris Wilson writes:
> After reading the event status from the CSB, write back 0 (an invalid
> value) so we can detect if the HW should signal a new event without
> writing the event in the future.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=108315
> Signed-off-by: Chris Wilson
On Mon, Oct 29, 2018 at 04:00:04PM -0700, Eric Anholt wrote:
> Ville Syrjala writes:
>
> > From: Ville Syrjälä
> >
> > Add a function to check whether there is at least one plane that
> > supports a specific format and modifier combination. Drivers can
> > use this to reject unsupported formats/
Quoting Mika Kuoppala (2018-10-30 09:31:56)
> Chris Wilson writes:
>
> > After reading the event status from the CSB, write back 0 (an invalid
> > value) so we can detect if the HW should signal a new event without
> > writing the event in the future.
> >
> > References: https://bugs.freedesktop.
On Mon, 29 Oct 2018, Rodrigo Vivi wrote:
> Introduce Display Gen. The goal is to use this to minimize
> the amount of platform codename checks we have nowdays on
> display code.
>
> The introduction of a new platform should be just
> gen >= current.
So the patches 1-3 look nice for GLK. The thing
Chris Wilson writes:
> Quoting Mika Kuoppala (2018-10-30 09:31:56)
>> Chris Wilson writes:
>>
>> > After reading the event status from the CSB, write back 0 (an invalid
>> > value) so we can detect if the HW should signal a new event without
>> > writing the event in the future.
>> >
>> > Refer
== Series Details ==
Series: Implement HDCP2.2: PART-I (rev2)
URL : https://patchwork.freedesktop.org/series/51495/
State : failure
== Summary ==
Applying: drm/i915: wrapping all hdcp var into intel_hdcp
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/i915_debugfs.c
== Series Details ==
Series: drm/i915/execlists: Poison the CSB after use
URL : https://patchwork.freedesktop.org/series/51703/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5054 -> Patchwork_10646 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_1
Hi Manasi,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on v4.19 next-20181030]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https
Op 26-10-18 om 12:01 schreef Uma Shankar:
> Plane input CSC needs to be enabled to convert frambuffers from
> YUV to RGB. This is needed for bottom 3 planes on ICL, rest of
> the planes have hardcoded conversion and taken care by the legacy
> code.
>
> This patch defines the co-efficient values for
If we reduce the suspend function for intel_opregion to do the minimum
required, the resume function can also do the simple task of notifier
the ACPI bios that we are back. This avoid some nasty restrictions on
the likes of register_acpi_notifier() that are not allowed during the
early phase of res
== Series Details ==
Series: drm/i915/execlists: Poison the CSB after use
URL : https://patchwork.freedesktop.org/series/51703/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5054 -> Patchwork_10648 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_1
== Series Details ==
Series: drm/i915: Stop calling intel_opregion unregister/register in
suspend/resume (rev2)
URL : https://patchwork.freedesktop.org/series/50630/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
4e7c4e2dac56 drm/i915: Stop calling intel_opregion unregister/reg
On Mon, Oct 29, 2018 at 02:35:36PM -0700, Manasi Navare wrote:
> On Mon, Oct 29, 2018 at 10:39:21PM +0200, Ville Syrjälä wrote:
> > On Wed, Oct 24, 2018 at 03:28:39PM -0700, Manasi Navare wrote:
> > > DSC can be supported per DP connector. This patch adds a per connector
> > > debugfs node to expos
On Mon, Oct 29, 2018 at 03:12:51PM -0700, Manasi Navare wrote:
> On Mon, Oct 29, 2018 at 10:30:39PM +0200, Ville Syrjälä wrote:
> > On Wed, Oct 24, 2018 at 03:28:25PM -0700, Manasi Navare wrote:
> > > DSC params like the enable, compressed bpp, slice count and
> > > dsc_split are added to the intel
On Mon, Oct 29, 2018 at 04:08:43PM -0700, Manasi Navare wrote:
> On Mon, Oct 29, 2018 at 10:34:58PM +0200, Ville Syrjälä wrote:
> > On Mon, Oct 29, 2018 at 10:30:39PM +0200, Ville Syrjälä wrote:
> > > On Wed, Oct 24, 2018 at 03:28:25PM -0700, Manasi Navare wrote:
> > > > DSC params like the enable,
== Series Details ==
Series: drm/i915: Stop calling intel_opregion unregister/register in
suspend/resume (rev2)
URL : https://patchwork.freedesktop.org/series/50630/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5054 -> Patchwork_10649 =
== Summary - SUCCESS ==
No regre
Next version of [1]. Now includes all the patches I'm juggling, although
I haven't gone through the patches toward the end of the series all that
much. Still needs the DSI PLL stuff Vandita covers.
Also available at icl-dsi-2018-10-30 branch of [2].
The patches that include my Reviewed-by I haven
From: Madhav Chauhan
This patch moves intl_dsi_host_init() code to intel_dsi.c so that legacy
and gen11 DSI code can share this code.
v2 by Jani:
- Move the shared stuff to intel_dsi.c
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi.c | 34 +++
From: Madhav Chauhan
Driver needs payload/header credits for sending any command
and data over DSI link. These credits are released once command
or data sent to link. This patch adds functions to wait for releasing
of payload and header credits.
As per BSPEC, driver needs to ensure that all of c
From: Madhav Chauhan
This patch disables transcoders by writing to TRANS_CONF
registers for each DSI ports.
v2 by Jani:
- Wait for pipeconf active to go low
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 26 ++
1 file ch
From: Madhav Chauhan
This patch disables DDI function by writing to
TRANS_DDI_FUNC_CTL registers of DSI ports as part
of DSI disable sequence.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 8
1 file changed, 8
From: Madhav Chauhan
As part of DSI disabling sequence, DSI link need to enter
in ULPS by writing into DSI_LP_MSG register. This patch
does the same using a wrapper function.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c
From: Madhav Chauhan
This patch disables both DSI ports by writing to
DDI_BUF_CTL registers as part of DSI encoder disable
sequence.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 23 +++
1 file chang
From: Madhav Chauhan
This patch disables portsync mode if DSI link
is operating in dual link mode by writing to
TRANS_DDI_FUNC_CTL2 registers.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 10 ++
1 file changed,
From: Madhav Chauhan
This patch programs maximum size of the payload transmitted
from peripheral back to the host processor using short packet
as a part of panel programming.
v2: Rebase
v3 by Jani:
- Add FIXME note.
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/d
From: Madhav Chauhan
This patch configures mode of combo phy as DDI and
disable IO power for DDI ports used by DSI.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 23 +++
1 file changed, 23 insertions
From: Madhav Chauhan
This patch enables backlight of DSI panel by using VBT
BACKLIGHT_ON sequence and panel specific functions.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 6 ++
1 file changed, 6 insertions(+)
di
From: Madhav Chauhan
Program the timeout values (in escape clock) for HS TX, LP RX and TA
timeout.
HX TX: Ensure that host does not continuously transmit in the HS
state. If this timer expires, then host will gracefully end its HS
transmission and allow the link to enter into LP state.
LP RX: M
This patch allocates memory for DSI encoder and connector
which will be used for various DSI encoder/connector operations
and attaching the same to DRM subsystem. This patch also extracts
DSI modes info from VBT and save the desired mode info to connector.
v2 by Jani:
- Drop GEN11 prefix from enc
From: Madhav Chauhan
Move DSI connector functions to intel_dsi.c and make them available to
both legacy and ICL DSI.
v2 by Jani:
- Move the functions to intel_dsi.c
- Don't reuse intel_dsi_connector_destroy()
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915
From: Madhav Chauhan
This patch execute poweron, deassert reset, display on
VBT sequences and send TURN_ON DSI command to panel for
powering it up.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 7 +++
1 file changed
From: Madhav Chauhan
This patch disbles backlight of DSI panel by using VBT
BACKLIGHT_OFF sequence and panel specific disable functions.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 12
1 file changed, 12
This patch allocates DSI host structure for each
DSI port available on gen11 and register them with
DSI fwk of DRM. Some of the DSI host operations are
also registered as part of this. This patch also fills
MIPI config block info from VBT to local structure.
v2 by Jani:
- indentation
Signed-off-
From: Madhav Chauhan
This patch defines DSI_HTX_TO, DSI_LRX_H_TO, DSI_PWAIT_TO
and DSI_TA_TO registers for DSI transcoders '0' and '1'.
They are used for contention recovery on DPHY.
v2: Define SHIFT for bitfields.
v3 by Jani:
- Fix timeout bit definitions
Signed-off-by: Madhav Chauhan
Signed
From: Madhav Chauhan
This patch sends command and executes display off,
assert reset, power off VBT seqeuences to power
down DSI panel. Patch also adds high level function
to wrap all the panel sepcific programming during
DSI disabling.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Si
From: Madhav Chauhan
This patch retrieves DSI pkt (from DSI msg) to be
sent over DSI link using DRM DSI exported functions.
A wrapper function is also added as "DSI host transfer"
for sending DSI data/cmd.
v2 by Jani:
- Use the new credit available helper
- Use int for free_credits
Signed-of
From: Madhav Chauhan
This patch assigns connector functions for DSI to
DRM connector structure.
v2 by Jani:
- use common connector destroy hook
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 9 +
1 file changed, 9 insertions(+)
diff --
From: Madhav Chauhan
This patch registers DSI connectors helper functions
with DRM driver.
v2 by Jani:
- Indentation change
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/
From: Madhav Chauhan
This patch implements compute config and enable function
for Gen11 DSI encoder which is required at the time of
modeset. Enable function is empty as functionality is
implemented inside pre-enable function but still needed
otherwise null pointer dereference during modeset.
v2
From: Madhav Chauhan
This patch fills backlight, CABC and general port
info for Gen11 DSI.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/icl
From: Madhav Chauhan
This patch read out the current hw state for DSI and
return true if encoder is active.
v2 by Jani:
- Squash connector get hw state hook here
- Squash encode get hw state fix here
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.
From: Madhav Chauhan
This patch defines payload/header registers for each DSI
transcoder used for transmitting DSI packets.
v2 by Jani:
- Drop full register mask and shift for payload
- Use lower case for hex 0x
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i
From: Madhav Chauhan
This patch detects DSI presence for ICL platform
by reading VBT. DSI detection is done while initializing
DSI using newly added function intel_gen11_dsi_init.
v2 by Jani:
- Preserve old behavour of intel_bios_is_dsi_present()
- s/intel_gen11_dsi_init/icl_dsi_init/g
Signed
From: Madhav Chauhan
This patch implements the functionality for getting PIPE
configuration to which DSI encoder is connected. Used during
the atomic modeset.
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/icl_dsi.c | 14 ++
1 file changed, 14 in
This patch adds DSI packet payload to command payload
queue using credit based mechanism for *long* packets.
v2 by Jani:
- Add intel_dsi local variable for better code flow
- Use the new credit available helper
- Use int for free_credits, i, and j
Signed-off-by: Madhav Chauhan
Signed-off-by:
From: Madhav Chauhan
There are two panel power sequencers. Each register
has two addressable instances. This patch defines
both the instances of Panel power control register
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 11 +++
1 file c
From: Anusha Srivatsa
Add defines for DSS_CTL registers.
These registers specify the big joiner, splitter,
overlap pixels and info regarding
compression enabled on left or right branch.
v2:
- rebase. Remove overlapping defines(James Ausmus)
- Rename the register to ICL_DSS_CTL1/2_PIPE_ (manasi)
From: Madhav Chauhan
For ICELAKE DSI, Display Pins are the only GPIOs
that need to be programmed. So DSI driver should have
its own implementation to toggle these pins based on
GPIO info coming from VBT sequences instead of using
platform specific GPIO driver.
Signed-off-by: Madhav Chauhan
Sign
From: Madhav Chauhan
For Gen11 DSI, we use similar registers like for eDP
to find if DSI encoder is connected or not to a pipe.
This patch refactors existing hsw_get_transcoder_state()
to handle this.
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_disp
From: Madhav Chauhan
This patch configures DSI video mode dual link by
programming DSS_CTL registers.
v2: Use new bitfield definitions from Anusha's patch
Correct register to be programmed and use max
depth buffer value (James)
v3 by Jani:
- checkpatch fixes
Signed-off-by: Madhav Chau
From: Madhav Chauhan
Transcoder timings for Gen11 DSI encoder
is available at pipe level unlike in older platform
where port specific registers need to be accessed.
v2 by Jani:
- get timings for (!dsi || icl) instead of (dsi && icl).
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
-
From: Madhav Chauhan
Gen11 DSI doesn't use DCS commands based functionality
for enabling/disabling backlight but uses PWM based
functions similar to eDP.
Note by Jani: This should be decided by VBT, not hard coded. DCS
brightness control is still a thing.
Signed-off-by: Madhav Chauhan
Signed-o
From: Madhav Chauhan
This patch define missing bitfield for shortplug ctl ddi
register which will be used for ICL DSI GPIO programming.
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/
From: Madhav Chauhan
For Gen11 DSI, we don't need to wait for getting
DSI FIFO empty after sending DCS commands.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi_vbt.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
From: Madhav Chauhan
Display Pins are the only GPIOs that need to be used by
driver for DSI panels. So driver should now have its own
implementation to toggle these pins based on GPIO info
received from VBT sequences.
Signed-off-by: Madhav Chauhan
Signed-off-by: Jani Nikula
---
drivers/gpu/dr
== Series Details ==
Series: drm/i915/icl: dsi enabling (rev3)
URL : https://patchwork.freedesktop.org/series/51011/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b251037fd588 drm/i915/icl: Move dsi host init code to common file
a43a103a8a44 drm/i915/dsi: move connector mode fu
== Series Details ==
Series: drm/i915/icl: dsi enabling (rev3)
URL : https://patchwork.freedesktop.org/series/51011/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915/icl: Move dsi host init code to common file
Okay!
Commit: drm/i915/dsi: move c
== Series Details ==
Series: drm/i915/icl: dsi enabling (rev3)
URL : https://patchwork.freedesktop.org/series/51011/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5054 -> Patchwork_10650 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10650 absolu
On Tue, 30 Oct 2018, Jani Nikula wrote:
> Jani Nikula (3):
> drm/i915/icl: Allocate DSI encoder/connector
> drm/i915/icl: Allocate hosts for DSI ports
> drm/i915/icl: Load DSI packet payload to queue
These are by Madhav, I accidentally took authorship while
rebasing. Fixed locally.
BR,
Jan
Hi Matthew,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on v4.19 next-20181030]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
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== Series Details ==
Series: drm/i915/gtt: Revert "Disable read-only support under GVT"
URL : https://patchwork.freedesktop.org/series/51730/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5053_full -> Patchwork_10644_full =
== Summary - WARNING ==
Minor unknown changes c
On Mon, Oct 29, 2018 at 08:49:58PM +, Chris Wilson wrote:
> Older platforms require fence registers to perform blits, and so
> userspace is expected to mark up the objects to request fences be
> assigned.
>
> Fixes: ff2db94acb53 ("igt/gem_tiled_fence_blits: Remove libdrm_intel
> dependence")
On Mon, 29 Oct 2018, Anusha Srivatsa wrote:
> The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
> from the base - which is the FLexi IO Adaptor. Lets follow the
> offset calculation while accessing these registers.
Why?
If I search the specs or i915_reg.h for, say, 0x1638c0 I'll fi
On Tue, Oct 30, 2018 at 01:56:40PM +0200, Jani Nikula wrote:
> From: Madhav Chauhan
>
> For ICELAKE DSI, Display Pins are the only GPIOs
> that need to be programmed. So DSI driver should have
> its own implementation to toggle these pins based on
> GPIO info coming from VBT sequences instead of
On Tue, Oct 30, 2018 at 01:56:43PM +0200, Jani Nikula wrote:
> From: Madhav Chauhan
>
> For Gen11 DSI, we use similar registers like for eDP
> to find if DSI encoder is connected or not to a pipe.
> This patch refactors existing hsw_get_transcoder_state()
> to handle this.
>
> Signed-off-by: Mad
On Tue, 30 Oct 2018, Ville Syrjälä wrote:
> On Tue, Oct 30, 2018 at 01:56:40PM +0200, Jani Nikula wrote:
>> From: Madhav Chauhan
>>
>> For ICELAKE DSI, Display Pins are the only GPIOs
>> that need to be programmed. So DSI driver should have
>> its own implementation to toggle these pins based on
On Tue, Oct 30, 2018 at 10:35:07AM +0100, Daniel Vetter wrote:
> On Mon, Oct 29, 2018 at 04:00:04PM -0700, Eric Anholt wrote:
> > Ville Syrjala writes:
> >
> > > From: Ville Syrjälä
> > >
> > > Add a function to check whether there is at least one plane that
> > > supports a specific format and
On Tue, Oct 30, 2018 at 6:56 AM Jani Nikula wrote:
>
> On Mon, 29 Oct 2018, Anusha Srivatsa wrote:
> > The registers DPCSSS,DPSP,DPMLE1 and DPPMS are all at an offset
> > from the base - which is the FLexi IO Adaptor. Lets follow the
> > offset calculation while accessing these registers.
>
> Why
On Tue, Oct 30, 2018 at 04:18:28PM +0200, Ville Syrjälä wrote:
> On Tue, Oct 30, 2018 at 10:35:07AM +0100, Daniel Vetter wrote:
> > On Mon, Oct 29, 2018 at 04:00:04PM -0700, Eric Anholt wrote:
> > > Ville Syrjala writes:
> > >
> > > > From: Ville Syrjälä
> > > >
> > > > Add a function to check w
From ICL onwards all DDI/TypeC ports - even working in HDMI mode - need
to know their corresponding AUX CH, so move the field to a common
struct.
No functional change.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_ddi.c | 4 +++-
drivers/gpu/drm/i
ICL has repurposed some of the AUX HW signals/flags, so that we have to
program these for HDMI too. In practice this means enabling the AUX
power well for HDMI mode too.
The last patch fixes an issue where BIOS leaves the PLL->port mapping
enabled even though the corresponding encoder is disabled.
From ICL onwards all the DDI/TypeC ports - even working in HDMI mode -
need to know their corresponding AUX channel, so move the corresponding
helper to a common place.
No functional change.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/i915_drv.h | 1
For DDI/TypeC ports the AUX power domain needs to be enabled before the
port's PLL is enabled, so move the enabling earlier accordingly.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_ddi.c | 46 +---
drivers/gpu/d
DDI/TypeC ports need the AUX power domain for main link functionality
even when they operate in HDMI static mode, so enable the power domain
for these ports too.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_ddi.c | 15 +++
1 file change
BIOS can leave the PLL to port mapping enabled, even if the
corresponding encoder is disabled. Disable the port mapping in this
case.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/drm/i915/intel_ddi.c | 23 +++
drivers/gpu/drm/i915/intel_di
From ICL onwards DDI/TypeC ports - even in HDMI static mode - need to know
which AUX CH belongs to them, so initialize aux_ch for those ports too.
For consistency do this for all HDMI ports, not only for DDI/TypeC ones.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gp
From ICL onwards the AUX power domain may change dynamically based on
whether a DDI/TypeC port is in thunderbolt or non-thunderbolt mode, so
use a helper function instead of a static field to get the current
domain.
Cc: Paulo Zanoni
Cc: Ville Syrjälä
Signed-off-by: Imre Deak
---
drivers/gpu/dr
Most of the AUX_CH_CTL flags are concerned with DP AUX transfer
parameters. As opposed to this the flag specifying the thunderbolt vs.
non-thunderbolt mode of the port is not related to AUX transfers at all
(rather it's repurposed to enable either TBT or non-TBT PHY HW blocks).
The programming has
== Series Details ==
Series: drm/i915: Stop calling intel_opregion unregister/register in
suspend/resume (rev2)
URL : https://patchwork.freedesktop.org/series/50630/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5054_full -> Patchwork_10649_full =
== Summary - SUCCESS ==
== Series Details ==
Series: drm/i915/icl: dsi enabling (rev3)
URL : https://patchwork.freedesktop.org/series/51011/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_5055 -> Patchwork_10651 =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_10651 absolu
== Series Details ==
Series: drm/i915/icl: Fix HDMI on TypeC static ports
URL : https://patchwork.freedesktop.org/series/51765/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
83eb4def4751 drm/i915: Move intel_aux_ch() to intel_bios.c
-:47: CHECK:SPACING: No space is necessary af
== Series Details ==
Series: drm/i915/icl: Fix HDMI on TypeC static ports
URL : https://patchwork.freedesktop.org/series/51765/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Move intel_aux_ch() to intel_bios.c
-drivers/gpu/drm/i915/selftests
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