Quoting Tvrtko Ursulin (2018-09-05 15:25:44)
> From: Lionel Landwerlin
>
> Verifies that the kernel programs slices correctly based by reading
> the value of PWR_CLK_STATE register or MI_SET_PREDICATE on platforms
> before Cannonlake.
>
> v2: Add subslice tests (Lionel)
> Use MI_SET_PREDICAT
== Series Details ==
Series: drm/i915: add LG eDP panel to quirk database
URL : https://patchwork.freedesktop.org/series/49251/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e5c2ff993f03 drm/i915: add LG eDP panel to quirk database
-:36: WARNING:LONG_LINE: line over 100 charact
== Series Details ==
Series: drm/i915: add LG eDP panel to quirk database
URL : https://patchwork.freedesktop.org/series/49251/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: add LG eDP panel to quirk database
-O:drivers/gpu/drm/i915/intel_display.c:6702:18: warnin
Quoting Chris Wilson (2018-09-05 16:31:16)
> Since this is handling user provided bpp and depth, we need to sanity
> check and propagate the EINVAL back rather than assume what the insane
> client intended and fill the logs with DRM_ERROR.
>
> v2: Check both bpp and depth match the builtin pixel f
== Series Details ==
Series: drm/i915: add LG eDP panel to quirk database
URL : https://patchwork.freedesktop.org/series/49251/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4776 -> Patchwork_10105 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https:/
On Thu, 06 Sep 2018, "Lee, Shawn C" wrote:
> The N value was computed by kernel driver that based on synchronous clock
> mode. But only specific N value (0x8000) would be acceptable for
> LG LP140WF6-SPM1 eDP panel which is running at asynchronous clock mode.
As I wrote before, it's the DP source
On Thu, 06 Sep 2018, "Lee, Shawn C" wrote:
> The N value was computed by kernel driver that based on synchronous clock
> mode. But only specific N value (0x8000) would be acceptable for
> LG LP140WF6-SPM1 eDP panel which is running at asynchronous clock mode.
> With the other N value, Tcon will en
Using the guc, we cannot disable the user interrupt generation as we use
it for driving submission. And from Icelake, we no longer have the
ability to individually mask interrupt generation from each engine,
disabling our ability to fake missed interrupts.
In both cases, report back to userspace t
The prior assumption was that we did not need to reset the CSB on
wedging when cancelling the outstanding requests as it would be cleaned
up in the subsequent reset prior to restarting the GPU. However, what
was not accounted for was that in performing the reset, we would try to
process the outstan
That we use a WB mapping for updating the RING_TAIL register inside the
context image even on !llc machines has been a source of consternation
for every reader. It appears to work on bsw+, but it may just have been
that we have been incredibly bad at detecting the errors.
v2: With extra enthusiasm
If the request is currently on the HW (in port 0), then we do not need
to kick the submission tasklet to evaluate whether we should be
preempting itself in order to execute it again.
In the case that was annoying me:
execlists_schedule: rq(18:211173).prio=0 -> 2
need_preempt: last(18:211174
We need to exercise the HW and submission paths for switching contexts
rapidly to check that features such as execlists' wa_tail are adequate.
Plus it's an interesting baseline latency metric.
v2: Check the initial request for allocation errors
Signed-off-by: Chris Wilson
---
.../gpu/drm/i915/s
Fix up the error unwind for logical_ring_init() failing by moving the
cleanup into the callers who own the various bits of state during
initialisation.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c | 18 +++---
1 file changed, 11 insertions(+), 7 deletions(-)
diff
Now that we reload both RING_HEAD and RING_TAIL when rebinding the
context, we do not need to scrub those registers immediately on resume.
v2: Handle the perma-pinned contexts.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Mika Kuoppala
---
drivers/gpu/drm/i915/intel_lrc.c | 29 +
Move max firmware size to the same if ladder with firmware name and
required version. This allows us to detect the missing max size for a
platform without actually loading the firmware, and makes the whole
thing easier to maintain.
We need to move the power get earlier to allow for early return in
With i915.dmc_firmware_path="" it's obvious the intention is to disable
CSR firmware loading. Bypass the firmware request altogether in this
case, with more obvious debug logging.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_csr.c | 6 ++
1 file changed, 6 insertions(+)
diff --
Having two separate if ladders gets increasingly hard to maintain. Put
them together.
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_csr.c | 54
2 files changed, 23 insertions(+), 32 deletions(-)
diff -
Quoting Michal Wajdeczko (2018-08-29 22:10:36)
> Upcoming Gen11 GuC firmware requires new interface that is incompatible
> with existing pre-Gen11 firmwares. Updated firmwares for pre-Gen11 will
> arrive later. In the meantime sanitize the enable_guc option so that we
> can enable HuC authenticatio
Quoting Michal Wajdeczko (2018-08-29 22:10:36)
> Upcoming Gen11 GuC firmware requires new interface that is incompatible
> with existing pre-Gen11 firmwares. Updated firmwares for pre-Gen11 will
> arrive later. In the meantime sanitize the enable_guc option so that we
> can enable HuC authenticatio
== Series Details ==
Series: series starting with [1/7] drm/i915: Missed interrupt simulation is no
more, tell the world
URL : https://patchwork.freedesktop.org/series/49255/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ac19c8f1d890 drm/i915: Missed interrupt simulation is no
Quoting Michal Wajdeczko (2018-08-29 22:10:37)
> Definition of the parameters block passed to GuC is about to change.
> Slightly refactor code now to make upcoming patch smaller.
>
> Signed-off-by: Michal Wajdeczko
> Cc: Joonas Lahtinen
> Cc: John Spotswood
Reviewed-by: Joonas Lahtinen
Regar
== Series Details ==
Series: series starting with [1/7] drm/i915: Missed interrupt simulation is no
more, tell the world
URL : https://patchwork.freedesktop.org/series/49255/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Missed interrupt simulation is no more, te
Quoting Michal Wajdeczko (2018-08-29 22:10:38)
> Gen11 GuC boot parameter definitions are different than previously
> used for Gen9. Try to support both definitions until new firmwares
> for pre-Gen11 will be available.
This is exactly the kind of branching we want to avoid. Purpose of the
GuC is
On Wed, Sep 05, 2018 at 05:03:46PM -0700, Deepak Rawat wrote:
> Add DRIVER_VMWGFX to represent vmwgfx device for running igt tests.
>
> Signed-off-by: Deepak Rawat
> ---
> lib/drmtest.c | 9 -
> lib/drmtest.h | 3 +++
> 2 files changed, 11 insertions(+), 1 deletion(-)
>
> diff --git a/l
Quoting Deepak Rawat (2018-09-06 01:03:47)
> vmwgfx does not support GEM interface so calling gem_close on vmwgfx
> results in error. Call dumb destroy IOCTL in case have dumb buffer.
>
> Signed-off-by: Deepak Rawat
> ---
> lib/igt_fb.c | 5 -
> lib/igt_kms.c | 15 +++
> lib/ig
== Series Details ==
Series: series starting with [1/7] drm/i915: Missed interrupt simulation is no
more, tell the world
URL : https://patchwork.freedesktop.org/series/49255/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4778 -> Patchwork_10106 =
== Summary - FAILURE ==
Quoting Deepak Rawat (2018-09-06 01:03:48)
> For a Xorg bug vmwgfx has a kernel workaround which reset the value of
> mode::type. This will cause crtc state not to match what is expected.
Seems suspect, I think we need a stronger reason to accept iface
irregularities.
-Chris
__
Quoting Michal Wajdeczko (2018-08-29 22:10:40)
> Until now the GuC and HW engine class has been the same, which allowed
> us to use them interchangeable. But it is better to start doing the
> right thing and use the GuC definitions for the firmware interface.
>
> We also keep the same class id in
== Series Details ==
Series: series starting with [1/3] drm/i915/csr: keep firmware name and
required version together
URL : https://patchwork.freedesktop.org/series/49256/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/csr: keep firmware name and required version
Quoting Deepak Rawat (2018-09-06 01:03:49)
> Cairo surface creation will fail if stride of provided buffer is not
> same as expected by cairo. This fails for vmwgfx odd length framebuffer
> as in vmwgfx stride is always width * bpp.
>
> Signed-off-by: Deepak Rawat
> ---
> lib/igt_fb.c | 3 +++
>
Quoting Jani Nikula (2018-09-06 09:21:24)
> Having two separate if ladders gets increasingly hard to maintain. Put
> them together.
Does it even have to be an if-ladder? Something like
struct platform_requirements {
unsigned long platform_mask;
u32 required_version;
const c
Quoting Jani Nikula (2018-09-06 09:21:26)
> With i915.dmc_firmware_path="" it's obvious the intention is to disable
> CSR firmware loading. Bypass the firmware request altogether in this
> case, with more obvious debug logging.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/intel_cs
== Series Details ==
Series: series starting with [1/3] drm/i915/csr: keep firmware name and
required version together
URL : https://patchwork.freedesktop.org/series/49256/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4778 -> Patchwork_10107 =
== Summary - FAILURE ==
S
On Thu, 06 Sep 2018, Chris Wilson wrote:
> Quoting Jani Nikula (2018-09-06 09:21:24)
>> Having two separate if ladders gets increasingly hard to maintain. Put
>> them together.
>
> Does it even have to be an if-ladder? Something like
> struct platform_requirements {
> unsigned long platform_
On 06/09/2018 08:00, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-09-05 15:25:44)
From: Lionel Landwerlin
Verifies that the kernel programs slices correctly based by reading
the value of PWR_CLK_STATE register or MI_SET_PREDICATE on platforms
before Cannonlake.
v2: Add subslice tests (Li
Quoting Jani Nikula (2018-09-06 09:21:24)
> Having two separate if ladders gets increasingly hard to maintain. Put
> them together.
>
> Signed-off-by: Jani Nikula
> ---
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_csr.c | 54
>
On 05/09/2018 16:18, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-09-05 15:22:18)
From: Chris Wilson
We want to expose the ability to reconfigure the slices, subslice and
eu per context and per engine. To facilitate that, store the current
configuration on the context for each engine, whi
Quoting Jani Nikula (2018-09-06 09:21:25)
> Move max firmware size to the same if ladder with firmware name and
> required version. This allows us to detect the missing max size for a
> platform without actually loading the firmware, and makes the whole
> thing easier to maintain.
>
> We need to m
On 9/6/2018 5:12 AM, Rodrigo Vivi wrote:
The subject here is marked as icl, but the code seems to all platforms
what am I missing?
Sorry, my mistake. Will update it accordingly.
But also I didn't check spec yet on this particular case
The spec only mentions that the result lines should be gr
Quoting Chris Wilson (2018-09-06 10:08:37)
> Quoting Jani Nikula (2018-09-06 09:21:26)
> > With i915.dmc_firmware_path="" it's obvious the intention is to disable
> > CSR firmware loading. Bypass the firmware request altogether in this
> > case, with more obvious debug logging.
> >
> > Signed-off-
On 05/09/2018 16:21, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-09-05 15:22:19)
-static u32 make_rpcs(struct drm_i915_private *dev_priv,
-struct intel_sseu *ctx_sseu)
+u32 gen8_make_rpcs(struct drm_i915_private *dev_priv,
+ struct intel_sseu *req_sseu)
Am Mittwoch, 5. September 2018, 15:57:09 CEST schrieb Daniel Vetter:
> Remove the kerneldoc and EXPORT_SYMBOL which aren't used and really
> shouldn't ever be used by drivers directly.
>
> Unfortunately this means we need to move the set_writeback_fb function
> around to avoid a forward decl.
>
>
Quoting Tvrtko Ursulin (2018-09-06 10:31:21)
>
> On 06/09/2018 08:00, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-09-05 15:25:44)
> >> From: Lionel Landwerlin
> >>
> >> Verifies that the kernel programs slices correctly based by reading
> >> the value of PWR_CLK_STATE register or MI_SET_
On 05/09/2018 16:29, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-09-05 15:22:21)
From: Chris Wilson
Now this looks nothing like my first suggestion!
I think Tvrtko should stand ad the author of the final mechanism, I
think it is substantially different from the submission method first
Quoting Rodrigo Vivi (2018-09-05 19:42:28)
> On Wed, Sep 05, 2018 at 12:07:43PM +0300, Joonas Lahtinen wrote:
> > Quoting Rodrigo Vivi (2018-09-04 08:27:14)
> > > On Mon, Sep 03, 2018 at 01:00:39PM +0300, Imre Deak wrote:
> > > > On Mon, Aug 27, 2018 at 05:38:44PM -0700, Anusha Srivatsa wrote:
> >
Quoting Tvrtko Ursulin (2018-09-06 10:50:32)
>
> On 05/09/2018 16:29, Chris Wilson wrote:
> > I've a slight preference to setting to 0 then overwriting it afterwards.
>
> We can't use/validate it then. Alternative to just not clear it for ABI
> where it is not used? In other words would go away
On 05/09/2018 15:22, Tvrtko Ursulin wrote:
From: Lionel Landwerlin
If some of the contexts submitting workloads to the GPU have been
configured to shutdown slices/subslices, we might loose the NOA
configurations written in the NOA muxes.
One possible solution to this problem is to reprogram th
On 06/09/2018 10:50, Tvrtko Ursulin wrote:
On 05/09/2018 16:29, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-09-05 15:22:21)
From: Chris Wilson
Now this looks nothing like my first suggestion!
I think Tvrtko should stand ad the author of the final mechanism, I
think it is substantially
Quoting Lionel Landwerlin (2018-09-06 10:57:47)
> On 05/09/2018 15:22, Tvrtko Ursulin wrote:
> > From: Lionel Landwerlin
> >
> > If some of the contexts submitting workloads to the GPU have been
> > configured to shutdown slices/subslices, we might loose the NOA
> > configurations written in the N
Am Mittwoch, 5. September 2018, 20:15:09 CEST schrieb Daniel Vetter:
> - drmP.h is now fully split up.
> - vkms is happening (and will gain its own todo and docs under a new
> vkms.rst file real soon)
> - legacy cruft is completely hidden now, drm_vblank.c is split out
> from drm_irq.c now. I'v
On 06/09/2018 11:10, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-09-06 10:57:47)
On 05/09/2018 15:22, Tvrtko Ursulin wrote:
From: Lionel Landwerlin
If some of the contexts submitting workloads to the GPU have been
configured to shutdown slices/subslices, we might loose the NOA
configu
Quoting Lionel Landwerlin (2018-09-06 11:18:01)
> On 06/09/2018 11:10, Chris Wilson wrote:
> > Quoting Lionel Landwerlin (2018-09-06 10:57:47)
> >> On 05/09/2018 15:22, Tvrtko Ursulin wrote:
> >>> From: Lionel Landwerlin
> >>>
> >>> If some of the contexts submitting workloads to the GPU have been
On Thu, 06 Sep 2018, Chris Wilson wrote:
> Quoting Jani Nikula (2018-09-06 09:21:25)
>> Move max firmware size to the same if ladder with firmware name and
>> required version. This allows us to detect the missing max size for a
>> platform without actually loading the firmware, and makes the whol
== Series Details ==
Series: drm/i915: add LG eDP panel to quirk database
URL : https://patchwork.freedesktop.org/series/49251/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4776_full -> Patchwork_10105_full =
== Summary - FAILURE ==
Serious unknown changes coming with P
On 06/09/2018 11:22, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-09-06 11:18:01)
On 06/09/2018 11:10, Chris Wilson wrote:
Quoting Lionel Landwerlin (2018-09-06 10:57:47)
On 05/09/2018 15:22, Tvrtko Ursulin wrote:
From: Lionel Landwerlin
If some of the contexts submitting workloads t
As the result blocks for WM1-WM7 are always kept higher than the
level below the present level, make sure result lines are also higher
than the level below for WM1-WM7.
V3: Updated the commit message.
Signed-off-by: Karthik B S
---
drivers/gpu/drm/i915/intel_pm.c | 2 ++
1 file changed, 2 inser
Having two separate if ladders gets increasingly hard to maintain. Put
them together.
Reviewed-by: Chris Wilson
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_csr.c | 54
2 files changed, 23 insertions(
Move max firmware size to the same if ladder with firmware name and
required version. This allows us to detect the missing max size for a
platform without actually loading the firmware, and makes the whole
thing easier to maintain.
We need to move the power get earlier to allow for early return in
With i915.dmc_firmware_path="" it's obvious the intention is to disable
CSR firmware loading. Bypass the firmware request altogether in this
case, with more obvious debug logging.
v2: Use DRM_INFO for logging (Chris)
Reviewed-by: Chris Wilson
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/i915
On Thu, 06 Sep 2018, Petri Latvala wrote:
> On Wed, Sep 05, 2018 at 05:03:46PM -0700, Deepak Rawat wrote:
>> Add DRIVER_VMWGFX to represent vmwgfx device for running igt tests.
>>
>> Signed-off-by: Deepak Rawat
>> ---
>> lib/drmtest.c | 9 -
>> lib/drmtest.h | 3 +++
>> 2 files changed,
On Wed, Sep 05, 2018 at 01:12:00PM -0700, Radhakrishna Sripada wrote:
> Use the newly added "max bpc" connector property to limit pipe bpp.
>
> V3: Use drm_connector_state to access the "max bpc" property
> V4: Initialize the drm property, add suuport to DP(Ville)
> V5: Use the property in the con
Hi all,
The following changes tagged drm-intel-testing-2018-09-06:
drm-intel-next-2018-09-06:
UAPI Changes:
- GGTT coherency GETPARAM: GGTT has turned out to be non-coherent for some
platforms, which we've failed to communicate to userspace so far. SNA was
modified to do extra flushing on non
Quoting Zhenyu Wang (2018-09-04 06:01:54)
>
> Hi,
>
> Here's initial gvt-next for 4.20 with two optimization for
> guest context shadowing and command parser, and with W=1 build fixes.
Thanks, pulled this, but it had one merge conflict (in gvt/reg.h).
Please make sure the resolution I put in int
On 6 September 2018 at 10:40, Heiko Stuebner wrote:
> Am Mittwoch, 5. September 2018, 20:15:09 CEST schrieb Daniel Vetter:
>> - drmP.h is now fully split up.
>> - vkms is happening (and will gain its own todo and docs under a new
>> vkms.rst file real soon)
>> - legacy cruft is completely hidden
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/icl: Avoid Gen10 watermark
workarounds in Gen11 (rev2)
URL : https://patchwork.freedesktop.org/series/49170/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4780 -> Patchwork_10108 =
== Summary - SUCCESS ==
Hi all,
Disregard the previous message, and look at this tag instead :P
I'll still apply the gvt-next pull and do one more tag.
Regards, Joonas
The following changes tagged drm-intel-testing-2018-09-06-1:
drm-intel-next-2018-09-06-1:
UAPI Changes:
- GGTT coherency GETPARAM: GGTT has turned out
On 7/10/2018 3:10 PM, Madhav Chauhan wrote:
This patch setup voltage swing before enabling
combo PHY DDI (shared with DSI).
Note that DSI voltage swing programming is for
high speed data buffers. HW automatically handles
the voltage swing for the low power data buffers.
v2: Rebase
Signed-off-
== Series Details ==
Series: series starting with [v2,1/3] drm/i915/csr: keep firmware name and
required version together
URL : https://patchwork.freedesktop.org/series/49269/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/csr: keep firmware name and required versi
On Thu, 06 Sep 2018, Jani Nikula wrote:
>> The N value was computed by kernel driver that based on synchronous
>> clock mode. But only specific N value (0x8000) would be acceptable for
>> LG LP140WF6-SPM1 eDP panel which is running at asynchronous clock mode.
>
>As I wrote before, it's the DP so
== Series Details ==
Series: series starting with [v2,1/3] drm/i915/csr: keep firmware name and
required version together
URL : https://patchwork.freedesktop.org/series/49269/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4782 -> Patchwork_10109 =
== Summary - FAILURE ==
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/icl: Avoid Gen10 watermark
workarounds in Gen11 (rev2)
URL : https://patchwork.freedesktop.org/series/49170/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4780_full -> Patchwork_10108_full =
== Summary - F
> -Original Message-
> From: Daniel Vetter
> Sent: Wednesday, September 5, 2018 9:48 AM
> To: Li, Sun peng (Leo)
> Cc: DRI Development ; Intel Graphics
> Development ; Daniel Vetter
> ; Deucher, Alexander
> ; Wentland, Harry
> ; Grodzovsky, Andrey
> ; Cheng, Tony ; S,
> Shirish
> Subject
Exercise O(N^2) behaviour in reading the error state, and push it to the
extreme.
Reported-by: Jason Ekstrand
Signed-off-by: Chris Wilson
---
lib/meson.build | 1 +
tests/gem_exec_capture.c | 320 ++-
tests/intel-ci/blacklist.txt | 1 +
3 fil
On Thu, Sep 06, 2018 at 09:46:13AM +0300, Jani Nikula wrote:
> On Wed, 05 Sep 2018, Rodrigo Vivi wrote:
> > On Wed, Sep 05, 2018 at 12:07:43PM +0300, Joonas Lahtinen wrote:
> >> Was not the decision that we only gate the MODULE_FIRMWARE line until
> >> the firmware is in linux-firmware.git?
> >>
== Series Details ==
Series: igt/gem_exec_capture: Capture many, many objects
URL : https://patchwork.freedesktop.org/series/49288/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4782 -> IGTPW_1804 =
== Summary - FAILURE ==
Serious unknown changes coming with IGTPW_1804 a
If we fail to allocate an array for a large number of user requested
capture objects, reduce the array size and try to grab at least some of
the objects!
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gpu_error.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions
If the caller supplies more than 4G of objects and than one that has to
be in the low 4G, it is possible for the low 4G to be full before we
attempt to find room for the last object that must be there. As we don't
reorder the two types, every pass hits the same problem and we fail with
ENOSPC. Howe
== Series Details ==
Series: series starting with [1/2] drm/i915: Reorder execobject[] to insert
non-48b objects into the low 4G
URL : https://patchwork.freedesktop.org/series/49290/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
d1fd66113f8d drm/i915: Reorder execobject[] to i
== Series Details ==
Series: series starting with [1/2] drm/i915: Reorder execobject[] to insert
non-48b objects into the low 4G
URL : https://patchwork.freedesktop.org/series/49290/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Reorder execobject[] to insert non
== Series Details ==
Series: series starting with [1/2] drm/i915: Reorder execobject[] to insert
non-48b objects into the low 4G
URL : https://patchwork.freedesktop.org/series/49290/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4782 -> Patchwork_10110 =
== Summary - FAILU
From: Kai Chen
On GEN9LP, raise the RPS FUp Interrupt Limiter above softmax so that the
HW won't miss interrupt when requested max_freq is set back to RP0
value.
Signed-off-by: Kai Chen
---
drivers/gpu/drm/i915/intel_pm.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
d
== Series Details ==
Series: drm/i915: Raise RPS FUp Interrupt Limiter for GEN9LP above softmax
URL : https://patchwork.freedesktop.org/series/49293/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e67dcf0dbc2b drm/i915: Raise RPS FUp Interrupt Limiter for GEN9LP above softmax
-:
Quoting kai.c...@intel.com (2018-09-06 19:19:02)
> From: Kai Chen
>
> On GEN9LP, raise the RPS FUp Interrupt Limiter above softmax so that the
> HW won't miss interrupt when requested max_freq is set back to RP0
> value.
>
> Signed-off-by: Kai Chen
> ---
> drivers/gpu/drm/i915/intel_pm.c | 15
We should update GuC power domain states also when GuC submission
is disabled, otherwise GuC might complain or ignore our requests.
This seems to be required for all currently released GuC firmwares.
v2: it is only needed by pre-Gen11 firmwares
Signed-off-by: Michal Wajdeczko
Cc: John Spotswood
This will let the driver decide where GuC can be used
Signed-off-by: Michal Wajdeczko
---
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/intel_uc.c| 3 +++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i91
Given that we are now reasonably confident in our ability to detect and
reserve the stolen memory (physical memory reserved for graphics by the
BIOS) for ourselves on most machines, we can put it to use. In this
case, we need a page to hold the overlay registers.
On an i915g running MythTv, H Buus
The user parameters to put_image are not copied back to userspace
(DRM_IOW), and so we can modify the ioctl parameters (having already been
copied to a temporary kernel struct) directly and use those in place,
avoiding another temporary malloc and lots of manual copying.
Signed-off-by: Chris Wilso
== Series Details ==
Series: drm/i915: Raise RPS FUp Interrupt Limiter for GEN9LP above softmax
URL : https://patchwork.freedesktop.org/series/49293/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4782 -> Patchwork_10111 =
== Summary - SUCCESS ==
No regressions found.
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/guc: Update GuC power domain
states
URL : https://patchwork.freedesktop.org/series/49294/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4782 -> Patchwork_10112 =
== Summary - FAILURE ==
Serious unknown
== Series Details ==
Series: series starting with [1/2] drm/i915/overlay: Allocate physical
registers from stolen
URL : https://patchwork.freedesktop.org/series/49295/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
35d7413847d3 drm/i915/overlay: Allocate physical registers from
== Series Details ==
Series: series starting with [1/2] drm/i915/overlay: Allocate physical
registers from stolen
URL : https://patchwork.freedesktop.org/series/49295/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/overlay: Allocate physical registers from stolen
O
Quoting Tvrtko Ursulin (2018-09-05 15:22:15)
> From: Tvrtko Ursulin
>
> Updated series after continuing Lionel's work.
>
> Userspace for the feature is the media-driver project on GitHub. Please see
> https://github.com/intel/media-driver/pull/271/commits.
>
> No headline changes this time.
>
Quoting Chris Wilson (2018-09-06 20:33:35)
> Quoting Tvrtko Ursulin (2018-09-05 15:22:15)
> > From: Tvrtko Ursulin
> >
> > Updated series after continuing Lionel's work.
> >
> > Userspace for the feature is the media-driver project on GitHub. Please see
> > https://github.com/intel/media-driver/
== Series Details ==
Series: series starting with [1/2] drm/i915/overlay: Allocate physical
registers from stolen
URL : https://patchwork.freedesktop.org/series/49295/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4782 -> Patchwork_10113 =
== Summary - WARNING ==
Minor
== Series Details ==
Series: drm/i915: Raise RPS FUp Interrupt Limiter for GEN9LP above softmax
URL : https://patchwork.freedesktop.org/series/49293/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4782_full -> Patchwork_10111_full =
== Summary - SUCCESS ==
No regressions
48 bit ppgtt device configuration is really just extended address
range full ppgtt and may actually be something other than 48 bits.
Change USES_FULL_48BIT_PPGTT() to USES_FULL_4LVL_PPGTT() to better
describe that a 4 level walk table extended range PPGTT is being
used. Add a new device info field
Quoting Bob Paauwe (2018-09-06 21:04:09)
> @@ -1647,9 +1647,10 @@ static struct i915_hw_ppgtt *gen8_ppgtt_create(struct
> drm_i915_private *i915)
> ppgtt->vm.i915 = i915;
> ppgtt->vm.dma = &i915->drm.pdev->dev;
>
> - ppgtt->vm.total = USES_FULL_48BIT_PPGTT(i915) ?
> -
== Series Details ==
Series: drm/i915: Rename full ppgtt configuration to be more generic (rev2)
URL : https://patchwork.freedesktop.org/series/49021/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
6e4a835ff874 drm/i915: Make 48bit full ppgtt configuration generic (v2)
-:85: CHE
The hotplug detection routine of drm_helper_hpd_irq_event() can detect
changing of status of connector, but it can not detect changing of edid.
Following scenario requires detection of changing of edid.
1) plug display device to a connector
2) system suspend
3) unplug 1)'s display device and p
In order to use a detected edid on drm helper functions, it moves
a detected edid member to drm_connector structure from intel_connector
structure.
Signed-off-by: Gwan-gyeong Mun
---
drivers/gpu/drm/i915/intel_dp.c | 18 +-
drivers/gpu/drm/i915/intel_drv.h | 1 -
drivers/gpu/
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