On Mon, Jul 02, 2018 at 12:52:31PM +0300, Ville Syrjälä wrote:
> On Mon, Jul 02, 2018 at 09:46:23AM +0200, Daniel Vetter wrote:
> > On Thu, Jun 28, 2018 at 10:43:01PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä
> > >
> > > We only ever drive the panel with the fixed mode, hence we don't
On 07/02/2018 11:18 PM, Chris Wilson wrote:
Quoting Imre Deak (2018-07-02 14:57:56)
Work around the following boot time crash:
[ 10.456056] CPU: 1 PID: 220 Comm: systemd-udevd Tainted: GW
4.17.0-rc7-CI-CI_DRM_4040+ #182
[ 10.465828] Hardware name: Intel Corporation Ice Lake
On Mon, Jul 02, 2018 at 03:54:25PM +0200, Noralf Trønnes wrote:
> This the beginning of an API for in-kernel clients.
> First out is a way to get a framebuffer backed by a dumb buffer.
>
> Only GEM drivers are supported.
> The original idea of using an exported dma-buf was dropped because it
> als
On Mon, Jul 02, 2018 at 03:54:29PM +0200, Noralf Trønnes wrote:
> Add client callbacks and hook them up.
> Add a list of clients per drm_device.
>
> Signed-off-by: Noralf Trønnes
btw for reviewing it'd be simpler if you merge the 2 patches that add the
client library, avoids me having to jump ba
On 02.07.2018 17:16, StanLis wrote:
From: Stanislav Lisovskiy
PLANE_CTL_FORMAT_AYUV is already supported, according to hardware
specification.
v2: Edited commit message, removed redundant whitespaces.
v3: Fixed fallthrough logic for the format switch cases.
Signed-off-by: Stanislav Lisovskiy
live_gtt is a very slow test to run, simply because it tries to allocate
and use as much as the 48b address space as possibly can and in the
process will try to own all of the system memory. This leads to resource
exhaustion and CPU starvation; the latter impacts us when the NMI
watchdog declares a
On Tue, Jul 03, 2018 at 10:56:16AM +0800, Zhao Yakui wrote:
> Based on HW spec the fence reg on SNB+ is defined as 64-bit. Just follow
> the b-spec to use 64-bit read/write mode.
>
> Signed-off-by: Zhao Yakui
Please use git blame to understand why you've just re-introduced a bug
that took month
On Tue, Jul 03, 2018 at 10:56:17AM +0800, Zhao Yakui wrote:
> On VGPU scenario the read/write operation of fence_reg will be trapped
> by the GVT-g. And then gvt-g follows the HW spec to write the fence_reg.
> So it is unnecessary to read/write fence reg several times. This will help
> to reduce th
sysinfo() doesn't include all reclaimable memory. In particular it
excludes the majority of global_node_page_state(NR_FILE_PAGES),
reclaimable pages that are a copy of on-disk files It seems the only way
to obtain this counter is by parsing /proc/meminfo. For comparison,
check vm_enough_memory() wh
Quoting Daniel Vetter (2018-07-03 09:49:29)
> On Tue, Jul 03, 2018 at 10:56:16AM +0800, Zhao Yakui wrote:
> > Based on HW spec the fence reg on SNB+ is defined as 64-bit. Just follow
> > the b-spec to use 64-bit read/write mode.
> >
> > Signed-off-by: Zhao Yakui
>
> Please use git blame to unde
== Series Details ==
Series: drm/i915/selftests: Let other struct_mutex users have their gpu time
URL : https://patchwork.freedesktop.org/series/45810/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4418 -> Patchwork_9504 =
== Summary - WARNING ==
Minor unknown changes co
Quoting Daniel Vetter (2018-07-03 09:51:03)
> On Tue, Jul 03, 2018 at 10:56:17AM +0800, Zhao Yakui wrote:
> > On VGPU scenario the read/write operation of fence_reg will be trapped
> > by the GVT-g. And then gvt-g follows the HW spec to write the fence_reg.
> > So it is unnecessary to read/write fe
On 03/07/2018 09:56, Chris Wilson wrote:
sysinfo() doesn't include all reclaimable memory. In particular it
excludes the majority of global_node_page_state(NR_FILE_PAGES),
reclaimable pages that are a copy of on-disk files It seems the only way
to obtain this counter is by parsing /proc/meminfo.
This is to exercise DDB algorithm corner case where
DDB allocation was not happening properly for varying size plane.
Current DDB algorithm uses datarate based DDB division among
planes, but planes with same width require same DDB allocation
irrespective of their height.
To address this a Multipl
Quoting Daniel Vetter (2018-07-03 08:03:09)
> On Mon, Jul 02, 2018 at 12:52:31PM +0300, Ville Syrjälä wrote:
> > On Mon, Jul 02, 2018 at 09:46:23AM +0200, Daniel Vetter wrote:
> > > On Thu, Jun 28, 2018 at 10:43:01PM +0300, Ville Syrjala wrote:
> > > > From: Ville Syrjälä
> > > >
> > > > We only
Quoting Tomi Sarvela (2018-07-03 08:15:05)
> On 07/02/2018 11:18 PM, Chris Wilson wrote:
> > Quoting Imre Deak (2018-07-02 14:57:56)
> >> Work around the following boot time crash:
> >>
> >> [ 10.456056] CPU: 1 PID: 220 Comm: systemd-udevd Tainted: GW
> >> 4.17.0-rc7-CI-CI_DRM_40
On 03/07/2018 09:30, Chris Wilson wrote:
live_gtt is a very slow test to run, simply because it tries to allocate
and use as much as the 48b address space as possibly can and in the
process will try to own all of the system memory. This leads to resource
exhaustion and CPU starvation; the latter
On Tue, Jul 03, 2018 at 10:22:51AM +0100, Chris Wilson wrote:
> Quoting Tomi Sarvela (2018-07-03 08:15:05)
> > On 07/02/2018 11:18 PM, Chris Wilson wrote:
> > > Quoting Imre Deak (2018-07-02 14:57:56)
> > >> Work around the following boot time crash:
> > >>
> > >> [ 10.456056] CPU: 1 PID: 220 Com
== Series Details ==
Series: tests/kms_plane_multiple: DDB corner testcase (rev2)
URL : https://patchwork.freedesktop.org/series/45578/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4404 -> IGTPW_1525 =
== Summary - SUCCESS ==
No regressions found.
External URL:
http
Quoting Matthew Auld (2018-07-02 14:57:33)
> On 30 June 2018 at 10:05, Chris Wilson wrote:
> > If the whole object is already pinned by HW for use as scanout, we will
> > fail to move it to the mappable region and so must resort to using a
> > partial VMA covering the whole object.
> >
> > Bugzill
On Mon, 18 Jun 2018, Neil Armstrong wrote:
> Hi Lee,
>
> On 18/06/2018 09:44, Lee Jones wrote:
> > On Fri, 01 Jun 2018, Neil Armstrong wrote:
> >
> >> Having a 16 byte mkbp event size makes it possible to send CEC
> >> messages from the EC to the AP directly inside the mkbp event
> >> instead of
On Tue, Jul 03, 2018 at 10:05:28AM +0100, Chris Wilson wrote:
> Quoting Daniel Vetter (2018-07-03 09:51:03)
> > On Tue, Jul 03, 2018 at 10:56:17AM +0800, Zhao Yakui wrote:
> > > On VGPU scenario the read/write operation of fence_reg will be trapped
> > > by the GVT-g. And then gvt-g follows the HW
Quoting Tvrtko Ursulin (2018-07-03 10:27:47)
>
> On 03/07/2018 09:30, Chris Wilson wrote:
> > @@ -169,6 +177,8 @@ static int igt_ppgtt_alloc(void *arg)
> > ppgtt->vm.clear_range(&ppgtt->vm, 0, size);
> > }
> >
> > + schedule_locked(i915);
> > +
>
> Is it needed in this
== Series Details ==
Series: drm/i915/selftests: Let other struct_mutex users have their gpu time
URL : https://patchwork.freedesktop.org/series/45810/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4418_full -> Patchwork_9504_full =
== Summary - WARNING ==
Minor unknown
On Thu, Jun 14, 2018 at 08:56:25PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Just like with PIPESTAT, the edge triggered IIR on i965/g4x
> also causes problems for hotplug interrupts. To make sure
> we don't get the IIR port interrupt bit stuck low with the
> ISR bit high we must forc
Quoting Chris Wilson (2018-07-03 09:30:15)
> @@ -132,18 +140,18 @@ fake_dma_object(struct drm_i915_private *i915, u64 size)
>
> static int igt_ppgtt_alloc(void *arg)
> {
> - struct drm_i915_private *dev_priv = arg;
> + struct drm_i915_private *i915 = arg;
> struct i915_hw_pp
On 03/07/2018 10:52, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-07-03 10:27:47)
On 03/07/2018 09:30, Chris Wilson wrote:
@@ -169,6 +177,8 @@ static int igt_ppgtt_alloc(void *arg)
ppgtt->vm.clear_range(&ppgtt->vm, 0, size);
}
+ schedule_locked(i915);
+
Is
For a ppgtt that we are constructing, there is no struct_mutex
dependence so skip it. In the process, also ping the scheduler
frequently to try and avoid the NMI watchdog.
Suggested-by: Tvrtko Ursulin
References: https://bugs.freedesktop.org/show_bug.cgi?id=107094
Signed-off-by: Chris Wilson
Cc:
>-Original Message-
>From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
>Sent: Tuesday, July 3, 2018 5:01 PM
>To: Daniel Vetter ; Zhao, Yakui
>Cc: intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH v2 1/2] drm/i915: Use 64-bit to Read/Write
>fence reg on SNB+
>
>Quoting D
>-Original Message-
>From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
>Sent: Tuesday, July 3, 2018 4:51 PM
>To: Zhao, Yakui
>Cc: intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: write fence reg only once on
>VGPU
>
>On Tue,
From: Hang Yuan
This helps initramfs builder and other tools to know the full dependencies
of i915 and have gvt module loaded with i915.
v2: add condition and change to pre-dependency (Chris)
Signed-off-by: Hang Yuan
---
drivers/gpu/drm/i915/i915_pci.c | 6 ++
1 file changed, 6 insertions
Op 02-07-18 om 13:07 schreef Mahesh Kumar:
> This patch implements "verify_crc_source" callback function for
> rockchip drm driver.
>
> Changes since V1:
> - simplify the verification (Jani N)
>
> Signed-off-by: Mahesh Kumar
> Cc: dri-de...@lists.freedesktop.org
> Reviewed-by: Maarten Lankhorst
live_gtt is a very slow test to run, simply because it tries to allocate
and use as much as the 48b address space as possibly can and in the
process will try to own all of the system memory. This leads to resource
exhaustion and CPU starvation; the latter impacts us when the NMI
watchdog declares a
Op 02-07-18 om 13:07 schreef Mahesh Kumar:
> This patch implements "verify_crc_source" callback function for
> AMD drm driver.
>
> Signed-off-by: Mahesh Kumar
> Cc: dri-de...@lists.freedesktop.org
> Reviewed-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1
Op 02-07-18 om 13:07 schreef Mahesh Kumar:
> This patch implements "verify_crc_source" callback function for
> rcar drm driver.
>
> Signed-off-by: Mahesh Kumar
> Cc: dri-de...@lists.freedesktop.org
> Reviewed-by: Maarten Lankhorst
> ---
> drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 40
> ++
We want to do a complete pass before checking the timeout, but just in
case the pass is quite slow, touch the NMI watchdog to prevent a
false positive.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 8
1 file changed, 8 insertions(+)
Quoting hang.y...@linux.intel.com (2018-07-03 11:12:51)
> From: Hang Yuan
>
> This helps initramfs builder and other tools to know the full dependencies
> of i915 and have gvt module loaded with i915.
>
> v2: add condition and change to pre-dependency (Chris)
>
> Signed-off-by: Hang Yuan
> ---
== Series Details ==
Series: drm/i915/selftests: Drop struct_mutex around lowlevel pggtt allocation
URL : https://patchwork.freedesktop.org/series/45819/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4420 -> Patchwork_9505 =
== Summary - SUCCESS ==
No regressions found.
Hi Maarten,
Am Dienstag, 3. Juli 2018, 12:16:41 CEST schrieb Maarten Lankhorst:
> Op 02-07-18 om 13:07 schreef Mahesh Kumar:
> > This patch implements "verify_crc_source" callback function for
> > rockchip drm driver.
> >
> > Changes since V1:
> > - simplify the verification (Jani N)
> >
> > Si
On 03/07/2018 11:18, Chris Wilson wrote:
live_gtt is a very slow test to run, simply because it tries to allocate
and use as much as the 48b address space as possibly can and in the
process will try to own all of the system memory. This leads to resource
exhaustion and CPU starvation; the latter
== Series Details ==
Series: drm/i915: declare gvt as i915's soft dependency
URL : https://patchwork.freedesktop.org/series/45821/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4420 -> Patchwork_9506 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https
On 03/07/2018 11:07, Chris Wilson wrote:
For a ppgtt that we are constructing, there is no struct_mutex
dependence so skip it. In the process, also ping the scheduler
frequently to try and avoid the NMI watchdog.
Suggested-by: Tvrtko Ursulin
References: https://bugs.freedesktop.org/show_bug.cg
On 03/07/2018 11:25, Chris Wilson wrote:
We want to do a complete pass before checking the timeout, but just in
case the pass is quite slow, touch the NMI watchdog to prevent a
false positive.
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
---
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c |
Quoting Tvrtko Ursulin (2018-07-03 11:55:28)
>
> On 03/07/2018 11:07, Chris Wilson wrote:
> > For a ppgtt that we are constructing, there is no struct_mutex
> > dependence so skip it. In the process, also ping the scheduler
> > frequently to try and avoid the NMI watchdog.
> >
> > Suggested-by: T
Quoting Tvrtko Ursulin (2018-07-03 12:00:13)
>
> On 03/07/2018 11:25, Chris Wilson wrote:
> > We want to do a complete pass before checking the timeout, but just in
> > case the pass is quite slow, touch the NMI watchdog to prevent a
> > false positive.
> >
> > Signed-off-by: Chris Wilson
> > Cc
On Thu, May 03, 2018 at 04:26:02PM +0200, Daniel Vetter wrote:
> dma_fence_default_wait is the default now, same for the trivial
> enable_signaling implementation.
>
> Reviewed-by: Eric Anholt
> Signed-off-by: Daniel Vetter
> Cc: David Airlie
> Cc: Gerd Hoffmann
> Cc: virtualizat...@lists.linu
== Series Details ==
Series: tests/kms_plane_multiple: DDB corner testcase (rev2)
URL : https://patchwork.freedesktop.org/series/45578/
State : failure
== Summary ==
= CI Bug Log - changes from IGT_4531_full -> IGTPW_1525_full =
== Summary - FAILURE ==
Serious unknown changes coming with I
== Series Details ==
Series: drm/i915/selftests: Let other struct_mutex users have their gpu time
(rev2)
URL : https://patchwork.freedesktop.org/series/45810/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4420 -> Patchwork_9507 =
== Summary - WARNING ==
Minor unknown ch
Am 28.06.2018 um 11:58 schrieb Zhang, Jerry (Junwei):
On 06/22/2018 10:11 PM, Christian König wrote:
The caching of SGT's done by the DRM code is actually quite harmful and
should probably removed altogether in the long term.
Start by providing a separate DMA-buf export implementation in
amdgp
Am 28.06.2018 um 11:53 schrieb Zhang, Jerry (Junwei):
On 06/22/2018 10:11 PM, Christian König wrote:
Add function variants which can be called with the reservation lock
already held.
v2: reordered, add lockdep asserts, fix kerneldoc
Signed-off-by: Christian König
---
drivers/dma-buf/dma-buf
Am 25.06.2018 um 11:12 schrieb Daniel Vetter:
On Mon, Jun 25, 2018 at 10:22:31AM +0200, Daniel Vetter wrote:
On Fri, Jun 22, 2018 at 04:11:01PM +0200, Christian König wrote:
First step towards unpinned DMA buf operation.
I've checked the DRM drivers to potential locking of the reservation
obje
On Mon, Jun 11, 2018 at 11:02:57PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Adjust the EIR clearing to cope with the edge triggered IIR
> on i965/g4x. To guarantee an edge in the ISR master error bit
> we temporarily mask everything in EMR. As some of the EIR bits
> can't even be dir
On Mon, Jun 11, 2018 at 11:02:58PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> For whatever reason we only unmask and enable the master error
> interrut on gen4. With the EIR handling fixed let's do that
> on gen2/3 as well.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Imre Deak
>
== Series Details ==
Series: drm/i915/selftests: Touch the NMI watchdog inside a GTT pass
URL : https://patchwork.freedesktop.org/series/45823/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4421 -> Patchwork_9508 =
== Summary - SUCCESS ==
No regressions found.
Externa
Hi Lee,
On 03/07/2018 11:43, Lee Jones wrote:
> On Mon, 18 Jun 2018, Neil Armstrong wrote:
>
>> Hi Lee,
>>
>> On 18/06/2018 09:44, Lee Jones wrote:
>>> On Fri, 01 Jun 2018, Neil Armstrong wrote:
>>>
Having a 16 byte mkbp event size makes it possible to send CEC
messages from the EC to t
On Mon, Jul 02, 2018 at 10:00:35AM -0700, Sinclair Yeh wrote:
> Reviewed-by: Sinclair Yeh
>
> I assume you'll upstream this as part of your series?
Already pushed actually. In my haste I failed to realize I was
still missing an ack/rb for vmwgfx. Sorry about that.
>
> On Tue, Jun 26, 2018 at 1
>-Original Message-
>From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel Vetter
>Sent: Tuesday, July 3, 2018 5:52 PM
>To: Chris Wilson
>Cc: Daniel Vetter ; Zhao, Yakui ;
>intel-gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH v2 2/2] drm/i915: write fence reg
On Tue, Jul 03, 2018 at 01:46:44PM +0200, Christian König wrote:
> Am 25.06.2018 um 11:12 schrieb Daniel Vetter:
> > On Mon, Jun 25, 2018 at 10:22:31AM +0200, Daniel Vetter wrote:
> > > On Fri, Jun 22, 2018 at 04:11:01PM +0200, Christian König wrote:
> > > > First step towards unpinned DMA buf oper
On 03/07/2018 12:07, Chris Wilson wrote:
Quoting Tvrtko Ursulin (2018-07-03 12:00:13)
On 03/07/2018 11:25, Chris Wilson wrote:
We want to do a complete pass before checking the timeout, but just in
case the pass is quite slow, touch the NMI watchdog to prevent a
false positive.
Signed-off-by
This patch defines AUX lane registers for PORT_PCS_DW1,
PORT_TX_DW2, PORT_TX_DW4, PORT_TX_DW5 used during
dsi enabling.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/
Escape Clock is used for LP communication across the DSI
Link. To achieve the constant frequency of the escape clock
from the variable DPLL frequency output, a variable divider(M)
is needed. This patch programs the same.
v2: (Jani N) Don't end line with "(".
Signed-off-by: Madhav Chauhan
---
dr
This patch configures mode of operation for DSI
and enable DDI IO power by configuring power well.
v2: Use for_each_dsi_port() for power get (Jani N)
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_new.c | 23 +++
1 file changed, 23 insertions(+)
diff --git
This patch defines DSI_CLK_TIMING_PARAM, DPHY_CLK_TIMING_PARAM,
DSI_DATA_TIMING_PARAM, DPHY_DATA_TIMING_PARAM register used in
dphy programming.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 40
1 file changed, 40 insertions(+)
diff
This patch setup voltage swing before enabling
combo PHY DDI (shared with DSI).
Note that DSI voltage swing programming is for
high speed data buffers. HW automatically handles
the voltage swing for the low power data buffers.
v2: Rebase
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/in
This patch adds the new registers and corresponding bit definitions
which will be used for programming/enable DSI PLL.
v2: Review comments from Jani N
- Fix spaces while defining ICL_ESC_CLK_DIV_MASK
- Define shift and mask for bitfields.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani N
This patch set the loadgen select and latency optimization for
aux and transmit lanes of combo phy transmitters. It will be
used for MIPI DSI HS operations.
v2: Rebase
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_new.c | 38
1 file change
This register used to power down individual lanes for
DDI/DSI ports. Bitfields to power up/down various
combinations of lanes are also added in this patch.
v2: Review comments from Jani N
- Use override instead of "override" for bitfields
- Define mask for override bitfield
- Define PW
This patch defines DSI_TA_TIMING_PARAM and
DPHY_TA_TIMING_PARAM registers used in
dphy programming.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_re
This patch enables DDI buffer by writing to DDI_BUF_CTL
register and wait for DDI status to be *not idle* for a
port.
v2: Rebase
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_new.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i91
This patch defines DSI IO mode control register and it's bits
used while enabling IO power for DSI.
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gp
From ICELAKE platform onwards, new MIPI DSI IP controller is integrated to
GPU/Display Engine and same could be extended for future Intel platforms as
well.
DSI IP controller supports MIPI DSI 1.3 and DPHY 1.2 specification.
So, a new DSI driver has been added inside I915.
Given below patches ar
This patch programs D-PHY timing parameters for the
clock and data lane (in escape clocks) of DSI
controller (DSI port 0 and 1).
These programmed timings would be used by DSI Controller
to calculate link transition latencies of the data and
clock lanes.
Signed-off-by: Madhav Chauhan
---
drivers/
This patch defines DSI_T_INIT_MASTER register for DSI ports
0/1 which will be used in dphy programming.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
in
This patch defines transcoder function configuration
registers and its bitfields for both DSI ports.
Used while programming/enabling DSI transcoder.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 47 +
1 file changed, 47 insertions(+)
This patch programs the time (in escape clocks) to drive
the link in the initialization (i.e. LP-11) state.
v2: Rebase
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_new.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi_n
To save power, unused lanes should be powered
down using the bitfield of PORT_CL_DW10.
v2: Review comments from Jani N
- Put default label next to case 4
- Include the shifts in the macros
Signed-off-by: Madhav Chauhan
Reviewed-by: Jani Nikula
---
drivers/gpu/drm/i915/intel_dsi_new.c |
This patch programs DSI operation mode, pixel format,
BGR info, link calibration etc for the DSI transcoder.
This patch also extract BGR info of the DSI panel from
VBT and save it inside struct intel_dsi which used for
configuring DSI transcoder.
v2: Rebase
Signed-off-by: Madhav Chauhan
---
dri
This patch adds a helper function to retrieve DSI
transcoder for a given DSI port using newly defined
enum names for DSI transcoders.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_display.h | 6 --
drivers/gpu/drm/i915/intel_dsi_new.c | 9 +
2 files changed, 13 inserti
This patch programs D-PHY timing parameters for the
bus turn around flow(in escape clocks) only if dsi link
frequency <=800 MHz using DPHY_TA_TIMING_PARAM and its
identical register DSI_TA_TIMING_PARAM (inside DSI
Controller within the Display Core).
Signed-off-by: Madhav Chauhan
---
drivers/gpu
This patch adds _MMIO_DSI and _DSI_TRANS macros for accessing
DSI transcoder registers.
Credits-to: Jani N
Cc: Jani Nikula
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/dr
Am 03.07.2018 um 14:52 schrieb Daniel Vetter:
On Tue, Jul 03, 2018 at 01:46:44PM +0200, Christian König wrote:
Am 25.06.2018 um 11:12 schrieb Daniel Vetter:
On Mon, Jun 25, 2018 at 10:22:31AM +0200, Daniel Vetter wrote:
On Fri, Jun 22, 2018 at 04:11:01PM +0200, Christian König wrote:
First st
On 2018-07-03 06:19 AM, Maarten Lankhorst wrote:
Op 02-07-18 om 13:07 schreef Mahesh Kumar:
This patch implements "verify_crc_source" callback function for
AMD drm driver.
Signed-off-by: Mahesh Kumar
Cc: dri-de...@lists.freedesktop.org
Reviewed-by: Maarten Lankhorst
Acked-by: Leo Li
--
On 2018-07-02 07:07 AM, Mahesh Kumar wrote:
This patch make changes to allocate crc-entries buffer before
enabling CRC generation.
It moves all the failure check early in the function before setting
the source or memory allocation.
Now set_crc_source takes only two variable inputs, values_cnt w
Den 03.07.2018 09.46, skrev Daniel Vetter:
On Mon, Jul 02, 2018 at 03:54:29PM +0200, Noralf Trønnes wrote:
Add client callbacks and hook them up.
Add a list of clients per drm_device.
Signed-off-by: Noralf Trønnes
btw for reviewing it'd be simpler if you merge the 2 patches that add the
clie
On Tue, Jul 03, 2018 at 03:02:11PM +0200, Christian König wrote:
> Am 03.07.2018 um 14:52 schrieb Daniel Vetter:
> > On Tue, Jul 03, 2018 at 01:46:44PM +0200, Christian König wrote:
> > > Am 25.06.2018 um 11:12 schrieb Daniel Vetter:
> > > > On Mon, Jun 25, 2018 at 10:22:31AM +0200, Daniel Vetter w
Quoting Tvrtko Ursulin (2018-07-03 13:54:01)
>
> On 03/07/2018 12:07, Chris Wilson wrote:
> > Quoting Tvrtko Ursulin (2018-07-03 12:00:13)
> >>
> >> On 03/07/2018 11:25, Chris Wilson wrote:
> >>> We want to do a complete pass before checking the timeout, but just in
> >>> case the pass is quite sl
On Tue, Jul 03, 2018 at 03:07:50PM +0200, Noralf Trønnes wrote:
>
> Den 03.07.2018 09.46, skrev Daniel Vetter:
> > On Mon, Jul 02, 2018 at 03:54:29PM +0200, Noralf Trønnes wrote:
> > > Add client callbacks and hook them up.
> > > Add a list of clients per drm_device.
> > >
> > > Signed-off-by: No
Quoting Zhao, Yakui (2018-07-03 13:47:46)
>
> >-Original Message-
> >From: Daniel Vetter [mailto:daniel.vet...@ffwll.ch] On Behalf Of Daniel
> >Vetter
> >Sent: Tuesday, July 3, 2018 5:52 PM
> >To: Chris Wilson
> >Cc: Daniel Vetter ; Zhao, Yakui ;
> >intel-gfx@lists.freedesktop.org
> >Sub
On VGPU scenario the read/write operation of fence_reg will be trapped
by the GVT-g. Then gvt-g follows the HW spec to program the fence_reg.
And the gvt-g takes care of updating the fence reg correctly for any
trapped value of fence reg.
So it is unnecessary to read/write fence reg several times.
Am 03.07.2018 um 15:11 schrieb Daniel Vetter:
On Tue, Jul 03, 2018 at 03:02:11PM +0200, Christian König wrote:
Am 03.07.2018 um 14:52 schrieb Daniel Vetter:
On Tue, Jul 03, 2018 at 01:46:44PM +0200, Christian König wrote:
Am 25.06.2018 um 11:12 schrieb Daniel Vetter:
On Mon, Jun 25, 2018 at 1
Quoting Zhao Yakui (2018-07-03 14:27:47)
> On VGPU scenario the read/write operation of fence_reg will be trapped
> by the GVT-g. Then gvt-g follows the HW spec to program the fence_reg.
> And the gvt-g takes care of updating the fence reg correctly for any
> trapped value of fence reg.
>
> So it
== Series Details ==
Series: drm/i915/selftests: Drop struct_mutex around lowlevel pggtt allocation
URL : https://patchwork.freedesktop.org/series/45819/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4420_full -> Patchwork_9505_full =
== Summary - FAILURE ==
Serious unkn
== Series Details ==
Series: ICELAKE DSI DRIVER (rev2)
URL : https://patchwork.freedesktop.org/series/44823/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
2fb3a21077c4 drm/i915/icl: Define register for DSI PLL
5d1f14446c69 drm/i915/icl: Program DSI Escape clock Divider
-:40: WA
Starting from ICL or gen 11 we have a new DSI block which requires
completely different programming from the current implementation. Having
them in the same file would be confusing. Rename the current DSI and DSI
PLL implementation files as gen7_dsi.c and gen7_dsi_pll.c.
No functional changes.
Re
Avoid confusion with the functions to be added for the new gen 11 DSI
implementation by renaming the current DSI functions. While at it,
permutate the words in the function names to make them all start with
"gen7_dsi" or "gen7_dsi_pll".
Leave the static functions as-is for now; they could be renam
For a ppgtt that we are constructing, there is no struct_mutex
dependence so skip it. In the process, also ping the scheduler
frequently to try and avoid the NMI watchdog.
v2: gen6 requires struct_mutex to clean up (currently)
Suggested-by: Tvrtko Ursulin
References: https://bugs.freedesktop.org
>-Original Message-
>From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
>Sent: Tuesday, July 3, 2018 9:25 PM
>To: Zhao, Yakui ; Daniel Vetter
>Cc: intel-gfx@lists.freedesktop.org
>Subject: RE: [Intel-gfx] [PATCH v2 2/2] drm/i915: write fence reg only once on
>VGPU
>
>Quoting Zhao, Yakui
== Series Details ==
Series: ICELAKE DSI DRIVER (rev2)
URL : https://patchwork.freedesktop.org/series/44823/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/icl: Define register for DSI PLL
Okay!
Commit: drm/i915/icl: Program DSI Escape clock Divider
Okay!
Commit:
Quoting Zhao, Yakui (2018-07-03 14:58:31)
> >-Original Message-
> >From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> >Sent: Tuesday, July 3, 2018 9:25 PM
> >To: Zhao, Yakui ; Daniel Vetter
> >Cc: intel-gfx@lists.freedesktop.org
> >Subject: RE: [Intel-gfx] [PATCH v2 2/2] drm/i915: writ
> -Original Message-
> From: Nikula, Jani
> Sent: Tuesday, July 3, 2018 7:23 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani ; Chauhan, Madhav
> ; Daniel Vetter ; Chris
> Wilson
> Subject: [PATCH v2 1/2] drm/i915/dsi: rename the current DSI files based on
> generation
>
> Star
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