Quoting Patchwork (2018-06-14 23:53:30)
> == Series Details ==
>
> Series: drm/i915: Enable provoking vertex fix on Gen9+ systems.
> URL : https://patchwork.freedesktop.org/series/44781/
> State : failure
>
> == Summary ==
>
> = CI Bug Log - changes from CI_DRM_4322 -> Patchwork_9312 =
>
> ==
== Series Details ==
Series: series starting with [1/2] drm/i915/whl: Introducing Whiskey Lake
platform
URL : https://patchwork.freedesktop.org/series/44782/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4322_full -> Patchwork_9313_full =
== Summary - WARNING ==
Minor u
For each platform, we have a few registers that rewritten with multiple
values -- they are not part of a sequence, just different parts of a
masked register set at different times (e.g. platform and gen
workarounds). Consolidate these into a single register write to keep the
table compact.
While a
Quoting Chris Wilson (2018-06-15 08:16:01)
> Quoting Patchwork (2018-06-14 23:53:30)
> > == Series Details ==
> >
> > Series: drm/i915: Enable provoking vertex fix on Gen9+ systems.
> > URL : https://patchwork.freedesktop.org/series/44781/
> > State : failure
> >
> > == Summary ==
> >
> > = CI
For each platform, we have a few registers that rewritten with multiple
values -- they are not part of a sequence, just different parts of a
masked register set at different times (e.g. platform and gen
workarounds). Consolidate these into a single register write to keep the
table compact.
While a
We are restricted to the number of registers we can rewrite into a
single command by the packet length. If we have more registers than can
be fitted into a single packet, we therefore need to split the writes
into multiple packets.
Reported-by: Kenneth Graunke
Signed-off-by: Chris Wilson
Cc: Osc
We are restricted to the number of registers we can rewrite into a
single command by the packet length. If we have more registers than can
be fitted into a single packet, we therefore need to split the writes
into multiple packets.
Reported-by: Kenneth Graunke
Signed-off-by: Chris Wilson
Cc: Osc
Quoting Chris Wilson (2018-06-14 22:24:01)
> From: Jon Bloomfield
>
> Hook up the flags to allow read-only ppGTT mappings for gen8+
>
> v2: Include a selftest to check that writes to a readonly PTE are
> dropped
>
> Signed-off-by: Jon Bloomfield
> Signed-off-by: Chris Wilson
> Cc: Joonas Laht
Quoting Chris Wilson (2018-06-14 22:24:02)
> If the user has created a read-only object, they should not be allowed
> to circumvent the write protection by using a GGTT mmapping. Deny it.
>
> Also most machines do not support read-only GGTT PTEs, so again we have
> to reject attempted writes. Fort
On Thu, 14 Jun 2018, Dhinakaran Pandiyan wrote:
> On Thu, 2018-06-14 at 16:56 +, Nagaraju, Vathsala wrote:
>> + Ashutosh(VBT team) + maulik
>>
>> 209 is confirmed version on kbl both by vbt team (Maulik) and google,
>> so we had used it.
>>
>> DK's suggestion is
>> if ((bdb->version >= 20
drm-misc-next-fixes-2018-06-15:
- Fix possible race conditions while unplugging DRM device.
The following changes since commit fbecef131676c1d18e8e6b42c04e10dc49725e96:
drm/v3d: add CONFIG_MMU dependency (2018-05-30 12:15:18 -0700)
are available in the Git repository at:
git://anongit.freed
== Series Details ==
Series: series starting with [CI,1/2] drm/i915/icl: implement DVFS for ICL
URL : https://patchwork.freedesktop.org/series/44784/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4322_full -> Patchwork_9314_full =
== Summary - WARNING ==
Minor unknown ch
== Series Details ==
Series: drm/i915: Break workaround register emission into batches of 15
URL : https://patchwork.freedesktop.org/series/44808/
State : failure
== Summary ==
Applying: drm/i915: Break workaround register emission into batches of 15
Using index info to reconstruct a base tree
== Series Details ==
Series: drm/i915: Keep the ctx workarounds tightly packed
URL : https://patchwork.freedesktop.org/series/44807/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4323 -> Patchwork_9316 =
== Summary - SUCCESS ==
No regressions found.
External URL:
htt
== Series Details ==
Series: series starting with [1/2] drm/i915: Keep the ctx workarounds tightly
packed
URL : https://patchwork.freedesktop.org/series/44809/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Keep the ctx workarounds tightly packed
Okay!
Commit: dr
From: Jon Bloomfield
Hook up the flags to allow read-only ppGTT mappings for gen8+
v2: Include a selftest to check that writes to a readonly PTE are
dropped
v3: Don't duplicate cpu_check() as we can just reuse it, and even worse
don't wholesale copy the theory-of-operation comment from igt_ctx_e
Quoting Joonas Lahtinen (2018-06-15 09:08:54)
> Quoting Chris Wilson (2018-06-14 22:24:02)
> > If the user has created a read-only object, they should not be allowed
> > to circumvent the write protection by using a GGTT mmapping. Deny it.
> >
> > Also most machines do not support read-only GGTT P
== Series Details ==
Series: series starting with [1/5] drm/i915/gtt: Add read only pages to
gen8_pte_encode (rev2)
URL : https://patchwork.freedesktop.org/series/44776/
State : failure
== Summary ==
Applying: drm/i915/gtt: Add read only pages to gen8_pte_encode
Using index info to reconstruc
== Series Details ==
Series: series starting with [1/2] drm/i915: Keep the ctx workarounds tightly
packed
URL : https://patchwork.freedesktop.org/series/44809/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4323 -> Patchwork_9318 =
== Summary - SUCCESS ==
No regressions
From: Kenneth Graunke
The SF and clipper units mishandle the provoking vertex in some cases,
which can cause misrendering with shaders that use flat shaded inputs.
There are chicken bits in 3D_CHICKEN3 (for SF) and FF_SLICE_CHICKEN
(for the clipper) that work around the issue. These registers a
For each platform, we have a few registers that rewritten with multiple
values -- they are not part of a sequence, just different parts of a
masked register set at different times (e.g. platform and gen
workarounds). Consolidate these into a single register write to keep the
table compact.
While a
We are restricted to the number of registers we can write with a
single command by the packet length. If we have more registers than can
be fitted into a single packet, we therefore need to split the writes
into multiple packets.
Reported-by: Kenneth Graunke
Signed-off-by: Chris Wilson
Cc: Oscar
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/whl: Introducing Whiskey Lake
platform
URL : https://patchwork.freedesktop.org/series/44787/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4322_full -> Patchwork_9315_full =
== Summary - WARNING ==
Mino
On Thu, 14 Jun 2018, Rodrigo Vivi wrote:
> On Wed, Jun 13, 2018 at 09:55:38AM +0300, Jani Nikula wrote:
>> On Tue, 12 Jun 2018, Lucas De Marchi wrote:
>> > On Tue, Jun 12, 2018 at 3:15 AM Jani Nikula wrote:
>> >>
>> >> On Tue, 12 Jun 2018, Tvrtko Ursulin
>> >> wrote:
>> >> > On 12/06/2018 10:1
== Series Details ==
Series: series starting with [1/3] drm/i915: Keep the ctx workarounds tightly
packed
URL : https://patchwork.freedesktop.org/series/44811/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
7aec116d9abf drm/i915: Keep the ctx workarounds tightly packed
6deece3d
== Series Details ==
Series: series starting with [1/3] drm/i915: Keep the ctx workarounds tightly
packed
URL : https://patchwork.freedesktop.org/series/44811/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Keep the ctx workarounds tightly packed
Okay!
Commit: dr
As we want to be able to call i915_reset_engine and co from a softirq or
timer context, we need to be irqsafe at all times. So we have to forgo
the simple spin_lock_irq for the full spin_lock_irqsave.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem.c |
We can avoid the mmio read of the CSB pointers after reset based on the
knowledge that the HW always start writing at entry 0 in the CSB buffer.
We need to reset our CSB head tracking after GPU reset (and on
sanitization after resume) so that we are expecting to read from entry
0, hence we reset ou
As we want to be able to call i915_reset_engine and co from a softirq or
timer context, we need to be irqsafe at all times. So we have to forgo
the simple spin_lock_irq for the full spin_lock_irqsave.
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem.c |
== Series Details ==
Series: series starting with [1/3] drm/i915: Keep the ctx workarounds tightly
packed
URL : https://patchwork.freedesktop.org/series/44811/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4323 -> Patchwork_9320 =
== Summary - FAILURE ==
Serious unknown
== Series Details ==
Series: drm/i915: Be irqsafe inside reset
URL : https://patchwork.freedesktop.org/series/44814/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4323 -> Patchwork_9321 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://patchwork.f
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Be irqsafe inside reset
URL : https://patchwork.freedesktop.org/series/44815/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
88cc0c1c5c51 drm/i915: Be irqsafe inside reset
73a559896046 drm/i915/execlists: Reset
== Series Details ==
Series: series starting with [CI,1/2] drm/i915: Be irqsafe inside reset
URL : https://patchwork.freedesktop.org/series/44815/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4323 -> Patchwork_9322 =
== Summary - SUCCESS ==
No regressions found.
Exte
If client is smart or lucky enough to create a new context
after each hang, our context banning mechanism will never
catch up, and as a result of that it will be saved from
client banning. This can result in a never ending streak of
gpu hangs caused by bad or malicious client, preventing
access fro
Quoting Mika Kuoppala (2018-06-15 11:18:28)
> If client is smart or lucky enough to create a new context
> after each hang, our context banning mechanism will never
> catch up, and as a result of that it will be saved from
> client banning. This can result in a never ending streak of
> gpu hangs ca
Escape Clock is used for LP communication across the DSI
Link. To achieve the constant frequency of the escape clock
from the variable DPLL frequency output, a variable divider(M)
is needed. This patch programs the same.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/Makefile| 1
This patch configures mode of operation for DSI
and enable DDI IO power by configuring power well.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_new.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c
b/drivers/gp
From ICELAKE platform onwards, new MIPI DSI IP controller is integrated to
GPU/Display Engine and same could be extended for future Intel platforms as
well.
DSI IP controller supports MIPI DSI 1.3 and DPHY 1.2 specification.
So, a new DSI driver has been added inside I915.
Given below patches ar
This register used to power down individual lanes for
DDI/DSI ports. Bitfields to power up/down various
combinations of lanes are also added in this patch.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/d
To save power, unused lanes should be powered
down using the bitfield of PORT_CL_DW10.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_new.c | 44
1 file changed, 44 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c
b/drivers/
This patch defines AUX lane registers for PORT_PCS_DW1,
PORT_TX_DW2, PORT_TX_DW4, PORT_TX_DW5 used during
dsi enabling.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/
This patch defines DSI IO mode control register and it's bits
used while enabling IO power for DSI.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
inde
This patch set the loadgen select and latency optimization for
aux and transmit lanes of combo phy transmitters. It will be
used for MIPI DSI HS operations.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_new.c | 38
1 file changed, 38 insert
This patch adds the new registers and corresponding bit definitions
which will be used for programming/enable DSI PLL.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu
This patch setup voltage swing before enabling
combo PHY DDI (shared with DSI).
Note that DSI voltage swing programming is for
high speed data buffers. HW automatically handles
the voltage swing for the low power data buffers.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_new.
This patch defines DSI_T_INIT_MASTER register for DSI ports
0/1 which will be used in dphy programming.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
in
This patch programs D-PHY timing parameters for the
clock and data lane (in escape clocks) of DSI
controller (DSI port 0 and 1).
These programmed timings would be used by DSI Controller
to calculate link transition latencies of the data and
clock lanes.
Signed-off-by: Madhav Chauhan
---
drivers/
This patch enables DDI buffer by writing to DDI_BUF_CTL
register and wait for DDI status to be *not idle* for a
port.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_new.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi_
This patch defines DSI_CLK_TIMING_PARAM, DPHY_CLK_TIMING_PARAM,
DSI_DATA_TIMING_PARAM, DPHY_DATA_TIMING_PARAM register used in
dphy programming.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 40
1 file changed, 40 insertions(+)
diff
This patch adds a helper function to retrieve DSI
transcoder for a given DSI port using newly defined
enum names for DSI transcoders.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_display.h | 6 --
drivers/gpu/drm/i915/intel_dsi_new.c | 9 +
2 files changed, 13 inserti
This patch defines DSI_TA_TIMING_PARAM and
DPHY_TA_TIMING_PARAM registers used in
dphy programming.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_re
This patch adds _MMIO_DSI and _DSI_TRANS macros for accessing
DSI transcoder registers.
Credits-to: Jani N
Cc: Jani Nikula
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/dr
This patch programs the time (in escape clocks) to drive
the link in the initialization (i.e. LP-11) state.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/intel_dsi_new.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_dsi_new.c
b/driv
This patch programs DSI operation mode, pixel format,
BGR info, link calibration etc for the DSI transcoder.
This patch also extract BGR info of the DSI panel from
VBT and save it inside struct intel_dsi which used for
configuring DSI transcoder.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm
This patch programs D-PHY timing parameters for the
bus turn around flow(in escape clocks) only if dsi link
frequency <=800 MHz using DPHY_TA_TIMING_PARAM and its
identical register DSI_TA_TIMING_PARAM (inside DSI
Controller within the Display Core).
Signed-off-by: Madhav Chauhan
---
drivers/gpu
This patch defines transcoder function configuration
registers and its bitfields for both DSI ports.
Used while programming/enabling DSI transcoder.
Signed-off-by: Madhav Chauhan
---
drivers/gpu/drm/i915/i915_reg.h | 47 +
1 file changed, 47 insertions(+)
== Series Details ==
Series: drm/i915: Fix context ban and hang accounting for client
URL : https://patchwork.freedesktop.org/series/44820/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Fix context ban and hang accounting for client
-drivers/gpu/drm/i915/selftests
If client is smart or lucky enough to create a new context
after each hang, our context banning mechanism will never
catch up, and as a result of that it will be saved from
client banning. This can result in a never ending streak of
gpu hangs caused by bad or malicious client, preventing
access fro
== Series Details ==
Series: drm/i915: Fix context ban and hang accounting for client
URL : https://patchwork.freedesktop.org/series/44820/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4323 -> Patchwork_9323 =
== Summary - WARNING ==
Minor unknown changes coming with Pa
== Series Details ==
Series: ICELAKE DSI DRIVER
URL : https://patchwork.freedesktop.org/series/44823/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
c891c2690e61 drm/i915/icl: Define register for DSI PLL
034415bf480c drm/i915/icl: Program DSI Escape clock Divider
-:38: WARNING:F
== Series Details ==
Series: ICELAKE DSI DRIVER
URL : https://patchwork.freedesktop.org/series/44823/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/icl: Define register for DSI PLL
Okay!
Commit: drm/i915/icl: Program DSI Escape clock Divider
Okay!
Commit: drm/i91
Quoting Chris Wilson (2018-06-14 23:14:18)
> We should we have all the kinks worked out and full-ppgtt now works
> reliably on gen7 (Ivybridge, Valleyview/Baytrail and Haswell). If we can
> let userspace have full control over their own ppgtt, it makes softpinning
> far more effective, in turn maki
Quoting Chris Wilson (2018-06-14 23:14:19)
> We believe we have all the kinks worked out, even for the early
> Valleyview devices, for whom we currently disable all ppgtt.
>
> References: 62942ed7279d ("drm/i915/vlv: disable PPGTT on early revs v3")
> Signed-off-by: Chris Wilson
> Cc: Ville Syrjä
Chris Wilson writes:
> For each platform, we have a few registers that rewritten with multiple
> values -- they are not part of a sequence, just different parts of a
> masked register set at different times (e.g. platform and gen
> workarounds). Consolidate these into a single register write to k
== Series Details ==
Series: ICELAKE DSI DRIVER
URL : https://patchwork.freedesktop.org/series/44823/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4323 -> Patchwork_9324 =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9324 need to be verified
man
Quoting Mika Kuoppala (2018-06-15 12:29:23)
> Chris Wilson writes:
>
> > For each platform, we have a few registers that rewritten with multiple
> > values -- they are not part of a sequence, just different parts of a
> > masked register set at different times (e.g. platform and gen
> > workaroun
Chris Wilson writes:
> For each platform, we have a few registers that rewritten with multiple
> values -- they are not part of a sequence, just different parts of a
> masked register set at different times (e.g. platform and gen
> workarounds). Consolidate these into a single register write to k
== Series Details ==
Series: drm/i915: Fix context ban and hang accounting for client (rev2)
URL : https://patchwork.freedesktop.org/series/44820/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Fix context ban and hang accounting for client
-drivers/gpu/drm/i915/se
== Series Details ==
Series: drm/i915: Keep the ctx workarounds tightly packed
URL : https://patchwork.freedesktop.org/series/44807/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4323_full -> Patchwork_9316_full =
== Summary - WARNING ==
Minor unknown changes coming with
For each platform, we have a few registers that are rewritten with
different values -- they are not part of a sequence, just different parts
of a masked register set at different times (e.g. platform and gen
workarounds). Consolidate these into a single register write to keep the
table compact, imp
== Series Details ==
Series: drm/i915: Fix context ban and hang accounting for client (rev2)
URL : https://patchwork.freedesktop.org/series/44820/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4323 -> Patchwork_9325 =
== Summary - WARNING ==
Minor unknown changes coming
== Series Details ==
Series: drm/i915: Keep the ctx workarounds tightly packed (rev2)
URL : https://patchwork.freedesktop.org/series/44807/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4323 -> Patchwork_9326 =
== Summary - SUCCESS ==
No regressions found.
External UR
== Series Details ==
Series: series starting with [1/2] drm/i915: Keep the ctx workarounds tightly
packed
URL : https://patchwork.freedesktop.org/series/44809/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4323_full -> Patchwork_9318_full =
== Summary - WARNING ==
Minor
As we want to compare a templated tiling pattern against the target_bo,
we need to know that the swizzling is compatible. Or else the two
tiling pattern may differ due to underlying page address that we cannot
know, and so the test may sporadically fail.
References: https://bugs.freedesktop.org/sh
Chris Wilson writes:
> Quoting Mika Kuoppala (2018-06-15 11:18:28)
>> If client is smart or lucky enough to create a new context
>> after each hang, our context banning mechanism will never
>> catch up, and as a result of that it will be saved from
>> client banning. This can result in a never en
On Fri, Jun 15, 2018 at 02:29:08PM +0300, Joonas Lahtinen wrote:
> Quoting Chris Wilson (2018-06-14 23:14:19)
> > We believe we have all the kinks worked out, even for the early
> > Valleyview devices, for whom we currently disable all ppgtt.
> >
> > References: 62942ed7279d ("drm/i915/vlv: disabl
Quoting Ville Syrjälä (2018-06-15 14:54:39)
> On Fri, Jun 15, 2018 at 02:29:08PM +0300, Joonas Lahtinen wrote:
> > Quoting Chris Wilson (2018-06-14 23:14:19)
> > > We believe we have all the kinks worked out, even for the early
> > > Valleyview devices, for whom we currently disable all ppgtt.
> >
== Series Details ==
Series: drm/i915: Be irqsafe inside reset
URL : https://patchwork.freedesktop.org/series/44814/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4323_full -> Patchwork_9321_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9321_
On Fri, Jun 15, 2018 at 02:57:32PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjälä (2018-06-15 14:54:39)
> > On Fri, Jun 15, 2018 at 02:29:08PM +0300, Joonas Lahtinen wrote:
> > > Quoting Chris Wilson (2018-06-14 23:14:19)
> > > > We believe we have all the kinks worked out, even for the early
>
While debugging we may want to examine params passed to GuC.
Print them all if config I915_DEBUG_GUC is enabled.
Signed-off-by: Michal Wajdeczko
Cc: Daniele Ceraolo Spurio
Cc: Michel Thierry
---
drivers/gpu/drm/i915/intel_guc.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/g
== Series Details ==
Series: drm/i915/guc: Print CTL params passed to Guc
URL : https://patchwork.freedesktop.org/series/44834/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4325 -> Patchwork_9327 =
== Summary - SUCCESS ==
No regressions found.
External URL:
https://
Atm we're zeroing out fields in MG_PLL_BIAS and MG_PLL_TDC_COLDST_BIAS
if refclk is 38.4MHz, whereas the spec tells us to preserve them.
Although the calculated values mostly match the register defaults even
for the 38.4MHz case, there are some differences wrt. what BIOS
programs (I noticed at leas
Some MG PLL registers have fields that need to be preserved at their HW
default or BIOS programmed values. So make sure we preserve them.
Cc: Vandita Kulkarni
Cc: Paulo Zanoni
Cc: James Ausmus
Signed-off-by: Imre Deak
Reviewed-by: James Ausmus
---
drivers/gpu/drm/i915/i915_reg.h | 13 +
== Series Details ==
Series: drm/i915: Enable provoking vertex fix on Gen9+ systems.
URL : https://patchwork.freedesktop.org/series/44781/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4325 -> Patchwork_9328 =
== Summary - FAILURE ==
Serious unknown changes coming with P
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Fix MG PLL setup when refclk
is 38.4MHz
URL : https://patchwork.freedesktop.org/series/44836/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b74cd00bcd1f drm/i915/icl: Fix MG PLL setup when refclk is 38.4MHz
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Fix MG PLL setup when refclk
is 38.4MHz
URL : https://patchwork.freedesktop.org/series/44836/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4325 -> Patchwork_9329 =
== Summary - WARNING ==
Minor unkno
If the user has created a read-only object, they should not be allowed
to circumvent the write protection by using a GGTT mmapping. Deny it.
Also most machines do not support read-only GGTT PTEs, so again we have
to reject attempted writes. Fortunately, this is known a priori, so we
can at least r
Exercise new API to probe that the userptr range is valid (backed by
struct pages and not pfn) or to populate the userptr upon creation (by
calling get_user_pages() on the range).
Signed-off-by: Chris Wilson
Cc: Tvrtko Ursulin
Cc: Michał Winiarski
---
tests/gem_userptr_blits.c | 140 ++
Setup a userptr object that only has a read-only mapping back to a file
store (memfd). Then attempt to write into that mapping using the GPU and
assert that those writes do not land (while also writing via a writable
userptr mapping into the same memfd to verify that the GPU is working!)
Signed-of
== Series Details ==
Series: series starting with [1/5] drm/i915/gtt: Add read only pages to
gen8_pte_encode (rev3)
URL : https://patchwork.freedesktop.org/series/44776/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0358c9fd1b9b drm/i915/gtt: Add read only pages to gen8_pte_en
== Series Details ==
Series: series starting with [1/5] drm/i915/gtt: Add read only pages to
gen8_pte_encode (rev3)
URL : https://patchwork.freedesktop.org/series/44776/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915/gtt: Add read only pages to gen8_pte_encode
Okay
== Series Details ==
Series: series starting with [1/5] drm/i915/gtt: Add read only pages to
gen8_pte_encode (rev3)
URL : https://patchwork.freedesktop.org/series/44776/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4325 -> Patchwork_9330 =
== Summary - WARNING ==
Minor
On 6/15/2018 1:59 AM, Chris Wilson wrote:
For each platform, we have a few registers that rewritten with multiple
values -- they are not part of a sequence, just different parts of a
masked register set at different times (e.g. platform and gen
workarounds). Consolidate these into a single regi
Quoting Oscar Mateo Lozano (2018-06-15 17:01:37)
>
>
> On 6/15/2018 1:59 AM, Chris Wilson wrote:
> > For each platform, we have a few registers that rewritten with multiple
> > values -- they are not part of a sequence, just different parts of a
> > masked register set at different times (e.g. pl
On Fri, Jun 15, 2018 at 09:01:37AM -0700, Oscar Mateo Lozano wrote:
>
>
> On 6/15/2018 1:59 AM, Chris Wilson wrote:
> > For each platform, we have a few registers that rewritten with multiple
> > values -- they are not part of a sequence, just different parts of a
> > masked register set at diffe
Quoting Ville Syrjälä (2018-06-15 17:19:14)
> On Fri, Jun 15, 2018 at 09:01:37AM -0700, Oscar Mateo Lozano wrote:
> >
> >
> > On 6/15/2018 1:59 AM, Chris Wilson wrote:
> > > For each platform, we have a few registers that rewritten with multiple
> > > values -- they are not part of a sequence, ju
On Fri, Jun 15, 2018 at 05:22:40PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjälä (2018-06-15 17:19:14)
> > On Fri, Jun 15, 2018 at 09:01:37AM -0700, Oscar Mateo Lozano wrote:
> > >
> > >
> > > On 6/15/2018 1:59 AM, Chris Wilson wrote:
> > > > For each platform, we have a few registers that r
From: Oscar Mateo
Once upon a time, we tried to apply workarounds for registers that lived
inside the context image for every new context. That meant emitting LRI
commands soon after each context was created.
Nowadays, we have a single golden context that gets used as a master
template for futur
From: Oscar Mateo
Once upon a time, we tried to apply workarounds for registers that lived
inside the context image for every new context. That meant emitting LRI
commands soon after each context was created.
Nowadays, we have a single golden context that gets used as a master
template for futur
From: Kenneth Graunke
The SF and clipper units mishandle the provoking vertex in some cases,
which can cause misrendering with shaders that use flat shaded inputs.
There are chicken bits in 3D_CHICKEN3 (for SF) and FF_SLICE_CHICKEN
(for the clipper) that work around the issue. These registers a
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