[Intel-gfx] Haswell full-ppgtt

Found the magic barrier required to fix the last remaining stress test, so as far as I can tell, this is ready to go: full-ppgtt for gen7, ivb/hsw/vlv. -Chris ___ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailm

[Intel-gfx] [PATCH 05/17] drm/i915/gtt: Invalidate GGTT caches after writing the gen6 page directories

When we update the gen6 ppgtt page directories, we do so by writing the new address into a reserved slot in the GGTT. It appears that when the GPU reads that entry from the gsm, it uses its small cache and that we need to invalidate that cache after writing. We don't see an issue currently as we pr

[Intel-gfx] [PATCH 02/17] drm/i915/ringbuffer: Brute force context restore

An issue encountered with switching mm on gen7 is that the GPU likes to hang (with the VS unit busy) when told to force restore the current context. We can simply workaround this by substituting the MI_FORCE_RESTORE flag with a round-trip through the kernel_context, forcing the context to be saved

[Intel-gfx] [PATCH 07/17] drm/i915/gtt: Subclass gen6_hw_ppgtt

The legacy gen6 ppgtt needs a little more hand holding than gen8+, and so requires a larger structure. As I intend to make this slightly more complicated in the future, separate the gen6 from the core gen8 hw struct by subclassing. This patch moves the gen6 only features out to gen6_hw_ppgtt and pi

[Intel-gfx] [PATCH 11/17] drm/i915/gtt: Lazily allocate page directories for gen7

As we were only supporting aliasing_ppgtt on gen7 for some time, we saved a few checks by preallocating the page directories on creation. However, since we need 2MiB of page directories for each ppgtt, to support arbitrary numbers of user contexts, we need to be more prudent in our allocations, and

[Intel-gfx] [PATCH 14/17] drm/i915/gtt: Cache the PTE encoding of the scratch page

As the most frequent PTE encoding is for the scratch page, cache it upon creation. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Matthew Auld Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_gtt.c | 20 ++-- drivers/gpu/drm/i915/i915_gem_gtt

[Intel-gfx] [PATCH 15/17] drm/i915/gtt: Reduce a pair of runtime asserts

We can stop asserting using WARN_ON as given sufficient CI coverage, we can rely on using GEM_BUG_ON() to catch problems before merging. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Matthew Auld Reviewed-by: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-

[Intel-gfx] [PATCH 12/17] drm/i915/gtt: Free unused page tables on unbind the context

As we cannot reliably change used page tables while the context is active, the earliest opportunity we have to recover excess pages is when the context becomes idle. So whenever we unbind the context (it must be idle, and indeed being evicted) free the unused ptes. Signed-off-by: Chris Wilson Cc:

[Intel-gfx] [PATCH 16/17] drm/i915/gtt: Skip clearing the GGTT under gen6+ full-ppgtt

If we know that the user cannot access the GGTT, by virtue of having a segregated memory area, we can skip clearing the unused entries as they cannot be accessed. Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Matthew Auld --- drivers/gpu/drm/i915/i915_gem_gtt.c | 4 +++

[Intel-gfx] [PATCH 17/17] drm/i915/gtt: Enable full-ppgtt by default everywhere

We should we have all the kinks worked out and full-ppgtt now works reliably on gen7 (Ivybridge, Valleyview/Baytrail and Haswell). If we can let userspace have full control over their own ppgtt, it makes softpinning far more effective, in turn making GPU dispatch far more efficient and more secure

[Intel-gfx] [PATCH 06/17] drm/i915/ringbuffer: Serialize load of PD_DIR

After triggering the mm switch with a load of PD_DIR, which may be deferred unto the MI_SET_CONTEXT on rcs, serialise the next commands with that load by posting a read of PD_DIR (or else those subsequent commands may access the stale page tables). Signed-off-by: Chris Wilson Cc: Joonas Lahtinen

[Intel-gfx] [PATCH 10/17] drm/i915/gtt: Only keep gen6 page directories pinned while active

In order to be able to evict the gen6 ppgtt, we have to unpin it at some point. We can simply use our context activity tracking to know when the ppgtt is no longer in use by hardware, and so only keep it pinned while being used a request. For the kernel_context (and thus aliasing_ppgtt), it remain

[Intel-gfx] [PATCH 01/17] drm/i915: Apply batch location restrictions before pinning

We special case the position of the batch within the GTT to prevent negative self-relocation deltas from underflowing. However, that restriction is being applied after a trial pin of the batch in its current position. Thus we are not rejecting an invalid location if the batch has been before, leadi

[Intel-gfx] [PATCH 03/17] drm/i915/ringbuffer: Fix context restore upon reset

The discovery with trying to enable full-ppgtt was that we were completely failing to the load both the mm and context following the reset. Although we were performing mmio to set the PP_DIR (per-process GTT) and CCID (context), these were taking no effect (the assumption was that this would trigge

[Intel-gfx] [PATCH 08/17] drm/i915/gtt: Onionify error handling for gen6_ppgtt_create

Pull the empty stubs together into the top level gen6_ppgtt_create, and tear each one down on error in proper onion order (rather than use Joonas' pet hate of calling the cleanup function in indeterminable state). Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Matthew Aul

[Intel-gfx] [PATCH 09/17] drm/i915/gtt: Make gen6 page directories evictable

Currently all page directories are bound at creation using an unevictable node in the GGTT. This severely limits us as we cannot remove any inactive ppgtt for new contexts, or under aperture pressure. To fix this we need to make the page directory into a first class and unbindable vma. Hence, the c

[Intel-gfx] [PATCH 13/17] drm/i915/gtt: Skip initializing PT with scratch if full

If we will completely overwrite the PT with PTEs for the object, we can forgo filling it with scratch entries. References: 14826673247e ("drm/i915: Only initialize partially filled pagetables") Signed-off-by: Chris Wilson Cc: Joonas Lahtinen Cc: Mika Kuoppala Cc: Matthew Auld Reviewed-by: Mat

[Intel-gfx] [PATCH 04/17] drm/i915: Wrap around the tail offset before setting ring->tail

The HW only accepts offsets within ring->size, and fails peculiarly if the RING_HEAD or RING_TAIL is set to ring->size. Therefore whenever we set ring->head/ring->tail we want to make sure it is within value (using intel_ring_wrap()). v2: Double check execlists as well Signed-off-by: Chris Wilson

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/17] drm/i915: Apply batch location restrictions before pinning

== Series Details == Series: series starting with [01/17] drm/i915: Apply batch location restrictions before pinning URL : https://patchwork.freedesktop.org/series/44539/ State : warning == Summary == $ dim checkpatch origin/drm-tip 17cecb85f303 drm/i915: Apply batch location restrictions bef

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [01/17] drm/i915: Apply batch location restrictions before pinning

== Series Details == Series: series starting with [01/17] drm/i915: Apply batch location restrictions before pinning URL : https://patchwork.freedesktop.org/series/44539/ State : warning == Summary == $ dim sparse origin/drm-tip Commit: drm/i915: Apply batch location restrictions before pinni

[Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [01/17] drm/i915: Apply batch location restrictions before pinning

== Series Details == Series: series starting with [01/17] drm/i915: Apply batch location restrictions before pinning URL : https://patchwork.freedesktop.org/series/44539/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4298 -> Patchwork_9252 = == Summary - SUCCESS == No r

[Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [01/17] drm/i915: Apply batch location restrictions before pinning

== Series Details == Series: series starting with [01/17] drm/i915: Apply batch location restrictions before pinning URL : https://patchwork.freedesktop.org/series/44539/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4298_full -> Patchwork_9252_full = == Summary - WARNING

Re: [Intel-gfx] [PATCH v7 0/6] Add ChromeOS EC CEC Support

On Fri, 08 Jun 2018, Hans Verkuil wrote: > On 08/06/18 10:17, Neil Armstrong wrote: > > On 08/06/2018 09:53, Hans Verkuil wrote: > >> On 06/01/2018 10:19 AM, Neil Armstrong wrote: > >>> Hi All, > >>> > >>> The new Google "Fizz" Intel-based ChromeOS device is gaining CEC support > >>> through it's E