The idea was to try and let the existing tasklet run to completion
before we began the reset, but it involves a racy check against anything
else that tries to run the tasklet. Rather than acknowledge and ignore
the race, let it be and don't try and be too clever.
The tasklet will resume execution
Catch up with the inflight CSB events, after disabling the tasklet
before deciding which request was truly guilty of hanging the GPU.
Signed-off-by: Chris Wilson
Cc: Michał Winiarski
CC: Michel Thierry
Cc: Jeff McGee
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/in
In preparation to more carefully handling incomplete preemption during
reset by execlists, we move the existing code wholesale to the backends
under a couple of new reset vfuncs.
Signed-off-by: Chris Wilson
Cc: Michał Winiarski
CC: Michel Thierry
Cc: Jeff McGee
Reviewed-by: Jeff McGee
---
dr
Pull the CSB event processing into its own routine so that we can reuse
it during reset to flush any missed interrupts/events.
Signed-off-by: Chris Wilson
Cc: Michał Winiarski
CC: Michel Thierry
Cc: Jeff McGee
Cc: Tvrtko Ursulin
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/intel_lrc
We cannot call kthread_park() from softirq context, so let's avoid it
entirely during the reset. We wanted to suspend the signaler so that it
would not mark a request as complete at the same time as we marked it as
being in error. Instead of parking the signaling, stop the engine from
advancing so
When setting up reset, we may need to recursively prepare an engine. In
which case we should only synchronously flush the tasklets on the outer
most call, the inner calls will then be inside an atomic section where
the tasklet will never be run (and so the sync will never complete).
Signed-off-by:
In the next patch, we will make the execlists reset prepare callback
take into account preemption by flushing the context-switch handler.
This is not applicable to the GuC submission backend, so split the two
into their own backend callbacks.
Signed-off-by: Chris Wilson
Cc: Michał Winiarski
CC:
As a complement to inject_preempt_context(), follow up with the function
to handle its completion. This will be useful should we wish to extend
the duties of the preempt-context for execlists.
v2: And do the same for the guc.
Signed-off-by: Chris Wilson
Cc: Jeff McGee
Cc: Michał Winiarski
Revi
On 2018-05-14 10:05 PM, Manasi Navare wrote:
> From: Gaurav K Singh
>
> This defines all the DSC parameters as per the VESA DSC spec
> that will be required for DSC encoder/decoder
>
> v2: Define this struct in DRM (From Manasi)
> * Changed the data types to u8/u16 instead of unsigned longs (Man
Hi Ville,
On 16/05/2018 16:07, Ville Syrjälä wrote:
> On Wed, May 16, 2018 at 09:40:17AM +0200, Neil Armstrong wrote:
>> On 16/05/2018 09:31, Neil Armstrong wrote:
>>> Hi Ville,
>>>
>>> On 15/05/2018 17:35, Ville Syrjälä wrote:
On Tue, May 15, 2018 at 04:42:19PM +0200, Neil Armstrong wrote:
>
== Series Details ==
Series: series starting with [CI,1/8] drm/i915: Remove tasklet flush before
disable
URL : https://patchwork.freedesktop.org/series/43279/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
65dc7678895f drm/i915: Remove tasklet flush before disable
4ec12cf75d13
== Series Details ==
Series: drm/i915: Enable fastset by default, except on initial modeset
URL : https://patchwork.freedesktop.org/series/43248/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4191_full -> Patchwork_9014_full =
== Summary - FAILURE ==
Serious unknown chan
Use new return type vm_fault_t for fault handler. For
now, this is just documenting that the function returns
a VM_FAULT value rather than an errno. Once all instances
are converted, vm_fault_t will become a distinct type.
commit 1c8f422059ae ("mm: change return type to vm_fault_t")
Fixed one che
Quoting Souptick Joarder (2018-05-16 20:12:20)
> Use new return type vm_fault_t for fault handler. For
> now, this is just documenting that the function returns
> a VM_FAULT value rather than an errno. Once all instances
> are converted, vm_fault_t will become a distinct type.
>
> commit 1c8f42205
== Series Details ==
Series: series starting with [CI,1/8] drm/i915: Remove tasklet flush before
disable
URL : https://patchwork.freedesktop.org/series/43279/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4193 -> Patchwork_9022 =
== Summary - WARNING ==
Minor unknown ch
Hi Dave,
A few more fixes this week, one going to stable.
drm-misc-fixes-2018-05-16:
- core: Fix regression in dev node offsets (Haneen)
- vc4: Fix memory leak on driver close (Eric)
- dumb-buffers: Prevent overflow in DIV_ROUND_UP() (Dan)
Cc: Haneen Mohammed
Cc: Eric Anholt
Cc: Dan Carpenter
== Series Details ==
Series: gpu: drm: i915: Change return type to vm_fault_t (rev4)
URL : https://patchwork.freedesktop.org/series/41893/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: gpu: drm: i915: Change return type to vm_fault_t
-O:drivers/gpu/drm/i915/i915_gem.c:2080:
== Series Details ==
Series: gpu: drm: i915: Change return type to vm_fault_t (rev4)
URL : https://patchwork.freedesktop.org/series/41893/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4193 -> Patchwork_9023 =
== Summary - WARNING ==
Minor unknown changes coming with Pat
On 05/16/2018 04:05 AM, Mika Kuoppala wrote:
Oscar Mateo writes:
Revert to the legacy implementation.
v2: GEN7_ROW_CHICKEN2 is masked
v3:
- Rebased
- Renamed to Wa_2006611047
- A0 and B0 only
v4:
- Add spaces around '<<' (and fix the surrounding code as well)
- Mark the WA as
On Wed, May 16, 2018 at 02:14:56PM -0400, Harry Wentland wrote:
> On 2018-05-14 10:05 PM, Manasi Navare wrote:
> > This patch defines a new header file for all the DSC 1.2 structures
> > and creates a structure for PPS infoframe which will be used to send
> > picture parameter set secondary data pa
On Wed, May 16, 2018 at 10:21:10AM -0700, Lucas De Marchi wrote:
> This reverts commit c0cfb10d9e1de490e36d3b9d4228c0ea0ca30677.
>
> This fails on a Dell XPS13 9350 machine giving me just a black screen.
> [drm:intel_dp_start_link_train [i915]] [CONNECTOR:59:eDP-1] Link Training
> Passed at Link
On Wed, 2018-05-16 at 09:14 +0530, vathsala nagaraju wrote:
> On Wednesday 16 May 2018 04:33 AM, Dhinakaran Pandiyan wrote:
> >
> > On Mon, 2018-05-14 at 09:02 +0530, vathsala nagaraju wrote:
> > >
> > > From: Vathsala Nagaraju
> > >
> > > For psr block #9, the vbt description has moved to opti
On 2018-05-14 10:05 PM, Manasi Navare wrote:
> VESA Display Stream Compression is a specification for visually losless
> video compression over display links. The DSC standard also defines
> a picture parameter set (PPS) which encoder must communicate to decoders.
> This is done by encapsulating PP
On Wed, 2018-05-16 at 09:33 -0700, matthew.s.atw...@intel.com wrote:
> From: Matt Atwood
>
> According to DP spec (2.9.3.1 of DP 1.4) if
> EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in
> DPCD
> 02200h through 0220Fh shall contain the DPRX's true capability. These
> values wil
== Series Details ==
Series: series starting with [CI,1/4] drm/i915: Remove tasklet flush before
disable
URL : https://patchwork.freedesktop.org/series/43265/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4192_full -> Patchwork_9017_full =
== Summary - WARNING ==
Minor
On Wed, May 16, 2018 at 03:31:52PM -0700, Dhinakaran Pandiyan wrote:
> On Wed, 2018-05-16 at 09:33 -0700, matthew.s.atw...@intel.com wrote:
> > From: Matt Atwood
> >
> > According to DP spec (2.9.3.1 of DP 1.4) if
> > EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in
> > DPCD
> >
== Series Details ==
Series: series starting with [1/7] drm/i915: Remove tasklet flush before disable
URL : https://patchwork.freedesktop.org/series/43266/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4192_full -> Patchwork_9018_full =
== Summary - WARNING ==
Minor unkn
On Fri, 2018-05-11 at 16:00 -0700, Dhinakaran Pandiyan wrote:
> PSR hardware and hence the driver code for VLV and CHV deviates a lot
> from
> their DDI counterparts. While the feature has been disabled for a
> long time
> now, retaining support for these platforms is a maintenance burden.
> There
On Wed, 2018-05-16 at 11:01 +0300, Jani Nikula wrote:
> This reverts commit dc911f5bd8aacfcf8aabd5c26c88e04c837a938e.
>
> Per the report, no matter what display mode you select with xrandr,
> the
> i915 driver will always select the alternate fixed mode. For the
> reporter this means that the disp
Em Qui, 2018-05-10 às 14:59 -0700, Oscar Mateo escreveu:
> Stop reading some now deprecated interrupt registers in both
> debugfs and error state. Instead, read the new equivalents in the
> Gen11 interrupt repartitioning scheme.
>
> Note that the equivalent to the PM ISR & IIR cannot be read witho
== Series Details ==
Series: series starting with [CI,1/5] drm/i915: Remove tasklet flush before
disable
URL : https://patchwork.freedesktop.org/series/43267/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4193_full -> Patchwork_9019_full =
== Summary - WARNING ==
Minor
== Series Details ==
Series: drm/dp: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT
URL : https://patchwork.freedesktop.org/series/43275/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4193_full -> Patchwork_9020_full =
== Summary - WARNING ==
Minor unknown changes
== Series Details ==
Series: Revert "drm/i915/edp: Do not do link training fallback or prune modes
on EDP"
URL : https://patchwork.freedesktop.org/series/43278/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4193_full -> Patchwork_9021_full =
== Summary - WARNING ==
Mino
This patch fixes the original commit c0cfb10d9e1de49 ("drm/i915/edp:
Do not do link training fallback or prune modes on EDP") that causes
a blank screen in case of certain eDP panels (Eg: seen on Dell XPS13 9350)
where first link training fails and a retraining is required by falling
back to lower
== Series Details ==
Series: drm/i915/dp: Link train Fallback on eDP only if fallback link BW can
fit panel's native mode
URL : https://patchwork.freedesktop.org/series/43291/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
8c9689628d51 drm/i915/dp: Link train Fallback on eDP on
== Series Details ==
Series: drm/i915/dp: Link train Fallback on eDP only if fallback link BW can
fit panel's native mode
URL : https://patchwork.freedesktop.org/series/43291/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4193 -> Patchwork_9024 =
== Summary - FAILURE ==
== Series Details ==
Series: series starting with [CI,1/8] drm/i915: Remove tasklet flush before
disable
URL : https://patchwork.freedesktop.org/series/43279/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4193_full -> Patchwork_9022_full =
== Summary - WARNING ==
Minor
On 16 May 2018 at 01:37, Laurent Pinchart
wrote:
> Hello,
>
> On Tuesday, 15 May 2018 17:24:52 EEST kbuild test robot wrote:
>> tree: git://anongit.freedesktop.org/drm/drm-tip drm-tip
>> head: c03987223c762e4a61142f0a9be6027bb181cdfa
>> commit: 9037d4b98b255979c6636045794775f5a89cc623 [711/734
Quoting Patchwork (2018-05-17 05:05:32)
> == Series Details ==
>
> Series: series starting with [CI,1/8] drm/i915: Remove tasklet flush before
> disable
> URL : https://patchwork.freedesktop.org/series/43279/
> State : success
>
> == Summary ==
>
> = CI Bug Log - changes from CI_DRM_4193_full
== Series Details ==
Series: gpu: drm: i915: Change return type to vm_fault_t (rev4)
URL : https://patchwork.freedesktop.org/series/41893/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4193_full -> Patchwork_9023_full =
== Summary - WARNING ==
Minor unknown changes comin
replace PRIu64 to llu to fix -Wformat compile warning on android :
format specifies type 'unsigned long' but the argument has type
'__u64' (aka 'unsigned long long') [-Wformat]
Tests: compilation with warning clean
Signed-off-by: jenny cao
---
freedreno/msm/msm_ringbuffer.c |
On 17 May 2018 at 14:42, Dave Airlie wrote:
> On 16 May 2018 at 01:37, Laurent Pinchart
> wrote:
>> Hello,
>>
>> On Tuesday, 15 May 2018 17:24:52 EEST kbuild test robot wrote:
>>> tree: git://anongit.freedesktop.org/drm/drm-tip drm-tip
>>> head: c03987223c762e4a61142f0a9be6027bb181cdfa
>>> co
On Thu, May 17, 2018 at 12:48 AM, Chris Wilson wrote:
> Quoting Souptick Joarder (2018-05-16 20:12:20)
>> Use new return type vm_fault_t for fault handler. For
>> now, this is just documenting that the function returns
>> a VM_FAULT value rather than an errno. Once all instances
>> are converted,
> -Original Message-
> From: C, Ramalingam
> Sent: Wednesday, May 16, 2018 16:05
> To: Usyskin, Alexander ; intel-
> g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
> seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;
> jani.nik...@linux.intel.com; Winkler, Tom
> -Original Message-
> From: C, Ramalingam
> Sent: Wednesday, May 16, 2018 18:20
> To: Usyskin, Alexander ; intel-
> g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
> seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;
> jani.nik...@linux.intel.com; Winkler, Tom
> -Original Message-
> From: C, Ramalingam
> Sent: Wednesday, May 16, 2018 18:53
> To: Shankar, Uma ; intel-
> g...@lists.freedesktop.org; dri-de...@lists.freedesktop.org;
> seanp...@chromium.org; dan...@ffwll.ch; ch...@chris-wilson.co.uk;
> jani.nik...@linux.intel.com; Winkler, Tomas ;
>
> -Original Message-
> From: Usyskin, Alexander
> Sent: Thursday, May 17, 2018 11:29 AM
> To: C, Ramalingam ; Shankar, Uma
> ; intel-gfx@lists.freedesktop.org; dri-
> de...@lists.freedesktop.org; seanp...@chromium.org; dan...@ffwll.ch;
> ch...@chris-wilson.co.uk; jani.nik...@linux.intel.co
We can avoid the mmio read of the CSB pointers after reset based on the
knowledge that the HW always start writing at entry 0 in the CSB buffer.
We need to reset our CSB head tracking after GPU reset (and on
sanitization after resume) so that we are expecting to read from entry
0.
Signed-off-by: C
To ease the frequent and ugly pointer dance of
&request->gem_context->engine[request->engine->id] during request
submission, store that pointer as request->hw_context. One major
advantage that we will exploit later is that this decouples the logical
context state from the engine itself.
v2: Set mo
As we reset the GPU on suspend/resume, we also do need to reset the
engine state tracking so call into the engine backends. This is
especially important so that we can also sanitize the state tracking
across resume.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 27 +++
One usecase would be to couple in via EGL_NV_context_priority_realtime
in userspace to provide some QoS guarantees in conjunction with setting
the highest priority.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem_context.c| 22 ++
drivers/gpu/drm/i915/i915_gem_context.h
Move the knowledge about resetting the current context tracking on the
engine from inside i915_gem_context.c into intel_engine_cs.c
Signed-off-by: Chris Wilson
Reviewed-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/i915_gem_context.c | 12 ++--
drivers/gpu/drm/i915/intel_engine_cs.c | 23
As we now only use the cached HWSP access to read the CSB buffer and no
longer use any forcewaked mmio, processing the CSB is fast and possible
to do so directly from inside the CS interrupt handler.
We have to rearrange the irq handler slightly as we wish to preserve the
single threaded access to
Searching for an available hole by address is slow, as there no
guarantee that a hole will be available and so we must walk over all
nodes in the rbtree before we determine the search was futile. In many
cases, the caller doesn't strictly care for the highest available hole
and was just opportunist
As we are splitting processing the CSB events from submitting the ELSP,
we also need to duplicate the check that we hold a device wakeref for our
hardware access to the disjoint locations.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c | 26 --
1 file ch
In the next patch, we will process the CSB events directly from the CS
interrupt handler, being called for each interrupt. Hence, we will no
longer have the need for a loop until the has-interrupt bit is clear,
and in the meantime can remove that small optimisation.
Signed-off-by: Chris Wilson
--
The HWACK bit more generically solves the problem of resubmitting ESLP
while the hardware is still processing the current ELSP write. We no
longer need to check port[0].count itself.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_lrc.c | 2 --
1 file changed, 2 deletions(-)
diff --g
In the next patch, we will begin processing the CSB from inside the
interrupt handler. This means that updating the execlists->port[] will
no longer be locked by the tasklet but by the engine->timeline.lock
instead. Pull dequeue and submit under the same lock for protection.
(An alternative, future
Having abandoned the split approach of acking then handling the GT irqs
(sacrificed to use the interrupt handler to guaranteed exclusive access
to the irq data), pull the two routines into one to let the compiler
eliminate the redundant storage.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i9
In order to support engine reset from irq (timer) context, we need to be
able to re-initialise the breadcrumbs. So we need to promote the plain
spin_lock_irq to a safe spin_lock_irqsave.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_breadcrumbs.c | 5 +++--
1 file changed, 3 inserti
To be useful later, enable intel_engine_dump() to be called from irq
context (i.e. using saving and restoring irq start rather than assuming
we enter with irqs enabled).
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_engine_cs.c | 11 +++
1 file changed, 7 insertions(+), 4 de
Following the removal of the last workarounds, the only CSB mmio access
is for the old vGPU interface. The mmio registers presented by vGPU do
not require forcewake and can be treated as ordinary volatile memory,
i.e. they behave just like the HWSP access just at a different location.
We can reduce
Back in commit 27af5eea54d1 ("drm/i915: Move execlists irq handler to a
bottom half"), we came to the conclusion that running our CSB processing
and ELSP submission from inside the irq handler was a bad idea. A really
bad idea as we could impose nearly 1s latency on other users of the
system, on av
Install a timer when trying to preempt on behalf of an important
context such that if the active context does not honour the preemption
request within the desired timeout, then we reset the GPU to allow the
important context to run.
v2: Install the timer on scheduling the preempt request; long bef
As we keep an rbtree of available holes sorted by their size, we can
very easily determine if there is any hole large enough that might
satisfy the allocation request. This helps when dealing with a highly
fragmented address space and a request for a search by address.
To cache the largest size, w
Store whether or not we need to kick the guc's execlists emulation on
the engine itself to avoid chasing the device info.
gen8_cs_irq_handler 512 428 -84
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_irq.c | 4 +++-
drivers/gpu/drm/i915/i
Use a liberal timeout of 20ms to ensure that the rendering for an
interactive pageflip is started in a timely fashion, and that
user interaction is not blocked by GPU, or CPU, hogs. This is at the cost
of resetting whoever was blocking the preemption, likely leading to that
context/process being ba
As all backends implement the same pin_count mechanism and do a
dec-and-test as their first step, pull that into the common
intel_context_unpin(). This also pulls into the caller, eliminating the
indirect call in the usual steady state case. The intel_context_pin()
side is a little more complicated
Since intel_sideband_read and intel_sideband_write differ by only a
couple of lines (depending on whether we feed the value in or out),
merge the two into a single common accessor.
v2: Restore vlv_flisdsi_read() lost during rebasing.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/intel_si
With the vlv sideband fixed to avoid sleeping while we talk to the
punit, the system should be much more stable and be able to utilise the
punit without risk.
This reverts commit 6067a27d1f01 ("drm/i915: Avoid tweaking evaluation
thresholds on Baytrail v3")
References: 6067a27d1f01 ("drm/i915: Av
When circumstances allow, trying resetting the engine directly from the
preemption timeout handler. As this is softirq context, we have to be
careful both not to sleep and not to spin on anything we may be
interrupting (e.g. the submission tasklet).
Signed-off-by: Chris Wilson
Cc: Mika Kuoppala
We want to be able to reset the GPU from inside a timer callback
(hardirq context). One step requires us to copy the default context
state over to the guilty context, which means we need to plan in advance
to have that object accessible from within an atomic context. The atomic
context prevents us
In the next patch, we want to store the intel_context pointer inside
i915_request, as it is frequently access via a convoluted dance when
submitting the request to hw. Having two context pointers inside
i915_request leads to confusion so first rename the existing
i915_gem_context pointer to i915_re
Since all the RPS handling code is in intel_gt_pm, move the irq handlers
there as well so that it all contained within one file.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 4 -
drivers/gpu/drm/i915/i915_irq.c | 314 +++-
drivers/gpu/dr
As we want to be able to call i915_reset_engine and co from a softirq or
timer context, we need to be irqsafe at all timers. So we have to forgo
the simple spin_lock_irq for the full spin_lock_irqsave.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_gem.c | 6 --
1 file changed, 4
Currently the purgeable objects, I915_MADV_DONTNEED, as mixed in the
normal bound/unbound lists. Every shrinker pass starts with an attempt
to purge from this set of unneeded objects, which entails us doing a
walk over both lists looking for any candidates. If there are none, and
since we are shrin
These routines are identical except in the nature of the value parameter.
For writes it is a pure in-param, but for a read, we need an out-param.
Since they differ in a single line, merge the two routines into one.
Signed-off-by: Chris Wilson
Reviewed-by: Imre Deak
---
drivers/gpu/drm/i915/inte
Currently, we try to report to the shrinker the precise number of
objects (pages) that are available to be reaped at this moment. This
requires searching all objects with allocated pages to see if they
fulfill the search criteria, and this count is performed quite
frequently. (The shrinker tries to
Ironlake does support being able to saving and reloading context specific
registers between contexts, providing isolation of the basic GPU state
(as programmable by userspace). This allows userspace to assume that the
GPU retains their state from one batch to the next, minimising the
amount of stat
The choice of preemption timeout is determined by the context from which
we trigger the preemption, as such allow the caller to specify the
desired timeout.
Effectively the other choice would be to use the shortest timeout along
the dependency chain. However, given that we would have already
trigg
We now have two locks for sideband access. The general one covering
sideband access across all generation, sb_lock, and a specific one
covering sideband access via the punit on vlv/chv. After lifting the
sb_lock around the punit into the callers, the pcu_lock is now redudant
and can be separated fr
Currently Ironlake operates under the assumption that rpm awake (and its
error checking is disabled). As such, we have missed a few places where we
access registers without taking the rpm wakeref and thus trigger
warnings. intel_ips being one culprit.
As this involved adding a potentially sleeping
As we now employ a very heavy pm_qos around the punit access, we want to
minimise the number of synchronous requests by performing one for the
whole punit sequence rather than around individual accesses. The
sideband lock is used for this, so push the pm_qos into the sideband
lock acquisition and r
Avoid looking at the magical engines[RCS] to decide if the HW and driver
supports logical contexts, and instead record that knowledge during
initialisation.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_gem_context.c | 5 ++---
drivers
To no surprise (since we've flip-flopped over the use of PIN_HIGH a few
times), doing a search by address over a pathologically fragmented
address space is exceeding slow. To protect ourselves from nearly
unbounded latency (think searching a million holes while under
struct_mutex), limit the search
Lift the sideband acquisition for vlv_punit_read and vlv_punit_write
into their callers, so that we can lock the sideband once for a sequence
of operations, rather than perform the heavyweight acquisition on each
request.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c |
The RPS worker exists to do the bidding of the GT powermanagement, so
move it from i915_irq to intel_gt_pm.c where it can be hidden from the
rest of the world. The goal being that the RPS worker is the one true
way though which all RPS updates are coordinated.
Signed-off-by: Chris Wilson
Reviewed
For consistency (and elegance!), add intel_device_info.has_rps.
The immediate boon is that RPS support is now emitted along the other
capabilities in the debug log and after errors.
Signed-off-by: Chris Wilson
Reviewed-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/i915_drv.h | 2 ++
Since commit b7137e0cf1e5 ("drm/i915: Defer enabling rc6 til after we
submit the first batch/context"), intel_suspend_gt_powersave() has been
a no-op. As we still do not need to do anything explicitly on suspend
(we do everything required on idling), remove the defunct function.
References: b7137e
sandybride_pcode is another sideband, so move it to their new home.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_drv.h | 10 --
drivers/gpu/drm/i915/intel_hdcp.c | 3 +-
drivers/gpu/drm/i915/intel_pm.c | 194 --
drivers/gpu/drm/i915/intel_s
On Ironlake, we are required to not enable rc6 until the GPU is loaded
with a valid context; after that point it can start to use a powersaving
context for rc6. This seems a reasonable requirement to impose on all
generations as we are already priming the system by loading a context on
resume. We c
While we talk to the punit over its sideband, we need to prevent the cpu
from sleeping in order to prevent a potential machine hang.
Note that by itself, it appears that pm_qos_update_request (via
intel_idle) doesn't provide a sufficient barrier to ensure that all core
are indeed awake (out of Cst
When choosing the initial frequency in intel_gt_pm_busy() we also need
to calculate the current min/max bounds. As this calculation is going to
become more complex with the intersection of several different limits,
refactor it to a common function. The alternative wold be to feed the
initial recloc
Broadwater and the rest of gen4 do support being able to saving and
reloading context specific registers between contexts, providing isolation
of the basic GPU state (as programmable by userspace). This allows
userspace to assume that the GPU retains their state from one batch to the
next, minimis
Valleyview and Cherryview update the GPU frequency via the punit, which
is very expensive as we have to ensure the cores do not sleep during the
comms. If we perform frequent RPS evaluations, the frequent punit
requests cause measurable system overhead for little benefit, so
increase the evaluation
Try to order the intel_gt_pm code to match the order it is used:
init
enable
disable
cleanup
Signed-off-by: Chris Wilson
Reviewed-by: Sagar Arun Kamble
---
drivers/gpu/drm/i915/intel_gt_pm.c | 170 ++---
drivers/gpu/drm/i915/intel_gt_pm.h
As i915_gem_object_phys_attach() wants to play dirty and mess around
with obj->mm.pages itself (replacing the shmemfs with a DMA allocation),
refactor the gubbins so into i915_gem_object_unset_pages() that we don't
have to duplicate all the secrets.
Signed-off-by: Chris Wilson
Cc: Joonas Lahtinen
Split the sideback declarations out of the ginormous i915_drv.h
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +
drivers/gpu/drm/i915/i915_drv.h | 63 -
drivers/gpu/drm/i915/i915_sysfs.c | 2 +
drivers/gpu/drm/i915/intel_cdclk.c
As we know that whenever the GT is awake, rc6 and rps are enabled (if
available), then we can remove the individual tracking and enabling to
the gen6_rps_busy/gen6_rps_idle() (now called intel_gt_pm_busy and
intel_gt_pm_idle) entry points.
Signed-off-by: Chris Wilson
---
drivers/gpu/drm/i915/i91
While we believe that we need to always reset the GPU to scrub the state
on transition to/from the driver, it is essential when we enable contexts.
Generalize the gen test to be on context-support instead.
References: d2b4b97933f5 ("drm/i915: Record the default hw state after reset
upon load"
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